},
.stats = {
.bin_uV = 10000, /* 10mV */
- }
+ },
+ .version = "P4.25",
};
static struct dvfs_rail tegra12_dvfs_rail_vdd_core = {
.step_up = 1400,
.vmin_cdev = &core_vmin_cdev,
.vmax_cdev = &core_vmax_cdev,
+ .stats = {
+ .bin_uV = 10000, /* 10mV */
+ },
+ .version = "P4.26",
};
static struct dvfs_rail tegra12_dvfs_rail_vdd_gpu = {
},
.stats = {
.bin_uV = 10000, /* 10mV */
- }
+ },
+ .version = "P4.28",
};
static struct dvfs_rail *tegra12_dvfs_rails[] = {
CORE_DVFS("host1x", 0, 1, 1, KHZ, 108000, 156000, 204000, 252000, 348000, 384000, 408000, 408000, 408000),
CORE_DVFS("host1x", 1, -1, 1, KHZ, 108000, 156000, 204000, 252000, 348000, 384000, 444000, 444000, 444000),
- CORE_DVFS("vi", 0, 0, 1, KHZ, 228000, 408000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("vi", 0, 1, 1, KHZ, 228000, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("vi", 1, -1, 1, KHZ, 228000, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("vi", 0, 0, 1, KHZ, 1, 408000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("vi", 0, 1, 1, KHZ, 1, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("vi", 1, -1, 1, KHZ, 1, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("isp", 0, 0, 1, KHZ, 228000, 408000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("isp", 0, 1, 1, KHZ, 228000, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("isp", 1, -1, 1, KHZ, 228000, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("isp", 0, 0, 1, KHZ, 1, 408000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("isp", 0, 1, 1, KHZ, 1, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("isp", 1, -1, 1, KHZ, 1, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
#ifdef CONFIG_TEGRA_DUAL_CBUS
CORE_DVFS("c2bus", 0, 0, 1, KHZ, 120000, 216000, 288000, 336000, 384000, 432000, 456000, 456000, 480000),
CORE_DVFS("cbus", -1, -1, 1, KHZ, 120000, 144000, 168000, 168000, 216000, 216000, 372000, 372000, 372000),
#endif
- CORE_DVFS("c4bus", 0, 0, 1, KHZ, 228000, 408000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("c4bus", 0, 1, 1, KHZ, 228000, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
- CORE_DVFS("c4bus", 1, -1, 1, KHZ, 228000, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("c4bus", 0, 0, 1, KHZ, 1, 408000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("c4bus", 0, 1, 1, KHZ, 1, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
+ CORE_DVFS("c4bus", 1, -1, 1, KHZ, 1, 420000, 480000, 600000, 600000, 600000, 600000, 600000, 600000),
CORE_DVFS("pll_m", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1200000, 1200000, 1200000),
CORE_DVFS("pll_c", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
/* Core voltages (mV): 800, 850, 900, 950, 1000, 1050, 1100, 1110, 1150 */
/* Clock limits for I/O peripherals */
+ CORE_DVFS("dsia", -1, -1, 1, KHZ, 500000, 500000, 750000, 750000, 750000, 750000, 750000, 750000, 750000),
+ CORE_DVFS("dsib", -1, -1, 1, KHZ, 500000, 500000, 750000, 750000, 750000, 750000, 750000, 750000, 750000),
+ CORE_DVFS("dsialp", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 156000, 156000, 156000, 156000, 156000),
+ CORE_DVFS("dsiblp", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 156000, 156000, 156000, 156000, 156000),
CORE_DVFS("hdmi", -1, -1, 1, KHZ, 1, 148500, 148500, 297000, 297000, 297000, 297000, 297000, 297000),
CORE_DVFS("pciex", -1, -1, 1, KHZ, 1, 250000, 250000, 500000, 500000, 500000, 500000, 500000, 500000),