SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO | \
SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
+#define IS_QUIRKS2_DELAYED_CLK_GATE(host) \
+ (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
+
/* Interface voltages */
#define SDHOST_1V8_OCR_MASK 0x8
#define SDHOST_HIGH_VOLT_MIN 2700000
saved_line = __LINE__;
goto err_node;
}
+ if (IS_QUIRKS2_DELAYED_CLK_GATE(host)) {
+ host->clk_gate_tmout_ticks = -1;
+ if (!debugfs_create_u32("clk_gate_tmout_ticks",
+ S_IRUGO | S_IWUSR,
+ root, (u32 *)&host->clk_gate_tmout_ticks)) {
+ saved_line = __LINE__;
+ goto err_node;
+ }
+ }
+
return;
err_node:
#define MAX_TUNING_LOOP 40
-#define SDIO_CLK_GATING_TICK_TMOUT (HZ / 50)
+#define SDIO_CLK_GATING_TICK_TMOUT (HZ / 1000) /* 1msec timeout */
+#define EMMC_CLK_GATING_TICK_TMOUT (HZ / 50) /* 20msec timeout */
+
+#define IS_SDIO_CARD(host) \
+ (host->mmc->card && \
+ (host->mmc->card->type == MMC_TYPE_SDIO))
+
+#define IS_EMMC_CARD(host) \
+ (host->mmc->card && \
+ (host->mmc->card->type == MMC_TYPE_MMC))
#define IS_SDIO_CARD_OR_EMMC(host) \
(host->mmc->card && \
return 0;
if (IS_DELAYED_CLK_GATE(host)) {
- if (host->is_clk_on)
- schedule_delayed_work(&host->delayed_clk_gate_wrk,
- SDIO_CLK_GATING_TICK_TMOUT);
+ if (host->is_clk_on) {
+ if (IS_SDIO_CARD(host))
+ host->clk_gate_tmout_ticks =
+ SDIO_CLK_GATING_TICK_TMOUT;
+ else if (IS_EMMC_CARD(host))
+ host->clk_gate_tmout_ticks =
+ EMMC_CLK_GATING_TICK_TMOUT;
+ if (host->clk_gate_tmout_ticks > 0)
+ schedule_delayed_work(
+ &host->delayed_clk_gate_wrk,
+ host->clk_gate_tmout_ticks);
+ }
return 0;
}