dvfs: tegra: Separate DFLL tune/resume ramp delays

Macro CL_DVFS_OUTPUT_RAMP_DELAY was used to specify two different ramp
delays: ramp across DFLL low voltage tuning range, and forced output
ramp during DFLL resume. Replaced this macro with two separate platform
configuration settings, optionally initialized from DT. Kept macro as
default fall-back in case when DT does not specify any of the added
ramp delays.

Bug 1632845

Change-Id: I43e7b1ea9e2202de808e2c031542843098e8d93e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/734556
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/drivers/platform/tegra/tegra_cl_dvfs.c b/drivers/platform/tegra/tegra_cl_dvfs.c
index d00f9f31376eefcd060ca6d395f04a1a0bdb952a..33fd894ae87db1ae553e9a00a86ce238e83fab2a 100644 (file)
--- a/drivers/platform/tegra/tegra_cl_dvfs.c
+++ b/drivers/platform/tegra/tegra_cl_dvfs.c
@@ -266,6 +266,7 @@ struct tegra_cl_dvfs {
 
        struct hrtimer                  tune_timer;
        ktime_t                         tune_delay;
+       ktime_t                         tune_ramp;
        u8                              tune_out_last;
 
        struct timer_list               calibration_timer;
@@ -988,10 +989,8 @@ static enum hrtimer_restart tune_timer_cb(struct hrtimer *timer)
                if ((cld->tune_out_last == cld->num_voltages) &&
                    (out_last >= cld->tune_high_out_min)  &&
                    (out_min >= cld->tune_high_out_min)) {
-                       ktime_t ramp_delay =
-                               ktime_set(0, CL_DVFS_OUTPUT_RAMP_DELAY * 1000);
                        set_tune_state(cld, TEGRA_CL_DVFS_TUNE_HIGH_REQUEST_2);
-                       hrtimer_start(&cld->tune_timer, ramp_delay,
+                       hrtimer_start(&cld->tune_timer, cld->tune_ramp,
                                      HRTIMER_MODE_REL);
                } else {
                        hrtimer_start(&cld->tune_timer, cld->tune_delay,
@@ -1912,6 +1911,13 @@ static int cl_dvfs_init(struct tegra_cl_dvfs *cld)
        hrtimer_init(&cld->tune_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
        cld->tune_timer.function = tune_timer_cb;
        cld->tune_delay = ktime_set(0, CL_DVFS_TUNE_HIGH_DELAY * 1000);
+       if (!cld->p_data->tune_ramp_delay)
+               cld->p_data->tune_ramp_delay = CL_DVFS_OUTPUT_RAMP_DELAY;
+       cld->tune_ramp = ktime_set(0, cld->p_data->tune_ramp_delay * 1000);
+
+       /* init forced output resume delay */
+       if (!cld->p_data->resume_ramp_delay)
+               cld->p_data->resume_ramp_delay = CL_DVFS_OUTPUT_RAMP_DELAY;
 
        /* init calibration timer */
        init_timer_deferrable(&cld->calibration_timer);
@@ -1987,7 +1993,7 @@ void tegra_cl_dvfs_resume(struct tegra_cl_dvfs *cld)
                    !cld->safe_dvfs->dfll_data.is_bypass_down()) {
                        cl_dvfs_wmb(cld);
                        output_enable(cld);
-                       udelay(CL_DVFS_OUTPUT_RAMP_DELAY);
+                       udelay(cld->p_data->resume_ramp_delay);
                }
        }
 }
@@ -2724,6 +2730,9 @@ static int cl_dvfs_dt_parse_pdata(struct platform_device *pdev,
        p_data->flags = flags;
        dev_dbg(&pdev->dev, "DT: flags: 0x%x\n", p_data->flags);
 
+       OF_READ_U32_OPT(dn, tune-ramp-delay, p_data->tune_ramp_delay);
+       OF_READ_U32_OPT(dn, resume-ramp-delay, p_data->resume_ramp_delay);
+
        /* pmic integration */
        i2c_dn = of_parse_phandle(dn, "i2c-pmic-integration", 0);
        pwm_dn = of_get_child_by_name(dn, "pwm-pmic-integration");

diff --git a/include/linux/platform/tegra/tegra_cl_dvfs.h b/include/linux/platform/tegra/tegra_cl_dvfs.h
index bc3b4ee898943b85f49a313f9b58858f16ffebfd..d757721bf982d23d7d730db8b393c86def399fe7 100644 (file)
--- a/include/linux/platform/tegra/tegra_cl_dvfs.h
+++ b/include/linux/platform/tegra/tegra_cl_dvfs.h
@@ -114,6 +114,8 @@ struct tegra_cl_dvfs_platform_data {
        struct voltage_reg_map  *vdd_map;
        int                     vdd_map_size;
        int                     pmu_undershoot_gb;
+       int                     resume_ramp_delay;
+       int                     tune_ramp_delay;
 
        struct tegra_cl_dvfs_cfg_param          *cfg_param;
 };