unsigned long ret;
BUG_ON(!nvhost_module_powered_ext(dc->ndev));
- if (!tegra_is_clk_enabled(dc->clk))
- WARN(1, "DC is clock-gated.\n");
+
+ if (WARN(!tegra_is_clk_enabled(dc->clk), "DC is clock-gated.\n") ||
+ WARN(!tegra_powergate_is_powered(dc->powergate_id),
+ "DC is power-gated.\n"))
+ return 0;
ret = readl(dc->base + reg * 4);
trace_display_readl(dc, ret, dc->base + reg * 4);
unsigned long reg)
{
BUG_ON(!nvhost_module_powered_ext(dc->ndev));
- if (!tegra_is_clk_enabled(dc->clk))
- WARN(1, "DC is clock-gated.\n");
+
+ if (WARN(!tegra_is_clk_enabled(dc->clk), "DC is clock-gated.\n") ||
+ WARN(!tegra_powergate_is_powered(dc->powergate_id),
+ "DC is power-gated.\n"))
+ return;
trace_display_writel(dc, val, dc->base + reg * 4);
writel(val, dc->base + reg * 4);