*
* Tegra Graphics Host Driver Entrypoint
*
- * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
int nb_channels; /* host1x: num channels supported */
int nb_pts; /* host1x: num syncpoints supported */
int nb_bases; /* host1x: num syncpoints supported */
- u64 client_managed; /* host1x: client managed syncpts */
int nb_mlocks; /* host1x: number of mlocks */
- const char **syncpt_names; /* names of sync points */
};
struct nvhost_master {
*
* Tegra Graphics Host Syncpoints for HOST1X
*
- * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2010-2014, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
static const char *t20_syncpt_name(struct nvhost_syncpt *sp, u32 id)
{
- struct host1x_device_info *info = &syncpt_to_dev(sp)->info;
- const char *name = NULL;
-
- if (id < info->nb_pts)
- name = info->syncpt_names[id];
-
+ const char *name = sp->syncpt_names[id];
return name ? name : "";
}
for (i = 0; i < NVHOST_MODULE_MAX_SYNCPTS && pdata->syncpts[i]; ++i)
ret |= (pdata->syncpts[i] == id);
- if (!ret || (id == NVSYNCPT_2D_0))
+ if (!ret)
return NVSYNCPT_INVALID;
return pdata->waitbases[0];
},
};
-static const char *s_syncpt_names[32] = {
- "gfx_host",
- "", "", "", "", "", "", "",
- "disp0_a", "disp1_a", "avp_0",
- "csi_vi_0", "csi_vi_1",
- "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
- "2d_0", "2d_1",
- "disp0_b", "disp1_b",
- "3d",
- "msenc",
- "disp0_c", "disp1_c",
- "vblank0", "vblank1",
- "tsec", "msenc_unused",
- "2d_tinyblt",
- "dsi"
-};
-
static struct host1x_device_info host1x02_info = {
.nb_channels = 9,
.nb_pts = 32,
.nb_mlocks = 16,
.nb_bases = 12,
- .syncpt_names = s_syncpt_names,
- .client_managed = NVSYNCPTS_CLIENT_MANAGED,
};
struct nvhost_device_data t11_host1x_info = {
*
* Tegra Graphics Host Syncpoints for T124
*
- * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
#include <linux/nvhost.h>
-#define NVSYNCPT_GK20A_BASE 64
-/* following is base + number of gk20a channels. TODO: remove magic */
-#define NVSYNCPT_GK20A_LAST (NVSYNCPT_GK20A_BASE + 127)
-
-#define NV_VI_0_SYNCPTS { \
- NVSYNCPT_VI_0_0, \
- NVSYNCPT_VI_0_1, \
- NVSYNCPT_VI_0_2, \
- NVSYNCPT_VI_0_3, \
- NVSYNCPT_VI_0_4}
-
-#define NV_VI_1_SYNCPTS { \
- NVSYNCPT_VI_1_0, \
- NVSYNCPT_VI_1_1, \
- NVSYNCPT_VI_1_2, \
- NVSYNCPT_VI_1_3, \
- NVSYNCPT_VI_1_4}
-
-#define NV_ISP_0_SYNCPTS {\
- NVSYNCPT_ISP_0_0, \
- NVSYNCPT_ISP_0_1, \
- NVSYNCPT_ISP_0_2, \
- NVSYNCPT_ISP_0_3}
-
-#define NV_ISP_1_SYNCPTS {\
- NVSYNCPT_ISP_1_0, \
- NVSYNCPT_ISP_1_1, \
- NVSYNCPT_ISP_1_2, \
- NVSYNCPT_ISP_1_3}
-
#define NVWAITBASE_3D (3)
#define NVWAITBASE_MSENC (4)
#define NVWAITBASE_TSEC (5)
#define GK20A_DEV_NAME_SIZE 5
-#define BIT64(nr) (1ULL << (nr))
-#define NVSYNCPTS_CLIENT_MANAGED_T124 ( \
- BIT64(NVSYNCPT_DISP0_A) | BIT64(NVSYNCPT_DISP1_A) | \
- BIT64(NVSYNCPT_DISP0_B) | BIT64(NVSYNCPT_DISP1_B) | \
- BIT64(NVSYNCPT_DISP0_C) | BIT64(NVSYNCPT_DISP1_C) | \
- BIT(NVSYNCPT_DISP0_D) | \
- BIT(NVSYNCPT_DISP0_H) | BIT(NVSYNCPT_DISP1_H) | \
- BIT64(NVSYNCPT_DSI) | \
- BIT64(NVSYNCPT_VBLANK0) | BIT64(NVSYNCPT_VBLANK1) | \
- BIT64(NVSYNCPT_AVP_0))
-
/* Host1x driver matches module IDs while setting a
* particular clock, This ID is used for EMC module.
*/
},
};
-static const char *s_syncpt_names[NV_HOST1X_SYNCPT_NB_PTS] = {
- [NVSYNCPT_ISP_0_0] = "ispa_memory",
- [NVSYNCPT_ISP_0_1] = "ispa_stats",
- [NVSYNCPT_ISP_0_2] = "ispa_stream",
- [NVSYNCPT_ISP_0_3] = "ispa_loadv",
- [NVSYNCPT_ISP_1_0] = "ispb_memory",
- [NVSYNCPT_ISP_1_1] = "ispb_stats",
- [NVSYNCPT_ISP_1_2] = "ispb_stream",
- [NVSYNCPT_ISP_1_3] = "ispb_loadv",
- [NVSYNCPT_VI_0_0] = "vi0_ispa",
- [NVSYNCPT_VI_0_1] = "vi0_ispb",
- [NVSYNCPT_VI_0_2] = "vi0_stream",
- [NVSYNCPT_VI_0_3] = "vi0_memory",
- [NVSYNCPT_VI_0_4] = "vi0_flash",
- [NVSYNCPT_VI_1_0] = "vi1_ispa",
- [NVSYNCPT_VI_1_1] = "vi1_ispb",
- [NVSYNCPT_VI_1_2] = "vi1_stream",
- [NVSYNCPT_VI_1_3] = "vi1_memory",
- [NVSYNCPT_VI_1_4] = "vi1_flash",
- [NVSYNCPT_3D] = "3d",
- [NVSYNCPT_MPE] = "mpe",
- [NVSYNCPT_MPE_EBM_EOF] = "mpe_ebm_eof",
- [NVSYNCPT_MPE_WR_SAFE] = "mpe_wr_safe",
- [NVSYNCPT_VIC] = "vic",
- [NVSYNCPT_TSEC] = "tsec",
- [NVSYNCPT_DISP0_A] = "disp0",
- [NVSYNCPT_DISP1_A] = "disp1",
- [NVSYNCPT_AVP_0] = "avp",
- [NVSYNCPT_DISP0_B] = "disp0b",
- [NVSYNCPT_DISP1_B] = "disp1b",
- [NVSYNCPT_DISP0_C] = "disp0c",
- [NVSYNCPT_DISP1_C] = "disp1c",
- [NVSYNCPT_DISP0_D] = "disp0d",
- [NVSYNCPT_DISP0_H] = "disp0h",
- [NVSYNCPT_DISP1_H] = "disp1h",
- [NVSYNCPT_VBLANK0] = "vblank0",
- [NVSYNCPT_VBLANK1] = "vblank1",
- [NVSYNCPT_DSI] = "dsi",
-};
-
static struct host1x_device_info host1x04_info = {
.nb_channels = T124_NVHOST_NUMCHANNELS,
.nb_pts = NV_HOST1X_SYNCPT_NB_PTS,
.nb_mlocks = NV_HOST1X_NB_MLOCKS,
.nb_bases = NV_HOST1X_SYNCPT_NB_BASES,
- .syncpt_names = s_syncpt_names,
- .client_managed = NVSYNCPTS_CLIENT_MANAGED_T124,
};
struct nvhost_device_data t124_host1x_info = {
int err;
struct t124 *t124 = 0;
- for (i = NVSYNCPT_GK20A_BASE; i <= NVSYNCPT_GK20A_LAST; i++)
- s_syncpt_names[i] = "gk20a";
-
/* don't worry about cleaning up on failure... "remove" does it. */
err = nvhost_init_t124_channel_support(host, op);
if (err)
},
};
-static const char *s_syncpt_names[48] = {
- "gfx_host",
- "", "", "", "", "", "", "",
- "disp0_a", "disp1_a", "avp_0",
- "csi_vi_0", "csi_vi_1",
- "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
- "2d_0", "2d_1",
- "disp0_b", "disp1_b",
- "3d",
- "msenc",
- "disp0_c", "disp1_c",
- "vblank0", "vblank1",
- "tsec", "msenc_unused",
- "2d_tinyblt",
- "dsi"
-};
-
static struct host1x_device_info host1x03_info = {
.nb_channels = 12,
.nb_pts = 48,
.nb_mlocks = 16,
.nb_bases = 12,
- .syncpt_names = s_syncpt_names,
- .client_managed = NVSYNCPTS_CLIENT_MANAGED,
};
struct nvhost_device_data t14_host1x_info = {
#define NVSYNCPT_INVALID (-1)
#define NVSYNCPT_GRAPHICS_HOST (0) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP0_D (5) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP0_H (6) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP1_H (7) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP0_A (8) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP1_A (9) /* t20, t30, t114, t148 */
-#define NVSYNCPT_AVP_0 (10) /* t20, t30, t114, t148 */
-#define NVSYNCPT_CSI_VI_0 (11) /* t20, t30, t114, t148 */
-#define NVSYNCPT_CSI_VI_1 (12) /* t20, t30, t114, t148 */
-#define NVSYNCPT_VI_ISP_0 (13) /* t20, t30, t114, t148 */
-#define NVSYNCPT_VI_ISP_1 (14) /* t20, t30, t114, t148 */
-#define NVSYNCPT_VI_ISP_2 (15) /* t20, t30, t114, t148 */
-#define NVSYNCPT_VI_ISP_3 (16) /* t20, t30, t114, t148 */
-#define NVSYNCPT_VI_ISP_4 (17) /* t20, t30, t114, t148 */
-#define NVSYNCPT_2D_0 (18) /* t20, t30, t114, t148 */
-#define NVSYNCPT_VIC (18) /* t124 */
-#define NVSYNCPT_2D_1 (19) /* t20, t30, t114, t148 */
-#define NVSYNCPT_MSENC_SLICE (19) /* t124 */
-#define NVSYNCPT_DISP0_B (20) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP1_B (21) /* t20, t30, t114, t148 */
-#define NVSYNCPT_3D (22) /* t20, t30, t114, t148 */
-#define NVSYNCPT_MPE (23) /* t20, t30 */
-#define NVSYNCPT_MSENC (23) /* t114, t148 */
-#define NVSYNCPT_DISP0_C (24) /* t20, t30, t114, t148 */
-#define NVSYNCPT_DISP1_C (25) /* t20, t30, t114, t148 */
+
#define NVSYNCPT_VBLANK0 (26) /* t20, t30, t114, t148 */
#define NVSYNCPT_VBLANK1 (27) /* t20, t30, t114, t148 */
-#define NVSYNCPT_MPE_EBM_EOF (28) /* t20, t30 */
-#define NVSYNCPT_TSEC (28) /* t114, t148 */
-#define NVSYNCPT_MPE_WR_SAFE (29) /* t20, t30 */
-#define NVSYNCPT_DSI (31) /* t20, t30, t114, t148 */
-#define NVSYNCPT_ISP_0_0 (32) /* t124 */
-#define NVSYNCPT_ISP_0_1 (33) /* t124 */
-#define NVSYNCPT_ISP_0_2 (34) /* t124 */
-#define NVSYNCPT_ISP_0_3 (35) /* t124 */
-#define NVSYNCPT_ISP_1_0 (36) /* t124 */
-#define NVSYNCPT_ISP_1_1 (37) /* t124 */
-#define NVSYNCPT_ISP_1_2 (38) /* t124 */
-#define NVSYNCPT_ISP_1_3 (39) /* t124 */
-#define NVSYNCPT_VI_0_0 (40) /* t124 */
-#define NVSYNCPT_VI_0_1 (41) /* t124 */
-#define NVSYNCPT_VI_0_2 (42) /* t124 */
-#define NVSYNCPT_VI_0_3 (43) /* t124 */
-#define NVSYNCPT_VI_0_4 (44) /* t124 */
-#define NVSYNCPT_VI_1_0 (45) /* t124 */
-#define NVSYNCPT_VI_1_1 (46) /* t124 */
-#define NVSYNCPT_VI_1_2 (47) /* t124 */
-#define NVSYNCPT_VI_1_3 (48) /* t124 */
-#define NVSYNCPT_VI_1_4 (49) /* t124 */
#define NVWAITBASE_2D_0 (1) /* t20, t30, t114 */
#define NVWAITBASE_2D_1 (2) /* t20, t30, t114 */
#define NVMODMUTEX_VIC (10) /* t124 */
#define NVMODMUTEX_VI_1 (11) /* t124 */
-/* sync points that are wholly managed by the client */
-#define NVSYNCPTS_CLIENT_MANAGED ( \
- BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) | \
- BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) | \
- BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) | \
- BIT(NVSYNCPT_DISP0_D) | \
- BIT(NVSYNCPT_DISP0_H) | BIT(NVSYNCPT_DISP1_H) | \
- BIT(NVSYNCPT_DSI) | \
- BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1) | \
- BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) | \
- BIT(NVSYNCPT_VI_ISP_1) | BIT(NVSYNCPT_VI_ISP_2) | \
- BIT(NVSYNCPT_VI_ISP_3) | BIT(NVSYNCPT_VI_ISP_4) | \
- BIT(NVSYNCPT_MPE_EBM_EOF) | BIT(NVSYNCPT_MPE_WR_SAFE) | \
- BIT(NVSYNCPT_2D_1) | BIT(NVSYNCPT_AVP_0))
-
enum nvhost_power_sysfs_attributes {
NVHOST_POWER_SYSFS_ATTRIB_CLOCKGATE_DELAY = 0,
NVHOST_POWER_SYSFS_ATTRIB_POWERGATE_DELAY,
projects / sojka / nv-tegra / linux-3.10.git / commitdiff