]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
platform: tegra: iommu: split dc.0 & dc.1 domains
authorBibek Basu <bbasu@nvidia.com>
Wed, 15 Jul 2015 11:21:38 +0000 (16:51 +0530)
committerBibek Basu <bbasu@nvidia.com>
Fri, 17 Jul 2015 04:37:32 +0000 (21:37 -0700)
arm_iommu_create_mapping dosent happen for dc.1
since we have only one domain for dc0 and dc1.As a result
dma_map_linear_attrs fails. To fix this split domains for dc.0
with swgid 0x404 (DC | DC12) and dc.1 with swgid 0x8 (DCB)

Bug 200093600

Change-Id: I40411eb8fb53519b29a2a0e9e24bd001fa144c8d
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/770452
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
arch/arm64/boot/dts/tegra210-soc-base.dtsi
drivers/platform/tegra/iommu.c

index 09d8366e1671578dfd0fd98fccaff736ded9cf77..edd4fc1cc4b22d1eac52f0a2d1cc8d407ade2660 100644 (file)
                domains = <&ppcs_as TEGRA_SWGROUP_CELLS5(PPCS, PPCS1, PPCS2, SE, SE1)
                           &gpu_as TEGRA_SWGROUP_CELLS(GPUB)
                           &ape_as TEGRA_SWGROUP_CELLS(APE)
-                          &dc_as TEGRA_SWGROUP_CELLS3(DC, DC12, DCB)
+                          &dc_as TEGRA_SWGROUP_CELLS2(DC, DC12)
+                          &dc_as TEGRA_SWGROUP_CELLS(DCB)
                           &common_as TEGRA_SWGROUP_CELLS(AFI)
                           &common_as TEGRA_SWGROUP_CELLS(SDMMC1A)
                           &common_as TEGRA_SWGROUP_CELLS(SDMMC2A)
                        reg = <0x0 0x54200000 0x0 0x00040000>;
                        interrupts = <0 73 0x04>;
                        iommus = <&smmu TEGRA_SWGROUP_DC>,
-                                <&smmu TEGRA_SWGROUP_DC12>,
-                                <&smmu TEGRA_SWGROUP_DCB>;
+                                <&smmu TEGRA_SWGROUP_DC12>;
                        status = "disabled";
 
                        rgb {
                        power-domains = <&mc_clk_pd>;
                        reg = <0x0 0x54240000 0x0 0x00040000>;
                        interrupts = <0 74 0x04>;
-                       iommus = <&smmu TEGRA_SWGROUP_DC>,
-                                <&smmu TEGRA_SWGROUP_DC12>,
-                                <&smmu TEGRA_SWGROUP_DCB>;
+                       iommus = <&smmu TEGRA_SWGROUP_DCB>;
                        status = "disabled";
 
                        rgb {
index 7cf13f71affc45cd93fa7eb3ea87fc5a1d1d6b5b..7ca96e774506f69c8edaf569a9375c320b6673a7 100644 (file)
@@ -165,11 +165,9 @@ static struct swgid_fixup tegra_swgid_fixup_t210[] = {
                                                  TEGRA_SWGROUP_BIT(PPCS1) |
          TEGRA_SWGROUP_BIT(PPCS2), },
        { .name = "tegradc.0", .swgids = TEGRA_SWGROUP_BIT(DC) |
-                                        TEGRA_SWGROUP_BIT(DCB) |
-        TEGRA_SWGROUP_BIT(DC12), .linear_map = tegra_fb_linear_map, },
-       { .name = "tegradc.1", .swgids = TEGRA_SWGROUP_BIT(DC) |
-                                        TEGRA_SWGROUP_BIT(DCB) |
         TEGRA_SWGROUP_BIT(DC12), .linear_map = tegra_fb_linear_map, },
+       { .name = "tegradc.1", .swgids = TEGRA_SWGROUP_BIT(DCB),
+                               .linear_map = tegra_fb_linear_map, },
        { .name = "tegra-fuse", .swgids = TEGRA_SWGROUP_BIT(PPCS) |
                                          TEGRA_SWGROUP_BIT(PPCS1) |
          TEGRA_SWGROUP_BIT(PPCS2), },