ceres/atlantis: t148 csi calibration

t148 needs more than one clock sources to run the mipi calibration.
verified the change doesn't affect calibration on t114.

bug 1319070

Change-Id: I026368b5d014590210e811b5533281f1e314fe37
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/240418
(cherry picked from commit 0e04f05cbc1455a818814cd668c701874910c693)
Reviewed-on: http://git-master/r/257012
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

diff --git a/arch/arm/mach-tegra/mipi-cal.c b/arch/arm/mach-tegra/mipi-cal.c
index 1dbcca5dd69ae5c580a41f360d0d4438102be1f8..bba978ad9eb52e6feee9b83acaabf8a41d13105d 100644 (file)
--- a/arch/arm/mach-tegra/mipi-cal.c
+++ b/arch/arm/mach-tegra/mipi-cal.c
@@ -1,41 +1,39 @@
 /*
  * arch/arch/mach-tegra/mipi-cal.c
  *
- * Copyright (C) 2013 NVIDIA Corporation.
+ * Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
  *
  * Author:
  *     Charlie Huang <chahuang@nvidia.com>
  *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
  *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/init.h>
 #include <linux/fs.h>
 #include <linux/mm.h>
-#include <linux/platform_device.h>
 #include <linux/miscdevice.h>
-#include <linux/export.h>
 #include <linux/module.h>
-#include <linux/io.h>
+#include <linux/clk.h>
 
 #include "iomap.h"
 
-#define CLK_OUT_ENB_H          0x014
-
-#define clk_writel(value, reg) __raw_writel(value, clk_base + (reg))
-#define clk_readl(reg)         __raw_readl(clk_base + (reg))
+struct mipi_cal_info {
+       struct clk *clk;
+       struct clk *clk72mhz;
+};
 
-static void __iomem            *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static struct mipi_cal_info    pm;
 static atomic_t                        mipi_cal_in_use;
-static u32                     saved_bit;
 
 static int mipi_cal_open(struct inode *inode, struct file *filp);
 static int mipi_cal_release(struct inode *inode, struct file *filp);
@@ -57,30 +55,24 @@ static struct miscdevice mipi_cal_dev = {
 
 static int mipi_cal_open(struct inode *inode, struct file *filp)
 {
-       u32 val;
-
-       /* only one client can work on the mipi-cal registers at one time. */
        if (atomic_xchg(&mipi_cal_in_use, 1))
                return -EBUSY;
 
-       /* Save enable bit to MIPI CAL Logic */
-       val = clk_readl(CLK_OUT_ENB_H);
-       saved_bit = val & 0x1000000;
-       /* Enable clock to MIPI CAL Logic */
-       val |= 0x1000000;
-       clk_writel(val, CLK_OUT_ENB_H);
+       if (pm.clk72mhz)
+               clk_prepare_enable(pm.clk72mhz);
+       if (pm.clk)
+               clk_prepare_enable(pm.clk);
+
        return nonseekable_open(inode, filp);
 }
 
 static int mipi_cal_release(struct inode *inode, struct file *filp)
 {
-       u32 val;
+       if (pm.clk)
+               clk_disable_unprepare(pm.clk);
+       if (pm.clk72mhz)
+               clk_disable_unprepare(pm.clk72mhz);
 
-       val = clk_readl(CLK_OUT_ENB_H);
-       val &= ~0x1000000;
-       /* Restore enable bit to MIPI CAL Logic */
-       val |= saved_bit;
-       clk_writel(val, CLK_OUT_ENB_H);
        WARN_ON(!atomic_xchg(&mipi_cal_in_use, 0));
        return 0;
 }
@@ -106,8 +98,20 @@ static int mipi_cal_dev_mmap(struct file *file, struct vm_area_struct *vma)
 
 static int __init mipi_cal_dev_init(void)
 {
+       pm.clk = clk_get_sys("mipi-cal", NULL);
+       if (IS_ERR_OR_NULL(pm.clk)) {
+               pr_warn("%s: cannot get mipi-cal clk.\n", __func__);
+               pm.clk = NULL;
+       }
+
+       pm.clk72mhz = clk_get_sys("clk72mhz", NULL);
+       if (IS_ERR_OR_NULL(pm.clk72mhz)) {
+               pr_warn("%s: cannot get mipi-cal clk.\n", __func__);
+               pm.clk72mhz = NULL;
+       }
+
        return misc_register(&mipi_cal_dev);
 }
 
 module_init(mipi_cal_dev_init);
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");

diff --git a/arch/arm/mach-tegra/tegra14_clocks.c b/arch/arm/mach-tegra/tegra14_clocks.c
index bfdc4d41078dc146d4d1a05aaaa37f91f22145c5..098587aaff2d9a13def38cbd66252d2b8f473c89 100644 (file)
--- a/arch/arm/mach-tegra/tegra14_clocks.c
+++ b/arch/arm/mach-tegra/tegra14_clocks.c
@@ -6806,13 +6806,13 @@ static void tegra14_pllp_init_dependencies(unsigned long pllp_rate)
                break;
        case 408000000:
                tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
-               tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
+               tegra_pll_p_out3.u.pll_div.default_rate = 68000000;
                tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
                tegra_clk_host1x.u.periph.threshold = 204000000;
                break;
        case 204000000:
                tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
-               tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
+               tegra_pll_p_out3.u.pll_div.default_rate = 68000000;
                tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
                tegra_clk_host1x.u.periph.threshold = 204000000;
                break;