arm64: tegra: add DT support for Jetson-E

Bug 200044360

Change-Id: I5baf191da2b473d48e6c090c02440b9546d49c71
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/562812
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 7f403957a3451bc129bc9296da211b6907afaeb8..a5618df1bd35b0045aea474aa27c1b60ac1b49f4 100644 (file)
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -28,6 +28,7 @@ dtb-$(CONFIG_MACH_GRENADA) += tegra210-foster-e-e2581-0930-a00-00.dtb
 dtb-$(CONFIG_MACH_GRENADA) += tegra210-foster-e-e2581-0930-a01-00.dtb
 dtb-$(CONFIG_MACH_GRENADA) += tegra210-loki-e-e2581-0031-a00-00.dtb
 dtb-$(CONFIG_MACH_GRENADA) += tegra210-loki-e-e2581-0031-a01-00.dtb
+dtb-$(CONFIG_MACH_GRENADA) += tegra210-jetson-e-p2595-0000-a00-00.dtb
 dtb-$(CONFIG_ARCH_TEGRA_18x_SOC) += tegra186-sim.dtb
 dtb-$(CONFIG_ARCH_TEGRA_18x_SOC) += tegra186-sim-cl33688874.dtb
 dtb-$(CONFIG_ARCH_TEGRA_18x_SOC) += tegra186-sim-cl33759297.dtb

diff --git a/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts b/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts
new file mode 100644 (file)
index 0000000..882c021
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-jetson-e-p2595-0000-a00-00.dts
@@ -0,0 +1,290 @@
+/*
+ * arch/arm64/boot/dts/tegra210-jetson-e-p2530-0930-e00-00.dts
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00020000;
+
+#include "tegra210-common.dtsi"
+#include "tegra210-platforms/tegra210-power-tree-p2595-0000-a00.dtsi"
+#include "tegra210-platforms/tegra210-jetson-e-gpio-p2595-0000-a00.dtsi"
+#include "tegra210-platforms/tegra210-jetson-e-pinmux-p2595-0000-a00.dtsi"
+#include "tegra210-platforms/tegra210-comms-p2530-0930.dtsi"
+#include "tegra210-platforms/tegra210-pwm-fan-p2530-0930.dtsi"
+#include "tegra210-platforms/tegra210-sdhci-p2530-0930.dtsi"
+#include "tegra210-platforms/tegra210-hdmi-p2530-0930.dtsi"
+#include "tegra210-platforms/tegra210-thermal-fan-est-p2530-0930.dtsi"
+#include "tegra210-platforms/tegra210-keys-p2530-0930.dtsi"
+#include "tegra210-platforms/tegra210-powermon-p2530-0930.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/iio/meter/ina3221x.h>
+#include "tegra210-platforms/tegra210-extcon-p2530-0930.dtsi"
+
+/ {
+       model = "jetson_e";
+       compatible = "nvidia,jetson-e", "nvidia,tegra210";
+       nvidia,dtsfilename = __FILE__;
+
+       nvidia,boardids = "2595:0000:A0";
+       nvidia,proc-boardid = "2595:0000:A0";
+       nvidia,pmu-boardid = "2595:0000:A0";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       chosen {
+        };
+
+       pmc@7000e400 {
+               nvidia,invert-interrupt;
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = < 0x0 0x80000000 0x0 0x80000000 >;
+       };
+
+       sdhci@700b0600 { /* SDMMC4 for EMMC */
+               uhs-mask = <0x0>;
+               built-in;
+               pll_source = "pll_p", "pll_c4_out2";
+               power-off-rail;
+               status = "okay";
+       };
+
+       sdhci@700b0400 { /* SDMMC3 for 2nd Wifi */
+               uhs-mask = <0x8>;
+               power-off-rail;
+               status = "okay";
+       };
+
+       sdhci@700b0200 { /* SDMMC2 for Wifi */
+               uhs-mask = <0x8>;
+               power-off-rail;
+               status = "okay";
+       };
+
+       sdhci@700b0000 { /* SDMMC1 for uSD card */
+               uhs-mask = <0xc>;
+               power-off-rail;
+               status = "okay";
+       };
+
+       adma@702e2000  {
+               interrupts = <0 24 0x04
+                             0 25 0x04
+                             0 26 0x04
+                             0 27 0x04
+                             0 28 0x04
+                             0 29 0x04
+                             0 30 0x04
+                             0 31 0x04
+                             0 32 0x04
+                             0 33 0x04>;
+               dma-channels = <10>;
+               status = "okay";
+       };
+
+       ahub {
+               i2s@702d1000 {
+                       pinctrl-names = "dap_active", "dap_inactive";
+                       pinctrl-0 = <>;
+                       pinctrl-1 = <>;
+                       regulator-supplies = "vdd-1v8-audio-hv", "vdd-1v8-audio-hv-bias";
+                       vdd-1v8-audio-hv-supply = <&max77620_sd3>;
+                       vdd-1v8-audio-hv-bias-supply = <&max77620_sd3>;
+               };
+
+               i2s@702d1300 {
+                       pinctrl-names = "dap_active", "dap_inactive";
+                       pinctrl-0 = <>;
+                       pinctrl-1 = <>;
+                       regulator-supplies = "vddio-dmic";
+                       vddio-dmic-supply = <&max77620_sd3>;
+               };
+
+               i2s@702d1100 {
+                       pinctrl-names = "dap_active", "dap_inactive";
+                       pinctrl-0 = <>;
+                       pinctrl-1 = <>;
+                       regulator-supplies = "vdd-1v8-spi-hv", "vdd-1v8-spi-hv-bias";
+                       vdd-1v8-spi-hv-supply = <&max77620_sd3>;
+                       vdd-1v8-spi-hv-bias-supply = <&max77620_sd3>;
+                       fsync-width = <0>;
+               };
+       };
+
+       host1x {
+               /* tegradc.0 */
+               dc@54200000 {
+                       status = "okay";
+                       nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
+                       nvidia,emc-clk-rate = <300000000>;
+                       nvidia,fb-bpp = <32>; /* bits per pixel */
+                       nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
+               };
+       };
+
+       spi@7000da00 {
+               status = "disabled";
+       };
+
+       sound {
+               compatible = "realtek,rt5639";
+               nvidia,model = "rt5639";
+               nvidia,num-codec-link = <1>;
+
+               nvidia,audio-routing =
+                       "y Headphone",  "y OUT",
+                       "y IN",         "y Mic";
+
+               nvidia,xbar = <&tegra_axbar>;
+
+               nvidia,dai-link-1 {
+                       link-name = "spdif-dit-1";
+                       cpu-dai = <&tegra_i2s2>;
+                       codec-dai = <&spdif_dit1>;
+                       cpu-dai-name = "I2S2";
+                       codec-dai-name = "dit-hifi";
+                       format = "dsp_a";
+                       bitclock-slave;
+                       frame-slave;
+                       bitclock-inversion;
+                       frame-inversion;
+                       bit-format = "s16_le";
+                       bclk_ratio = <4>;
+                       srate = <8000>;
+                       num-channel = <1>;
+                       name-prefix = "y";
+               };
+       };
+
+       extcon {
+               extcon@0 {
+                       status = "disabled";
+               };
+       };
+
+       udc@7d000000 {
+               nvidia,port-otg;
+               nvidia,charging-supported;
+               #extcon-cells = <1>;
+               status = "okay";
+       };
+
+        otg@7d000000 {
+               #extcon-cells = <1>;
+               status = "okay";
+       };
+
+       xusb_pad_ctl: padctl@0 { /* Put common control config here */
+               nvidia,ss_portmap = <0x0321>;
+               nvidia,lane_owner = <0xF056>; /* Use 0xF to disable lane assign */
+               status = "okay";
+       };
+
+       xusb@70090000 {
+               /* nvidia,uses_external_pmic;
+               /* nvidia,gpio_controls_muxed_ss_lanes; */
+               nvidia,gpio_ss1_sata = <0>;
+               nvidia,ulpicap = <0>; /* No ulpi support. can we remove */
+               nvidia,portmap = <0x0e07>;
+               nvidia,common_padctl = <&xusb_pad_ctl>;
+               status = "okay";
+       };
+
+       xudc@700d0000 {
+               nvidia,common_padctl = <&xusb_pad_ctl>;
+               nvidia,portmap = <0x0108>;
+               #extcon-cells = <1>;
+               status = "okay";
+       };
+
+       gpio-keys {
+               power {
+                       gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
+               };
+
+               sw_lid {
+                       status="disabled";
+               };
+       };
+
+       gpu-dvfs-rework {
+               status = "disabled";
+       };
+
+       pwm-leds {
+               compatible = "pwm-leds";
+               lightbar {
+                       label = "led_lightbar";
+                       pwms = <&tegra_pwm 0 10000000>;
+                       gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+                       max-brightness = <255>;
+                       default-brightness = <255>;
+                       linux,default-trigger = "default-on";
+               };
+       };
+
+       thermal-fan-est {
+               compatible = "jetson-thermal-est";
+               active_trip_temps = <0 63000 74000 85000 120000
+                               140000 150000 160000 170000 180000>;
+               active_hysteresis = <0 15000 11000 6000 4000
+                               0 0 0 0 0>;
+       };
+
+       pwm-fan {
+               compatible = "jetson-pwm-fan";
+               shared_data = <&pwm_fan_shared_data>;
+               active_pwm = <0 70 115 135 135 240 245 250 252 255>;
+       };
+
+        i2c@7000c000 {
+               rt5639: rt5639.0-001c@1c {
+                       compatible = "realtek,rt5639";
+                       reg = <0x1c>;
+               };
+
+                icm20628@68 { /* Accelerometer and Gyroscope */
+                        compatible = "invensense,mpu6xxx";
+                        reg = <0x68>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(X, 2) 0x00>;
+                        invensense,orientation = [ff 00 00 00 01 00 00 00 ff];
+                };
+
+                ak8963c@0c { /* Compass */
+                        compatible = "ak,ak89xx";
+                        reg = <0x0c>;
+                        orientation = [01 00 00 00 ff 00 00 00 ff];
+                };
+
+                jsa1127@39 { /* Ambient Light Sensor */
+                        compatible = "solteam-opto,jsa1127";
+                        reg = <0x39>;
+                        solteam-opto,rint = <100>;
+                        solteam-opto,integration-time = <2000>;
+                        solteam-opto,use-internal-integration-timing = <1>;
+                        solteam-opto,tint-coeff = <22>;
+                        solteam-opto,noisy = <1>;
+                };
+
+        };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-comms-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-comms-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..3af6934
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-comms-p2530-0930.dtsi
@@ -0,0 +1,36 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+/ {
+       gpio: gpio@6000d000 {
+               gpio-init-1 = <&wlan_default>;
+
+               wlan_default: wlan-default {
+                       gpio-input = <
+                               TEGRA_GPIO(H, 2)
+                               TEGRA_GPIO(I, 1)
+                               >;
+                       gpio-output-high = <
+                               TEGRA_GPIO(H, 0)
+                               TEGRA_GPIO(I, 0)
+                               >;
+               };
+       };
+
+       bluedroid_pm { /* BT BCM43340 in P2530 Compute Module */
+               compatible = "nvidia,tegra-bluedroid_pm";
+               id = <0>;
+               bluedroid_pm,reset-gpio = <&gpio TEGRA_GPIO(H, 4) 0>;
+               bluedroid_pm,host-wake-gpio = <&gpio TEGRA_GPIO(H, 5) 0>;
+               bluedroid_pm,ext-wake-gpio = <&gpio TEGRA_GPIO(H, 3) 0>;
+               interrupt-parent = <&gpio>;
+               interrupts = <TEGRA_GPIO(H, 5) 0x01>;
+       };
+
+       bcmdhd_wlan { /* WLAN BCM43340 in P2530 Compute Module */
+               compatible = "android,bcmdhd_wlan";
+               interrupt-parent = <&gpio>;
+               interrupts = <TEGRA_GPIO(H, 2) 0x14>;
+               wlan-pwr-gpio = <&gpio TEGRA_GPIO(H, 0) 0>;
+               status = "okay";
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-extcon-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-extcon-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..7723653
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-extcon-p2530-0930.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/ {
+       extcon {
+               otg_gpio_extcon: extcon@1 {
+                       compatible = "extcon-otg";
+                       reg = <0x1>;
+                       extcon-otg,name = "otg";
+                       id-gpio = <&max77620 0 0>;
+                       vbus-gpio = <&gpio TEGRA_GPIO(Z, 5) 0>;
+                       io-channels = <&ina3221x INA3221_CHAN_INDEX(1, VOLTAGE, NORMAL)>;
+                       vbus-presence-threshold = <4000>;
+                       io-channel-names = "vbus";
+                       debounce = <100>;
+                       vbus-auto-hw;
+                       extcon-gpio,cable-name = "USB", "USB-Host";
+                       #extcon-cells = <1>;
+               };
+       };
+
+       udc@7d000000 {
+               nvidia,enable-pmu-vbus-detection;
+               nvidia,id-detection-type = <1>;
+               extcon-cables = <&otg_gpio_extcon 0>;
+               extcon-cable-names = "vbus";
+       };
+
+       otg@7d000000 {
+               nvidia,enable-pmu-vbus-detection;
+               nvidia,id-detection-type = <1>;
+               extcon-cables = <&otg_gpio_extcon 0 &otg_gpio_extcon 1>;
+               extcon-cable-names = "vbus", "id";
+       };
+
+       xudc@700d0000 {
+               extcon-cables = <&otg_gpio_extcon 0 &otg_gpio_extcon 1>;
+               extcon-cable-names = "vbus", "id";
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-fixed-p2530-max7762x.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-fixed-p2530-max7762x.dtsi
new file mode 100644 (file)
index 0000000..e9de57b
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-fixed-p2530-max7762x.dtsi
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+/ {
+       regulators {
+               compatible = "simple-bus";
+               device_type = "fixed-regulators";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               battery_reg: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "vdd-ac-bat";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+               };
+
+               vdd_3v3: regulator@1 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <1>;
+                       regulator-name = "vdd-3v3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+                       gpio = <&max77620 3 0>;
+                       enable-active-high;
+                       consumers {
+                               c1 {
+                                       regulator-consumer-supply = "avdd_usb";
+                                       regulator-consumer-device = "tegra-ehci.0";
+                               };
+                               c2 {
+                                       regulator-consumer-supply = "avdd_usb";
+                                       regulator-consumer-device = "tegra-ehci.1";
+                               };
+                               c3 {
+                                       regulator-consumer-supply = "avdd_usb";
+                                       regulator-consumer-device = "tegra-ehci.2";
+                               };
+                               c5 {
+                                       regulator-consumer-supply = "vdd";
+                                       regulator-consumer-device = "1-004d";
+                               };
+                       };
+               };
+
+               max77620_gpio7: regulator@2 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <2>;
+                       regulator-name = "max77620-gpio7";
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       gpio = <&max77620 7 0>;
+                       enable-active-high;
+                       vin-supply = <&max77620_ldo0>;
+               };
+
+               lcd_bl_en: regulator@3 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <3>;
+                       regulator-name = "lcd-bl-en";
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
+                       enable-active-high;
+               };
+
+               en_vdd_sd: regulator@4 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <4>;
+                       regulator-name = "en-vdd-sd";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio TEGRA_GPIO(Z, 4) 0>;
+                       enable-active-high;
+                       vin-supply = <&vdd_3v3>;
+               };
+
+               en_vdd_cam: regulator@5 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <5>;
+                       regulator-name = "en-vdd-cam";
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       gpio = <&gpio TEGRA_GPIO(S, 4) 0>;
+                       enable-active-high;
+               };
+
+               vdd_sys_boost: regulator@6 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <6>;
+                       regulator-name = "vdd-sys-boost";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+                       gpio = <&max77620 1 0>;
+                       enable-active-high;
+               };
+
+               vdd_hdmi: regulator@7 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <7>;
+                       regulator-name = "vdd-hdmi";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(CC, 7) 0>;
+                       enable-active-high;
+                       vin-supply = <&vdd_sys_boost>;
+               };
+
+               en_vdd_cpu_fixed: regulator@8 {
+                       compatible = "regulator-fixed";
+                       reg = <8>;
+                       regulator-name = "vdd-cpu-fixed";
+                       regulator-min-microvolt = <1000000>;
+                       regulator-max-microvolt = <1000000>;
+               };
+
+               vdd_aux_3v3: regulator@9 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <9>;
+                       regulator-name = "aux-3v3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+               };
+
+               vdd_snsr_pm: regulator@10 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <10>;
+                       regulator-name = "snsr_pm";
+                       enable-active-high;
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+               };
+
+               vdd_usb_5v0: regulator@11 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <11>;
+                       status = "disabled";
+                       regulator-name = "vdd-usb-5v0";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       vin-supply = <&vdd_3v3>;
+                       regulator-always-on;
+                       enable-active-high;
+                       consumers {
+                               c0 {
+                                       regulator-consumer-supply = "usb_vbus";
+                                       regulator-consumer-device = "tegra-ehci.1";
+                               };
+                               c1 {
+                                       regulator-consumer-supply = "usb_vbus";
+                                       regulator-consumer-device = "tegra-ehci.2";
+                               };
+                       };
+               };
+
+               vdd_cdc_1v2_aud: regulator@101 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <101>;
+                       status = "disabled";
+                       regulator-name = "vdd_cdc_1v2_aud";
+                       regulator-min-microvolt = <1200000>;
+                       regulator-max-microvolt = <1200000>;
+                       enable-active-high;
+                       startup-delay-us = <250000>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-hdmi-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-hdmi-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..be4bcdf
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-hdmi-p2530-0930.dtsi
@@ -0,0 +1,91 @@
+/*
+ * arch/arm64/boot/dts/tegra210-platforms/tegra210-hdmi-p2530-0930.dtsi
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <dt-bindings/display/tegra-dc.h>
+
+/ {
+       host1x {
+               sor1 {
+                       status = "okay";
+                       nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                       nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 1>; /* PN7 */
+                       hdmi-display {
+                               status = "okay";
+                               compatible = "hdmi,display";
+                               disp-default-out {
+                                       nvidia,out-type = <TEGRA_DC_OUT_HDMI>;
+                                       nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_LOW>;
+                                       nvidia,out-parent-clk = "pll_d2";
+                                       nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
+                                       nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
+                               };
+                               tmds-config {
+                                       tmds-cfg@0 {
+                                               version = <1 0>;
+                                               pclk = <27000000>;
+                                               pll0 = <0x01003010>;
+                                               pll1 = <0x00301b00>;
+                                               pe-current = <0x00000000>;
+                                               drive-current = <0x1c1c1c1c>;
+                                               peak-current = <0x00000000>;
+                                               pad-ctls0-mask = <0xfffff0ff>;
+                                               pad-ctls0-setting = <0x00000400>;
+                                       };
+                                       tmds-cfg@1 {
+                                               version = <1 0>;
+                                               pclk = <74250000>;
+                                               pll0 = <0x01003110>;
+                                               pll1 = <0x00301500>;
+                                               pe-current = <0x00000000>;
+                                               drive-current = <0x23232323>;
+                                               peak-current = <0x00000000>;
+                                               pad-ctls0-mask = <0xfffff0ff>;
+                                               pad-ctls0-setting = <0x00000400>;
+                                       };
+                                       tmds-cfg@2 {
+                                               version = <1 0>;
+                                               pclk = <148500000>;
+                                               pll0 = <0x01003310>;
+                                               pll1 = <0x10300f00>;
+                                               pe-current = <0x00000000>;
+                                               drive-current = <0x2a2c2c2a>;
+                                               peak-current = <0x00000000>;
+                                               pad-ctls0-mask = <0xfffff0ff>;
+                                               pad-ctls0-setting = <0x00000400>;
+                                       };
+                                       tmds-cfg@3 {
+                                               version = <1 0>;
+                                               pclk = <0x7fffffff>;
+                                               pll0 = <0x01003f10>;
+                                               pll1 = <0x10300700>;
+                                               pe-current = <0x00000000>;
+                                               drive-current = <0x30323333>;
+                                               peak-current = <0x10101010>;
+                                               pad-ctls0-mask = <0xfffff0ff>;
+                                               pad-ctls0-setting = <0x00000600>;
+                                       };
+                               };
+                       };
+               };
+       };
+       hdmi_ddc: i2c@7000c700 {
+               clock-frequency = <100000>;
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-e-gpio-p2595-0000-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-e-gpio-p2595-0000-a00.dtsi
new file mode 100755 (executable)
index 0000000..61c5852
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-e-gpio-p2595-0000-a00.dtsi
@@ -0,0 +1,83 @@
+/*\r
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along\r
+ * with this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.\r
+ */\r
+\r
+#include <dt-bindings/gpio/tegra-gpio.h>\r
+\r
+/ {\r
+       gpio: gpio@6000d000 {\r
+               gpio-init-names = "default";\r
+               gpio-init-0 = <&gpio_default>;\r
+\r
+               gpio_default: default {\r
+                       gpio-input = <\r
+                               TEGRA_GPIO(E, 6)\r
+                               TEGRA_GPIO(A, 5)\r
+                               TEGRA_GPIO(X, 3)\r
+                               TEGRA_GPIO(X, 4)\r
+                               TEGRA_GPIO(X, 2)\r
+                               TEGRA_GPIO(X, 1)\r
+                               TEGRA_GPIO(X, 0)\r
+                               TEGRA_GPIO(X, 5)\r
+                               TEGRA_GPIO(X, 6)\r
+                               TEGRA_GPIO(X, 7)\r
+                               TEGRA_GPIO(Y, 1)\r
+                               TEGRA_GPIO(Z, 0)\r
+                               TEGRA_GPIO(G, 0)\r
+                               TEGRA_GPIO(K, 4)\r
+                               TEGRA_GPIO(K, 6)\r
+                               TEGRA_GPIO(H, 2)\r
+                               TEGRA_GPIO(H, 5)\r
+                               TEGRA_GPIO(I, 1)\r
+                               TEGRA_GPIO(CC, 6)\r
+                               TEGRA_GPIO(CC, 1)\r
+                               >;\r
+                       gpio-output-low = <\r
+                               TEGRA_GPIO(BB, 2)\r
+                               TEGRA_GPIO(BB, 3)\r
+                               TEGRA_GPIO(E, 4)\r
+                               TEGRA_GPIO(S, 4)\r
+                               TEGRA_GPIO(S, 5)\r
+                               TEGRA_GPIO(S, 6)\r
+                               TEGRA_GPIO(S, 7)\r
+                               TEGRA_GPIO(T, 0)\r
+                               TEGRA_GPIO(T, 1)\r
+                               TEGRA_GPIO(V, 6)\r
+                               TEGRA_GPIO(V, 1)\r
+                               TEGRA_GPIO(V, 2)\r
+                               TEGRA_GPIO(V, 5)\r
+                               TEGRA_GPIO(Z, 4)\r
+                               TEGRA_GPIO(G, 3)\r
+                               TEGRA_GPIO(K, 5)\r
+                               TEGRA_GPIO(K, 7)\r
+                               TEGRA_GPIO(L, 0)\r
+                               TEGRA_GPIO(H, 0)\r
+                               TEGRA_GPIO(H, 3)\r
+                               TEGRA_GPIO(H, 4)\r
+                               TEGRA_GPIO(H, 6)\r
+                               TEGRA_GPIO(H, 7)\r
+                               TEGRA_GPIO(I, 0)\r
+                               TEGRA_GPIO(I, 2)\r
+                               TEGRA_GPIO(I, 3)\r
+                               TEGRA_GPIO(CC, 7)\r
+                               >;\r
+                       gpio-output-high = <\r
+                               TEGRA_GPIO(V, 7)\r
+                               >;\r
+               };\r
+       };\r
+};\r

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-e-pinmux-p2595-0000-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-e-pinmux-p2595-0000-a00.dtsi
new file mode 100755 (executable)
index 0000000..05d475c
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-e-pinmux-p2595-0000-a00.dtsi
@@ -0,0 +1,1346 @@
+/*\r
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+ * more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along\r
+ * with this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.\r
+ */\r
+\r
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>\r
+\r
+/ {\r
+       pinmux: pinmux@700008d4 {\r
+               status = "okay";\r
+               pinctrl-names = "default", "drive", "unused";\r
+               pinctrl-0 = <&pinmux_default>;\r
+               pinctrl-1 = <&drive_default>;\r
+               pinctrl-2 = <&pinmux_unused_lowpower>;\r
+\r
+               pinmux_default: common {\r
+                       /* SFIO Pin Configuration */\r
+                       aud_mclk_pbb0 {\r
+                               nvidia,pins = "aud_mclk_pbb0";\r
+                               nvidia,function = "aud";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dvfs_pwm_pbb1 {\r
+                               nvidia,pins = "dvfs_pwm_pbb1";\r
+                               nvidia,function = "cldvfs";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dap1_din_pb1 {\r
+                               nvidia,pins = "dap1_din_pb1";\r
+                               nvidia,function = "i2s1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap1_dout_pb2 {\r
+                               nvidia,pins = "dap1_dout_pb2";\r
+                               nvidia,function = "i2s1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap1_fs_pb0 {\r
+                               nvidia,pins = "dap1_fs_pb0";\r
+                               nvidia,function = "i2s1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap1_sclk_pb3 {\r
+                               nvidia,pins = "dap1_sclk_pb3";\r
+                               nvidia,function = "i2s1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dmic1_clk_pe0 {\r
+                               nvidia,pins = "dmic1_clk_pe0";\r
+                               nvidia,function = "dmic1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dmic1_dat_pe1 {\r
+                               nvidia,pins = "dmic1_dat_pe1";\r
+                               nvidia,function = "dmic1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dmic2_clk_pe2 {\r
+                               nvidia,pins = "dmic2_clk_pe2";\r
+                               nvidia,function = "dmic2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dmic2_dat_pe3 {\r
+                               nvidia,pins = "dmic2_dat_pe3";\r
+                               nvidia,function = "dmic2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pe7 {\r
+                               nvidia,pins = "pe7";\r
+                               nvidia,function = "pwm3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       gen3_i2c_scl_pf0 {\r
+                               nvidia,pins = "gen3_i2c_scl_pf0";\r
+                               nvidia,function = "i2c3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       gen3_i2c_sda_pf1 {\r
+                               nvidia,pins = "gen3_i2c_sda_pf1";\r
+                               nvidia,function = "i2c3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam_i2c_scl_ps2 {\r
+                               nvidia,pins = "cam_i2c_scl_ps2";\r
+                               nvidia,function = "i2cvi";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam_i2c_sda_ps3 {\r
+                               nvidia,pins = "cam_i2c_sda_ps3";\r
+                               nvidia,function = "i2cvi";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam1_mclk_ps0 {\r
+                               nvidia,pins = "cam1_mclk_ps0";\r
+                               nvidia,function = "extperiph3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam2_mclk_ps1 {\r
+                               nvidia,pins = "cam2_mclk_ps1";\r
+                               nvidia,function = "extperiph3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pex_l0_clkreq_n_pa1 {\r
+                               nvidia,pins = "pex_l0_clkreq_n_pa1";\r
+                               nvidia,function = "pe0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pex_l0_rst_n_pa0 {\r
+                               nvidia,pins = "pex_l0_rst_n_pa0";\r
+                               nvidia,function = "pe0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pex_l1_clkreq_n_pa4 {\r
+                               nvidia,pins = "pex_l1_clkreq_n_pa4";\r
+                               nvidia,function = "pe1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pex_l1_rst_n_pa3 {\r
+                               nvidia,pins = "pex_l1_rst_n_pa3";\r
+                               nvidia,function = "pe1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pex_wake_n_pa2 {\r
+                               nvidia,pins = "pex_wake_n_pa2";\r
+                               nvidia,function = "pe";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc1_clk_pm0 {\r
+                               nvidia,pins = "sdmmc1_clk_pm0";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc1_cmd_pm1 {\r
+                               nvidia,pins = "sdmmc1_cmd_pm1";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc1_dat0_pm5 {\r
+                               nvidia,pins = "sdmmc1_dat0_pm5";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc1_dat1_pm4 {\r
+                               nvidia,pins = "sdmmc1_dat1_pm4";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc1_dat2_pm3 {\r
+                               nvidia,pins = "sdmmc1_dat2_pm3";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc1_dat3_pm2 {\r
+                               nvidia,pins = "sdmmc1_dat3_pm2";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc3_clk_pp0 {\r
+                               nvidia,pins = "sdmmc3_clk_pp0";\r
+                               nvidia,function = "sdmmc3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       sdmmc3_cmd_pp1 {\r
+                               nvidia,pins = "sdmmc3_cmd_pp1";\r
+                               nvidia,function = "sdmmc3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc3_dat0_pp5 {\r
+                               nvidia,pins = "sdmmc3_dat0_pp5";\r
+                               nvidia,function = "sdmmc3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc3_dat1_pp4 {\r
+                               nvidia,pins = "sdmmc3_dat1_pp4";\r
+                               nvidia,function = "sdmmc3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc3_dat2_pp3 {\r
+                               nvidia,pins = "sdmmc3_dat2_pp3";\r
+                               nvidia,function = "sdmmc3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       sdmmc3_dat3_pp2 {\r
+                               nvidia,pins = "sdmmc3_dat3_pp2";\r
+                               nvidia,function = "sdmmc3";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       shutdown {\r
+                               nvidia,pins = "shutdown";\r
+                               nvidia,function = "shutdown";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       lcd_te_py2 {\r
+                               nvidia,pins = "lcd_te_py2";\r
+                               nvidia,function = "displaya";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       lcd_bl_pwm_pv0 {\r
+                               nvidia,pins = "lcd_bl_pwm_pv0";\r
+                               nvidia,function = "pwm0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       lcd_gpio2_pv4 {\r
+                               nvidia,pins = "lcd_gpio2_pv4";\r
+                               nvidia,function = "pwm1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pwr_i2c_scl_py3 {\r
+                               nvidia,pins = "pwr_i2c_scl_py3";\r
+                               nvidia,function = "i2cpmu";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pwr_i2c_sda_py4 {\r
+                               nvidia,pins = "pwr_i2c_sda_py4";\r
+                               nvidia,function = "i2cpmu";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       clk_32k_in {\r
+                               nvidia,pins = "clk_32k_in";\r
+                               nvidia,function = "clk";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       clk_32k_out_py5 {\r
+                               nvidia,pins = "clk_32k_out_py5";\r
+                               nvidia,function = "soc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pz1 {\r
+                               nvidia,pins = "pz1";\r
+                               nvidia,function = "sdmmc1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pz5 {\r
+                               nvidia,pins = "pz5";\r
+                               nvidia,function = "soc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       clk_req {\r
+                               nvidia,pins = "clk_req";\r
+                               nvidia,function = "sys";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       core_pwr_req {\r
+                               nvidia,pins = "core_pwr_req";\r
+                               nvidia,function = "core";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cpu_pwr_req {\r
+                               nvidia,pins = "cpu_pwr_req";\r
+                               nvidia,function = "cpu";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pwr_int_n {\r
+                               nvidia,pins = "pwr_int_n";\r
+                               nvidia,function = "pmi";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap4_din_pj5 {\r
+                               nvidia,pins = "dap4_din_pj5";\r
+                               nvidia,function = "i2s4b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap4_dout_pj6 {\r
+                               nvidia,pins = "dap4_dout_pj6";\r
+                               nvidia,function = "i2s4b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap4_fs_pj4 {\r
+                               nvidia,pins = "dap4_fs_pj4";\r
+                               nvidia,function = "i2s4b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap4_sclk_pj7 {\r
+                               nvidia,pins = "dap4_sclk_pj7";\r
+                               nvidia,function = "i2s4b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       gen1_i2c_scl_pj1 {\r
+                               nvidia,pins = "gen1_i2c_scl_pj1";\r
+                               nvidia,function = "i2c1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       gen1_i2c_sda_pj0 {\r
+                               nvidia,pins = "gen1_i2c_sda_pj0";\r
+                               nvidia,function = "i2c1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       gen2_i2c_scl_pj2 {\r
+                               nvidia,pins = "gen2_i2c_scl_pj2";\r
+                               nvidia,function = "i2c2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       gen2_i2c_sda_pj3 {\r
+                               nvidia,pins = "gen2_i2c_sda_pj3";\r
+                               nvidia,function = "i2c2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       uart1_tx_pu0 {\r
+                               nvidia,pins = "uart1_tx_pu0";\r
+                               nvidia,function = "uarta";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart1_rx_pu1 {\r
+                               nvidia,pins = "uart1_rx_pu1";\r
+                               nvidia,function = "uarta";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       uart1_rts_pu2 {\r
+                               nvidia,pins = "uart1_rts_pu2";\r
+                               nvidia,function = "uarta";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart1_cts_pu3 {\r
+                               nvidia,pins = "uart1_cts_pu3";\r
+                               nvidia,function = "uarta";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       jtag_rtck {\r
+                               nvidia,pins = "jtag_rtck";\r
+                               nvidia,function = "jtag";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pk0 {\r
+                               nvidia,pins = "pk0";\r
+                               nvidia,function = "i2s5b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pk1 {\r
+                               nvidia,pins = "pk1";\r
+                               nvidia,function = "i2s5b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pk2 {\r
+                               nvidia,pins = "pk2";\r
+                               nvidia,function = "i2s5b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pk3 {\r
+                               nvidia,pins = "pk3";\r
+                               nvidia,function = "i2s5b";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pl1 {\r
+                               nvidia,pins = "pl1";\r
+                               nvidia,function = "soc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi1_mosi_pc0 {\r
+                               nvidia,pins = "spi1_mosi_pc0";\r
+                               nvidia,function = "spi1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi1_miso_pc1 {\r
+                               nvidia,pins = "spi1_miso_pc1";\r
+                               nvidia,function = "spi1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi1_sck_pc2 {\r
+                               nvidia,pins = "spi1_sck_pc2";\r
+                               nvidia,function = "spi1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi1_cs0_pc3 {\r
+                               nvidia,pins = "spi1_cs0_pc3";\r
+                               nvidia,function = "spi1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi1_cs1_pc4 {\r
+                               nvidia,pins = "spi1_cs1_pc4";\r
+                               nvidia,function = "spi1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi4_mosi_pc7 {\r
+                               nvidia,pins = "spi4_mosi_pc7";\r
+                               nvidia,function = "spi4";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi4_miso_pd0 {\r
+                               nvidia,pins = "spi4_miso_pd0";\r
+                               nvidia,function = "spi4";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       spi4_sck_pc5 {\r
+                               nvidia,pins = "spi4_sck_pc5";\r
+                               nvidia,function = "spi4";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi4_cs0_pc6 {\r
+                               nvidia,pins = "spi4_cs0_pc6";\r
+                               nvidia,function = "spi4";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart3_tx_pd1 {\r
+                               nvidia,pins = "uart3_tx_pd1";\r
+                               nvidia,function = "uartc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart3_rx_pd2 {\r
+                               nvidia,pins = "uart3_rx_pd2";\r
+                               nvidia,function = "uartc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       uart3_rts_pd3 {\r
+                               nvidia,pins = "uart3_rts_pd3";\r
+                               nvidia,function = "uartc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart3_cts_pd4 {\r
+                               nvidia,pins = "uart3_cts_pd4";\r
+                               nvidia,function = "uartc";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       uart4_tx_pi4 {\r
+                               nvidia,pins = "uart4_tx_pi4";\r
+                               nvidia,function = "uartd";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart4_rx_pi5 {\r
+                               nvidia,pins = "uart4_rx_pi5";\r
+                               nvidia,function = "uartd";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       uart4_rts_pi6 {\r
+                               nvidia,pins = "uart4_rts_pi6";\r
+                               nvidia,function = "uartd";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart4_cts_pi7 {\r
+                               nvidia,pins = "uart4_cts_pi7";\r
+                               nvidia,function = "uartd";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap2_din_paa2 {\r
+                               nvidia,pins = "dap2_din_paa2";\r
+                               nvidia,function = "i2s2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap2_dout_paa3 {\r
+                               nvidia,pins = "dap2_dout_paa3";\r
+                               nvidia,function = "i2s2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap2_fs_paa0 {\r
+                               nvidia,pins = "dap2_fs_paa0";\r
+                               nvidia,function = "i2s2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       dap2_sclk_paa1 {\r
+                               nvidia,pins = "dap2_sclk_paa1";\r
+                               nvidia,function = "i2s2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       usb_vbus_en0_pcc4 {\r
+                               nvidia,pins = "usb_vbus_en0_pcc4";\r
+                               nvidia,function = "usb";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       hdmi_cec_pcc0 {\r
+                               nvidia,pins = "hdmi_cec_pcc0";\r
+                               nvidia,function = "cec";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       /* GPIO Pin Configuration */\r
+                       dvfs_clk_pbb2 {\r
+                               nvidia,pins = "dvfs_clk_pbb2";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       gpio_x1_aud_pbb3 {\r
+                               nvidia,pins = "gpio_x1_aud_pbb3";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dmic3_clk_pe4 {\r
+                               nvidia,pins = "dmic3_clk_pe4";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pe6 {\r
+                               nvidia,pins = "pe6";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       cam_rst_ps4 {\r
+                               nvidia,pins = "cam_rst_ps4";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam_af_en_ps5 {\r
+                               nvidia,pins = "cam_af_en_ps5";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam_flash_en_ps6 {\r
+                               nvidia,pins = "cam_flash_en_ps6";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam1_pwdn_ps7 {\r
+                               nvidia,pins = "cam1_pwdn_ps7";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam2_pwdn_pt0 {\r
+                               nvidia,pins = "cam2_pwdn_pt0";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       cam1_strobe_pt1 {\r
+                               nvidia,pins = "cam1_strobe_pt1";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       sata_led_active_pa5 {\r
+                               nvidia,pins = "sata_led_active_pa5";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       als_prox_int_px3 {\r
+                               nvidia,pins = "als_prox_int_px3";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       temp_alert_px4 {\r
+                               nvidia,pins = "temp_alert_px4";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       motion_int_px2 {\r
+                               nvidia,pins = "motion_int_px2";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       touch_rst_pv6 {\r
+                               nvidia,pins = "touch_rst_pv6";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       touch_clk_pv7 {\r
+                               nvidia,pins = "touch_clk_pv7";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       touch_int_px1 {\r
+                               nvidia,pins = "touch_int_px1";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       modem_wake_ap_px0 {\r
+                               nvidia,pins = "modem_wake_ap_px0";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       button_power_on_px5 {\r
+                               nvidia,pins = "button_power_on_px5";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       button_vol_up_px6 {\r
+                               nvidia,pins = "button_vol_up_px6";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       button_vol_down_px7 {\r
+                               nvidia,pins = "button_vol_down_px7";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       button_home_py1 {\r
+                               nvidia,pins = "button_home_py1";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       lcd_bl_en_pv1 {\r
+                               nvidia,pins = "lcd_bl_en_pv1";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       lcd_rst_pv2 {\r
+                               nvidia,pins = "lcd_rst_pv2";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       ap_ready_pv5 {\r
+                               nvidia,pins = "ap_ready_pv5";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pz0 {\r
+                               nvidia,pins = "pz0";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pz4 {\r
+                               nvidia,pins = "pz4";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart2_tx_pg0 {\r
+                               nvidia,pins = "uart2_tx_pg0";\r
+                               nvidia,function = "uartb";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       uart2_cts_pg3 {\r
+                               nvidia,pins = "uart2_cts_pg3";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pk4 {\r
+                               nvidia,pins = "pk4";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pk5 {\r
+                               nvidia,pins = "pk5";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pk6 {\r
+                               nvidia,pins = "pk6";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       pk7 {\r
+                               nvidia,pins = "pk7";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pl0 {\r
+                               nvidia,pins = "pl0";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       wifi_en_ph0 {\r
+                               nvidia,pins = "wifi_en_ph0";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       wifi_wake_ap_ph2 {\r
+                               nvidia,pins = "wifi_wake_ap_ph2";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       ap_wake_bt_ph3 {\r
+                               nvidia,pins = "ap_wake_bt_ph3";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       bt_rst_ph4 {\r
+                               nvidia,pins = "bt_rst_ph4";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       bt_wake_ap_ph5 {\r
+                               nvidia,pins = "bt_wake_ap_ph5";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_UP>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       ph6 {\r
+                               nvidia,pins = "ph6";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       ap_wake_nfc_ph7 {\r
+                               nvidia,pins = "ap_wake_nfc_ph7";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       nfc_en_pi0 {\r
+                               nvidia,pins = "nfc_en_pi0";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       nfc_int_pi1 {\r
+                               nvidia,pins = "nfc_int_pi1";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       gps_en_pi2 {\r
+                               nvidia,pins = "gps_en_pi2";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       gps_rst_pi3 {\r
+                               nvidia,pins = "gps_rst_pi3";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pcc7 {\r
+                               nvidia,pins = "pcc7";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dp_hpd0_pcc6 {\r
+                               nvidia,pins = "dp_hpd0_pcc6";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                       };\r
+\r
+                       hdmi_int_dp_hpd_pcc1 {\r
+                               nvidia,pins = "hdmi_int_dp_hpd_pcc1";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+               };\r
+\r
+               pinmux_unused_lowpower: unused_lowpower {\r
+                       gpio_x3_aud_pbb4 {\r
+                               nvidia,pins = "gpio_x3_aud_pbb4";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi2_mosi_pb4 {\r
+                               nvidia,pins = "spi2_mosi_pb4";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi2_miso_pb5 {\r
+                               nvidia,pins = "spi2_miso_pb5";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi2_sck_pb6 {\r
+                               nvidia,pins = "spi2_sck_pb6";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi2_cs0_pb7 {\r
+                               nvidia,pins = "spi2_cs0_pb7";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spi2_cs1_pdd0 {\r
+                               nvidia,pins = "spi2_cs1_pdd0";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       dmic3_dat_pe5 {\r
+                               nvidia,pins = "dmic3_dat_pe5";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pa6 {\r
+                               nvidia,pins = "pa6";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       button_slide_sw_py0 {\r
+                               nvidia,pins = "button_slide_sw_py0";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       lcd_gpio1_pv3 {\r
+                               nvidia,pins = "lcd_gpio1_pv3";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pz2 {\r
+                               nvidia,pins = "pz2";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       pz3 {\r
+                               nvidia,pins = "pz3";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart2_rx_pg1 {\r
+                               nvidia,pins = "uart2_rx_pg1";\r
+                               nvidia,function = "uartb";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       uart2_rts_pg2 {\r
+                               nvidia,pins = "uart2_rts_pg2";\r
+                               nvidia,function = "rsvd2";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       wifi_rst_ph1 {\r
+                               nvidia,pins = "wifi_rst_ph1";\r
+                               nvidia,function = "rsvd0";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       qspi_io0_pee2 {\r
+                               nvidia,pins = "qspi_io0_pee2";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       qspi_io1_pee3 {\r
+                               nvidia,pins = "qspi_io1_pee3";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       qspi_sck_pee0 {\r
+                               nvidia,pins = "qspi_sck_pee0";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       qspi_cs_n_pee1 {\r
+                               nvidia,pins = "qspi_cs_n_pee1";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       qspi_io2_pee4 {\r
+                               nvidia,pins = "qspi_io2_pee4";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       qspi_io3_pee5 {\r
+                               nvidia,pins = "qspi_io3_pee5";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spdif_out_pcc2 {\r
+                               nvidia,pins = "spdif_out_pcc2";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       spdif_in_pcc3 {\r
+                               nvidia,pins = "spdif_in_pcc3";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+\r
+                       usb_vbus_en1_pcc5 {\r
+                               nvidia,pins = "usb_vbus_en1_pcc5";\r
+                               nvidia,function = "rsvd1";\r
+                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;\r
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;\r
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;\r
+                               nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;\r
+                       };\r
+               };\r
+\r
+               drive_default: drive {\r
+               };\r
+       };\r
+};\r

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-keys-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-keys-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..c3ea6f2
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-keys-p2530-0930.dtsi
@@ -0,0 +1,25 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       gpio-keys {
+               compatible = "gpio-keys";
+               gpio-keys,name = "gpio-keys";
+
+               power {
+                       label = "Power";
+                       gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_POWER>;
+                       gpio-key,wakeup;
+               };
+
+               sw_lid {
+                       label = "SW LID";
+                       gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>;
+                       linux,code = <SW_LID>;
+                       linux,input-type = <EV_SW>;
+                       gpio-key,wakeup;
+                       debounce-interval = <300>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-pmic-p2530-max7762x.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-pmic-p2530-max7762x.dtsi
new file mode 100644 (file)
index 0000000..bb97552
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-pmic-p2530-max7762x.dtsi
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/mfd/max77620.h>
+#include <dt-bindings/regulator/regulator.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+       i2c@7000d000 {
+               nvidia,bit-banging-xfer-after-shutdown;
+
+               cpu_max77621_reg: max77621@1b {
+                       compatible = "maxim,max77621";
+                       reg = <0x1b>;
+                       interrupts = <0 86 IRQ_TYPE_NONE>;
+                       status = "disabled";
+                       regulator-name = "vdd-cpu";
+                       regulator-min-microvolt = <606250>;
+                       regulator-max-microvolt = <1400000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+                       #thermal-sensor-cells = <0>;
+                       maxim,externally-enable;
+                       maxim,sleep-on-dvs;
+                       maxim,dvs-default-state = <1>;
+                       maxim,external-enable-gpio = <&max77620 5 0>;
+               };
+
+               gpu_max77621_reg: max77621@1c {
+                       compatible = "maxim,max77621";
+                       reg = <0x1c>;
+                       interrupts = <0 86 IRQ_TYPE_NONE>;
+                       status = "disabled";
+                       regulator-name = "vdd-gpu";
+                       regulator-min-microvolt = <606250>;
+                       regulator-max-microvolt = <1400000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+                       #thermal-sensor-cells = <0>;
+                       maxim,externally-enable;
+                       maxim,dvs-default-state = <1>;
+                       maxim,external-enable-gpio = <&max77620 6 0>;
+               };
+
+               max77620: max77620@3c {
+                       compatible = "maxim,max77620";
+                       reg = <0x3c>;
+                       interrupts = <0 86 IRQ_TYPE_NONE>;
+
+                       #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       maxim,enable-clock32k-out;
+
+                       maxim,system-pmic-power-off;
+
+                       maxim,hot-die-threshold-temp = <110000>;
+                       #thermal-sensor-cells = <0>;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&max77620_default>;
+
+                       gpio-init-names = "default";
+                       gpio-init-0 = <&max77620_gpio_default>;
+
+                       max77620_default: pinmux@0 {
+                               pin_gpio0 {
+                                       pins = "gpio0";
+                                       function = "gpio";
+                               };
+
+                               pin_gpio1 {
+                                       pins = "gpio1";
+                                       function = "fps-out";
+                                       drive-push-pull = <1>;
+                                       maxim,fps-source = <FPS_SRC_0>;
+                                       maxim,fps-power-up-period = <7>;
+                                       maxim,fps-power-down-period = <0>;
+                               };
+
+                               pin_gpio2_3 {
+                                       pins = "gpio2", "gpio3";
+                                       function = "fps-out";
+                                       drive-open-drain = <1>;
+                                       maxim,fps-source = <FPS_SRC_0>;
+                               };
+
+                               pin_gpio4 {
+                                       pins = "gpio4";
+                                       function = "32k-out1";
+                               };
+
+                               pin_gpio5_6_7 {
+                                       pins = "gpio5", "gpio6", "gpio7";
+                                       function = "gpio";
+                                       drive-push-pull = <1>;
+                               };
+                       };
+
+                       max77620_gpio_default:gpio_default {
+                               gpio-output-high = <2>;
+                       };
+
+                       watchdog {
+                               maxim,wdt-timeout = <16>;
+                               maxim,wdt-clear-time = <13>;
+                               status = "disabled";
+                               dt-override-status-odm-data = <0x00020000 0x00020000>;
+                       };
+
+                       fps {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               fps@0 {
+                                       reg = <0>;
+                                       maxim,fps-time-period = <2560>;
+                                       maxim,fps-enable-input = <FPS_EN_SRC_EN0>;
+                               };
+
+                               fps@1 {
+                                       reg = <1>;
+                                       maxim,fps-time-period = <2560>;
+                                       maxim,fps-enable-input = <FPS_EN_SRC_EN1>;
+                                       maxim,enable-sleep;
+                               };
+
+                               fps@2 {
+                                       reg = <2>;
+                                       maxim,fps-enable-input = <FPS_EN_SRC_EN0>;
+                               };
+                       };
+
+                       backup-battery {
+                               maxim,backup-battery-charging-current = <100>;
+                               maxim,backup-battery-charging-voltage = <3000000>;
+                               maxim,backup-battery-output-resister = <100>;
+                       };
+
+                       regulators {
+                               in-ldo0-1-supply = <&max77620_sd2>;
+                               in-ldo7-8-supply = <&max77620_sd2>;
+
+                               max77620_sd0: sd0 {
+                                       regulator-name = "vdd_core";
+                                       regulator-min-microvolt = <600000>;
+                                       regulator-max-microvolt = <1400000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                                       maxim,fps-source = <FPS_SRC_1>;
+                                       regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+                               };
+
+                               max77620_sd1: sd1 {
+                                       regulator-name = "vddio-ddr";
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+                                       maxim,fps-source = <FPS_SRC_0>;
+                               };
+
+                               max77620_sd2: sd2 {
+                                       regulator-name = "vdd-pre-reg";
+                                       regulator-min-microvolt = <1350000>;
+                                       regulator-max-microvolt = <1350000>;
+                                       maxim,fps-source = <FPS_SRC_1>;
+                               };
+
+                               max77620_sd3: sd3 {
+                                       regulator-name = "vdd-1v8";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       maxim,fps-source = <FPS_SRC_0>;
+                                       regulator-init-mode = <REGULATOR_MODE_NORMAL>;
+                                       consumers {
+                                               c7 {
+                                                       regulator-consumer-supply = "avdd_pll_utmip";
+                                                       regulator-consumer-device = "tegra-ehci.0";
+                                               };
+                                               c8 {
+                                                       regulator-consumer-supply = "avdd_pll_utmip";
+                                                       regulator-consumer-device = "tegra-ehci.1";
+                                               };
+                                               c9 {
+                                                       regulator-consumer-supply = "avdd_pll_utmip";
+                                                       regulator-consumer-device = "tegra-ehci.2";
+                                               };
+                                               c18 {
+                                                       regulator-consumer-supply = "vdd";
+                                                       regulator-consumer-device = "2-004c";
+                                               };
+                                               c19 {
+                                                       regulator-consumer-supply = "vdd";
+                                                       regulator-consumer-device = "0-004c";
+                                               };
+                                       };
+                               };
+
+                               max77620_ldo0: ldo0 {
+                                       regulator-name = "avdd-sys";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       maxim,fps-source = <FPS_SRC_NONE>;
+                                       consumers {
+                                               c0 {
+                                                       regulator-consumer-supply = "vddio_hsic";
+                                                       regulator-consumer-device = "tegra-ehci.1";
+                                               };
+                                               c1 {
+                                                       regulator-consumer-supply = "vddio_hsic";
+                                                       regulator-consumer-device = "tegra-ehci.2";
+                                               };
+                                       };
+                               };
+
+                               max77620_ldo1: ldo1 {
+                                       regulator-name = "vdd-pex";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       maxim,fps-source = <FPS_SRC_NONE>;
+                               };
+
+                               max77620_ldo2: ldo2 {
+                                       regulator-name = "vddio-sdmmc3";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       maxim,fps-source = <FPS_SRC_NONE>;
+                               };
+
+                               max77620_ldo3: ldo3 {
+                                       regulator-name = "vdd-cam-hv";
+                                       regulator-min-microvolt = <2800000>;
+                                       regulator-max-microvolt = <2800000>;
+                                       maxim,fps-source = <FPS_SRC_NONE>;
+                               };
+
+                               max77620_ldo4: ldo4 {
+                                       regulator-name = "vdd-rtc";
+                                       regulator-min-microvolt = <1250000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       maxim,fps-source = <FPS_SRC_0>;
+                               };
+
+                               max77620_ldo5: ldo5 {
+                                       regulator-name = "avdd-ts-hv";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       maxim,fps-source = <FPS_SRC_NONE>;
+                               };
+
+                               max77620_ldo6: ldo6 {
+                                       regulator-name = "vdd-ts";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       maxim,fps-source = <FPS_SRC_0>;
+                                       maxim,fps-power-up-period = <7>;
+                                       maxim,fps-power-down-period = <0>;
+                               };
+
+                               max77620_ldo7: ldo7 {
+                                       regulator-name = "vdd-gen-pll-edp";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       maxim,fps-source = <FPS_SRC_1>;
+                               };
+
+                               max77620_ldo8: ldo8 {
+                                       regulator-name = "vdd-hdmi-dp";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       maxim,fps-source = <FPS_SRC_NONE>;
+                               };
+                       };
+               };
+       };
+
+       i2c@7000c500 {
+               bq2419x: battery-charger@6b {
+                       compatible = "ti,bq2419x";
+                       reg = <0x6b>;
+
+                       interrupt-parent = <&gpio>;
+                       interrupts = <TEGRA_GPIO(Z, 0) 0x0>;
+                       #extcon-cells = <1>;
+
+                       #thermal-sensor-cells = <0>;
+
+                       battery_charger: charger {
+                               status = "disabled";
+                               regulator-name = "batt_regulator";
+                               regulator-max-microamp = <3000000>;
+                               ti,disbale-suspend-during-charging;
+                               ti,charge-voltage-limit-millivolt = <4200>;
+                               ti,charge-term-current-limit-milliamp = <384>;
+                               ti,ir-comp-voltage-millivolt = <112>;
+                               ti,ir-comp-resister-ohm = <70>;
+                               ti,pre-charge-current-limit-milliamp = <768>;
+                               ti,thermal-regulation-threshold-degc = <120>;
+                       };
+
+                       usb0_vbus: vbus {
+                               regulator-name = "vbus_regulator";
+                               ti,otg-iusb-gpio = <&gpio TEGRA_GPIO(CC, 5) 0>;
+                               consumers {
+                                       c1 {
+                                               regulator-consumer-supply = "usb_vbus";
+                                               regulator-consumer-device = "tegra-ehci.0";
+                                       };
+                               };
+                       };
+               };
+
+               battery-gauge@55 {
+                       status = "disabled";
+                       compatible = "ti,bq27441";
+                       reg = <0x55>;
+                       ti,design-capacity = <7700>;
+                       ti,design-energy = <27720>;
+                       ti,taper-rate = <167>;
+                       ti,terminate-voltage = <3150>;
+                       ti,v-at-chg-term = <4190>;
+                       ti,cc-gain = <0x7F738FE1>;
+                       ti,cc-delta = <0x940A8F4A>;
+                       ti,tz-name = "battery-temp";
+               };
+       };
+
+       dummy_cool_dev: dummy-cool-dev {
+               compatible = "dummy-cooling-dev";
+               #cooling-cells = <2>; /* min followed by max */
+       };
+
+       thermal-zones {
+               PMIC-Die {
+                       polling-delay = <0>; /* milliseconds */
+                       polling-delay-passive = <0>; /* milliseconds */
+
+                       thermal-sensors = <&max77620>;
+                       trips {
+                               die_temp_thresh: hot-die {
+                                       temperature = <120000>;
+                                       type = "active";
+                                       hysteresis = <0>;
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&die_temp_thresh>;
+                                       cooling-device = <&dummy_cool_dev THERMAL_NO_LIMIT
+                                                               THERMAL_NO_LIMIT>;
+                                       contribution = <100>;
+                                       cdev-type = "emergency-balanced";
+                               };
+                       };
+               };
+
+               PMIC-Die-max77621-0 {
+                       status = "disabled";
+                       polling-delay = <0>; /* milliseconds */
+                       polling-delay-passive = <0>; /* milliseconds */
+
+                       trips {
+                               die_temp_thresh_max77621_0: hot-die {
+                                       temperature = <120000>;
+                                       type = "active";
+                                       hysteresis = <0>;
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&die_temp_thresh_max77621_0>;
+                                       cooling-device = <&dummy_cool_dev THERMAL_NO_LIMIT
+                                                               THERMAL_NO_LIMIT>;
+                                       contribution = <100>;
+                                       cdev-type = "emergency-balanced";
+                               };
+                       };
+               };
+
+               PMIC-Die-max77621-1 {
+                       status = "disabled";
+                       polling-delay = <0>; /* milliseconds */
+                       polling-delay-passive = <0>; /* milliseconds */
+
+
+                       trips {
+                               die_temp_thresh_max77621_1: hot-die {
+                                       temperature = <120000>;
+                                       type = "active";
+                                       hysteresis = <0>;
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&die_temp_thresh_max77621_1>;
+                                       cooling-device = <&dummy_cool_dev THERMAL_NO_LIMIT
+                                                               THERMAL_NO_LIMIT>;
+                                       contribution = <100>;
+                                       cdev-type = "emergency-balanced";
+                               };
+                       };
+               };
+
+               Charger-Die {
+                       status = "disabled";
+                       polling-delay = <0>; /* milliseconds */
+                       polling-delay-passive = <0>; /* milliseconds */
+
+                       thermal-sensors = <&bq2419x>;
+                       trips {
+                               die_temp_thresh_chg: hot-die {
+                                       temperature = <120000>;
+                                       type = "active";
+                                       hysteresis = <0>;
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&die_temp_thresh_chg>;
+                                       cooling-device = <&dummy_cool_dev THERMAL_NO_LIMIT
+                                                               THERMAL_NO_LIMIT>;
+                                       contribution = <100>;
+                                       cdev-type = "emergency-balanced";
+                               };
+                       };
+               };
+       };
+
+       extcon {
+               compatible = "simple-bus";
+               device_type = "external-connection";
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-power-dvfs-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-power-dvfs-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..9e8a142
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-power-dvfs-p2530-0930.dtsi
@@ -0,0 +1,130 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+/ {
+       dfll-ovr@70110000 {
+               status = "okay";
+               compatible = "nvidia,tegra210-dfll";
+               reg = <0x0 0x70110000 0x0 0x400>;
+               out-clock-name="dfll_cpu";
+               board-params = <&dfll_ovr_params>;
+
+               pwm_dfll: pwm-pmic-integration {
+                       compatible = "nvidia,tegra210-dfll-pwm";
+                       pwm-1wire-direct;
+                       pwm-data-gpio = <&gpio TEGRA_GPIO(BB, 1) 0>;
+                       #pwm-cells = <2>;
+                       pwm-regulator = <&cpu_ovr_reg>;
+               };
+
+               dfll_ovr_params: dfll-ovr-board-params {
+                       sample-rate = <50000>;
+                       fixed-output-forcing;
+                       cf = <10>;
+                       ci = <0>;
+                       cg = <2>;
+                       droop-cut-value = <0xf>;
+                       droop-restore-ramp = <0x0>;
+                       scale-out-ramp = <0x0>;
+               };
+       };
+
+       dfll-max77621@70110000 {
+               status = "disabled";
+               compatible = "nvidia,tegra210-dfll";
+               reg = <0x0 0x70110000 0x0 0x400>;
+               out-clock-name="dfll_cpu";
+               board-params = <&dfll_max77621_parms>;
+               i2c-pmic-integration = <&i2c_dfll>;
+
+               i2c_dfll: dfll-max77621-integration {
+                       pmic-i2c-address = <0x36>;
+                       pmic-i2c-voltage-register = <0x01>;
+                       i2c-fs-rate = <400000>;
+                       sel-conversion-slope = <1>;
+               };
+
+               dfll_max77621_parms: dfll-max77621-board-params {
+                       sample-rate = <12500>;
+                       fixed-output-forcing;
+                       cf = <10>;
+                       ci = <0>;
+                       cg = <2>;
+                       droop-cut-value = <0xf>;
+                       droop-restore-ramp = <0x0>;
+                       scale-out-ramp = <0x0>;
+               };
+       };
+
+
+       pwm_regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu_ovr_reg: pwm-regulator@0 {
+                       status = "okay";
+                       reg = <0>;
+                       compatible = "regulator-pwm";
+                       pwms = <&pwm_dfll 0 2500>;
+                       regulator-name = "vdd_cpu";
+                       regulator-min-microvolt = <709000>;
+                       regulator-max-microvolt = <1320200>;
+                       regulator-init-microvolt = <1000000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+                       regulator-n-voltages = <33>;
+                       voltage-time-sel = <80>;
+               };
+
+               gpu_ovr_reg: pwm-regulator@1 {
+                       status = "okay";
+                       reg = <1>;
+                       compatible = "regulator-pwm";
+                       pwms = <&tegra_pwm 1 4880>;
+                       regulator-name = "vdd_gpu";
+                       regulator-min-microvolt = <710000>;
+                       regulator-max-microvolt = <1320000>;
+                       regulator-init-microvolt = <1000000>;
+                       regulator-ramp-delay = <500>;
+                       regulator-n-voltages = <62>;
+                       regulator-enable-ramp-delay = <1000>;
+                       regulator-boot-on;
+                       enable-gpio = <&max77620 6 0>;
+               };
+       };
+
+       dvfs_rails {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdd-cpu-rail-ovr@0 {
+                       status = "okay";
+                       reg = <0>;
+                       compatible = "nvidia,tegra210-dvfs-rail";
+                       vdd_cpu-supply = <&cpu_ovr_reg>;
+               };
+
+               vdd-gpu-rail-ovr@1 {
+                       status = "okay";
+                       reg = <1>;
+                       compatible = "nvidia,tegra210-dvfs-rail";
+                       vdd_gpu-supply = <&gpu_ovr_reg>;
+               };
+
+
+               vdd-cpu-rail-max77621@2 {
+                       status = "disabled";
+                       reg = <2>;
+                       compatible = "nvidia,tegra210-dvfs-rail";
+                       vdd_cpu-supply = <&cpu_max77621_reg>;
+               };
+
+               vdd-gpu-rail-max77621@3 {
+                       status = "disabled";
+                       reg = <3>;
+                       compatible = "nvidia,tegra210-dvfs-rail";
+                       vdd_gpu-supply = <&gpu_max77621_reg>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-power-tree-p2595-0000-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-power-tree-p2595-0000-a00.dtsi
new file mode 100644 (file)
index 0000000..840d677
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-power-tree-p2595-0000-a00.dtsi
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "tegra210-pmic-p2530-max7762x.dtsi"
+#include "tegra210-fixed-p2530-max7762x.dtsi"
+#include "tegra210-power-dvfs-p2530-0930.dtsi"
+
+/ {
+
+       i2c@7000d000 {
+               max77620@3c {
+                       regulators {
+                               ldo4 {
+                                       regulator-min-microvolt = <900000>;
+                                       regulator-max-microvolt = <900000>;
+                               };
+                       };
+               };
+       };
+
+       regulators {
+               regulator@2 {
+                       regulator-always-on;
+                       regulator-min-microvolt = <1200000>;
+                       regulator-max-microvolt = <1200000>;
+               };
+
+               vdd_disp_3v0: regulator@12 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <12>;
+                       regulator-name = "vdd-disp-3v0";
+                       regulator-min-microvolt = <3000000>;
+                       regulator-max-microvolt = <3000000>;
+                       gpio = <&gpio TEGRA_GPIO(I, 3) 0>;
+                       regulator-always-on;
+                       enable-active-high;
+               };
+
+               vdd_fan: regulator@13 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <13>;
+                       regulator-name = "vdd-fan";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(E, 4) 0>;
+                       regulator-always-on;
+                       enable-active-high;
+               };
+
+               usb_vbus1: regulator@14 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <14>;
+                       regulator-name = "usb-vbus1";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(CC, 4) 0>;
+                       enable-active-high;
+                       gpio-open-drain;
+               };
+
+               usb_vbus2: regulator@15 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <15>;
+                       regulator-name = "usb-vbus2";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(CC, 5) 0>;
+                       enable-active-high;
+                       gpio-open-drain;
+               };
+
+               usb_vbus3: regulator@16 {
+                       compatible = "regulator-fixed-sync";
+                       reg = <16>;
+                       regulator-name = "usb-vbus3";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(D, 4) 0>;
+                       enable-active-high;
+                       gpio-open-drain;
+               };
+       };
+       i2c@7000c000 {
+               icm20628@68 {
+                       vlogic-supply = <&max77620_ldo3>;
+                       vdd-supply = <&vdd_3v3>;
+               };
+
+               ak8975@0c {
+                       vid = <&max77620_ldo3>;
+                       vdd = <&vdd_3v3>;
+               };
+       };
+
+       i2c@7000c500 {
+               battery-charger@6b {
+                       status = "disabled";
+               };
+       };
+
+       efuse@7000f800 {
+               vpp_fuse-supply = <&max77620_sd3>;
+       };
+
+       host1x {
+               /* tegradc.0 */
+               dc@54200000 {
+                       avdd_hdmi-supply = <&max77620_ldo8>;
+                       avdd_hdmi_pll-supply = <&max77620_sd3>;
+                       vdd_hdmi_5v0-supply = <&vdd_hdmi>;
+               };
+
+               vi {
+                       avdd_dsi_csi-supply = <&max77620_gpio7>;
+               };
+       };
+
+       sound {
+               ldoen-supply = <&vdd_sys_boost>;
+               spkvdd-supply = <&vdd_sys_boost>;
+               dbvdd-supply = <&vdd_sys_boost>;
+               dmicvdd-supply = <&max77620_sd3>;
+       };
+
+       udc@7d000000 {
+               avdd_usb-supply = <&vdd_3v3>;
+               avdd_pll_utmip-supply = <&max77620_sd3>;
+               usb_bat_chg-supply = <&battery_charger>;
+       };
+
+       xusb@70090000 {
+               usb_vbus0-supply = <&battery_reg>;
+               usb_vbus1-supply = <&usb_vbus1>;
+               usb_vbus2-supply = <&usb_vbus2>;
+               usb_vbus3-supply = <&usb_vbus3>;
+               hvdd_usb-supply = <&vdd_3v3>;
+               avdd_pll_utmip-supply = <&max77620_sd3>;
+               vddio_hsic-supply = <&max77620_ldo0>;
+               avddio_usb-supply = <&max77620_ldo1>;
+               dvdd_sata-supply = <&max77620_ldo8>;
+               avddio_pll_uerefe-supply = <&max77620_ldo7>;
+       };
+
+       xudc@700d0000 {
+                usb_vbus0-supply = <&battery_reg>;
+                hvdd_usb-supply = <&vdd_3v3>;
+                avdd_pll_utmip-supply = <&max77620_sd3>;
+                avddio_usb-supply = <&max77620_ldo1>;
+                avddio_pll_uerefe-supply = <&max77620_ldo7>;
+        };
+
+       otg@7d000000 {
+               usb_vbus-supply = <&battery_reg>;
+       };
+
+       sdhci@700b0600 {
+               vddio_sdmmc-supply = <&max77620_sd3>;
+               vddio_sd_slot-supply = <&vdd_3v3>;
+       };
+
+       sdhci@700b0400 {
+               vddio_sdmmc-supply = <&max77620_sd3>;
+               vddio_sd_slot-supply = <&vdd_3v3>;
+       };
+
+       sdhci@700b0200 {
+               vddio_sdmmc-supply = <&max77620_sd3>;
+               vddio_sd_slot-supply = <&vdd_3v3>;
+       };
+
+       sdhci@700b0000 {
+               vddio_sdmmc-supply = <&max77620_ldo2>;
+               vddio_sd_slot-supply = <&en_vdd_sd>;
+       };
+
+       sata@70020000 {
+               hvdd_sata-supply = <&max77620_sd3>;
+               vddio_pex_sata-supply = <&max77620_sd3>;
+               avdd_sata-supply = <&max77620_sd3>;
+               vdd_sata-supply = <&max77620_ldo8>;
+               avdd_sata_pll-supply = <&max77620_ldo8>;
+       };
+
+       bluedroid_pm {
+               avdd-supply = <&battery_reg>;
+               dvdd-supply = <&max77620_sd3>;
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-powermon-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-powermon-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..b4a05b5
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-powermon-p2530-0930.dtsi
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+/ {
+       i2c@7000c400 {
+               ina3221x: ina3221x@40 {
+                       compatible = "ti,ina3221x";
+                       reg = <0x40>;
+                       ti,trigger-config = <0x7003>;
+                       ti,continuous-config = <0x7607>;
+                       ti,enable-forced-continuous;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       #io-channel-cells = <1>;
+                       channel@0 {
+                               reg = <0x0>;
+                               ti,rail-name = "VDD_BATT";
+                               ti,shunt-resistor-mohm = <5>;
+                               ti,current-critical-limit-ma = <6800>;
+                       };
+
+                       channel@1 {
+                               reg = <0x1>;
+                               ti,rail-name = "VDD_VBUS";
+                               ti,shunt-resistor-mohm = <2200>;
+                               ti,current-critical-limit-ma = <1800>;
+                       };
+
+                       channel@2 {
+                               reg = <0x2>;
+                               ti,rail-name = "VDD_MODEM";
+                               ti,shunt-resistor-mohm = <5>;
+                       };
+               };
+
+               ina226@46 {
+                       status = "disabled";
+                       compatible = "ti,ina226x";
+                       reg = <0x46>;
+                       ti,rail-name = "VDD_DDR";
+                       ti,continuous-config = <0x0407>;
+                       ti,trigger-config = <0x0403>;
+                       ti,resistor = <10>;
+                       ti,calibration-data = <0x0DF1>;
+                       ti,power-lsb = <143>;
+                       ti,divisor = <25>;
+                       ti,precision-multiplier = <1000>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-pwm-fan-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-pwm-fan-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..72543a5
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-pwm-fan-p2530-0930.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/ {
+       pwm_fan_shared_data: pfsd {
+               num_resources = <0>;
+               secret = <47>;
+               active_steps = <10>;
+               active_rpm = <0 1000 2000 3000 4000 5000 6000 7000 10000 11000>;
+               active_rru = <40 2 1 1 1 1 1 1 1 1>;
+               active_rrd = <40 2 1 1 1 1 1 1 1 1>;
+               state_cap_lookup = <2 2 2 2 3 3 3 4 4 4>;
+               pwm_period = <45334>;
+               pwm_id = <3>;
+               step_time = <100>; /* mesecs */
+               state_cap = <7>;
+               active_pwm_max = <256>;
+               tach_gpio =  <TEGRA_GPIO(G, 0)>; /* TEGRA_GPIO_PG0 */
+               pwm_gpio = <TEGRA_GPIO(E, 7)>; /* TEGRA_GPIO_PE7 */
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-sdhci-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-sdhci-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..d92d572
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-sdhci-p2530-0930.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/ {
+       sdhci@700b0600 {
+               tap-delay = <4>;
+               trim-delay = <8>;
+               nvidia,is-ddr-tap-delay;
+               nvidia,ddr-tap-delay = <0>;
+               mmc-ocr-mask = <0>;
+               dqs-trim-delay = <17>;
+               max-clk-limit = <200000000>;
+               bus-width = <8>;
+               id = <3>;
+               calib-3v3-offsets = <0x0505>;
+               calib-1v8-offsets = <0x0505>;
+               built-in;
+               compad-vref-3v3 = <0x7>;
+               compad-vref-1v8 = <0x7>;
+               nvidia,en-io-trim-volt;
+               nvidia,is-emmc;
+       };
+
+       sdhci@700b0400 {
+               tap-delay = <1>;
+               trim-delay = <3>;
+               mmc-ocr-mask = <0>;
+               max-clk-limit = <204000000>;
+               ddr-clk-limit = <48000000>;
+               bus-width = <4>;
+               id = <2>;
+               calib-3v3-offsets = <0x007D>;
+               calib-1v8-offsets = <0x7B7B>;
+               compad-vref-3v3 = <0x1>;
+               compad-vref-1v8 = <0x2>;
+               default-drv-type = <1>;
+               nvidia,en-io-trim-volt;
+       };
+
+       sdhci@700b0200 {
+               tap-delay = <4>;
+               trim-delay = <8>;
+               mmc-ocr-mask = <0>;
+               max-clk-limit = <204000000>;
+               bus-width = <4>;
+               id = <1>;
+               calib-3v3-offsets = <0x0505>;
+               calib-1v8-offsets = <0x0505>;
+               compad-vref-3v3 = <0x7>;
+               compad-vref-1v8 = <0x7>;
+               default-drv-type = <1>;
+               nvidia,en-io-trim-volt;
+       };
+
+       sdhci@700b0000 {
+               tap-delay = <2>;
+               trim-delay = <2>;
+               max-clk-limit = <204000000>;
+               ddr-clk-limit = <48000000>;
+               bus-width = <4>;
+               id = <0>;
+               mmc-ocr-mask = <3>;
+               calib-3v3-offsets = <0x007D>;
+               calib-1v8-offsets = <0x7B7B>;
+               compad-vref-3v3 = <0x1>;
+               compad-vref-1v8 = <0x2>;
+               cd-gpios = <&gpio TEGRA_GPIO_PZ1 0>;
+               nvidia,en-io-trim-volt;
+               nvidia,limit-vddio-max-volt;
+       };
+};

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-thermal-fan-est-p2530-0930.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-thermal-fan-est-p2530-0930.dtsi
new file mode 100644 (file)
index 0000000..a9da77d
--- /dev/null
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-thermal-fan-est-p2530-0930.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/ {
+       thermal_fan_est_shared_data: tfesd {
+               secret = <37>;
+               toffset = <0>;
+               polling_period = <1100>;
+               ndevs = <2>;
+               cdev_type = "pwm-fan";
+               tzp_governor_name = "pid_thermal_gov";
+
+               dev1 {
+                       dev_data = "Tboard_tegra";
+                       coeffs = <50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+               };
+
+               dev2 {
+                       dev_data = "Tdiode_tegra";
+                       coeffs = <50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
+               };
+       };
+
+       thermal-fan-est {
+               name = "thermal-fan-est";
+               num_resources = <0>;
+               shared_data = <&thermal_fan_est_shared_data>;
+               trip_length = <10>;
+               active_trip_temps = <0 57000 63000 74000 85000
+                               140000 150000 160000 170000 180000>;
+               active_hysteresis = <0 20000 7000 10000 10000
+                               0 0 0 0 0>;
+       };
+};