Removed from CL-DVFS driver direct read of CPU DFLL boot rate parameter
in kernel command line. Instead passed boot rate via DFLL data in safe
DVFS structure.
Bug
200085579
Change-Id: I2025b7245ae2773720b21a1cf1e8b75d9c992636
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/733949
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* If boot loader has set dfll clock, then dfll freq is
* passed in kernel command line from bootloader
*/
- if (tegra_dfll_boot_req_khz())
+ if (tegra_dfll_boot_req_khz()) {
+ cpu_dvfs->dfll_data.dfll_boot_khz = tegra_dfll_boot_req_khz();
rail->dfll_mode = true;
+ }
return 0;
}
u32 val;
int status;
unsigned long int rate;
- unsigned long int dfll_boot_req_khz = tegra_dfll_boot_req_khz();
+ unsigned long int dfll_boot_req_khz =
+ cld->safe_dvfs->dfll_data.dfll_boot_khz;
+
+ if (!dfll_boot_req_khz) {
+ pr_err("%s: Failed to sync DFLL boot rate\n", __func__);
+ return -EINVAL;
+ }
output_enable(cld);
u32 tune0_simon_mask;
u32 tune1;
bool tune0_low_at_cold;
+
unsigned long droop_rate_min;
unsigned long use_dfll_rate_min;
unsigned long out_rate_min;
unsigned long max_rate_boost;
+ /* Boot frequency if DFLL is enabled by boot-loader; zero otherwise */
+ unsigned long dfll_boot_khz;
+
int tune_high_min_millivolts;
int tune_high_margin_mv;
int min_millivolts;