clock: tegra21: Assign clock IDs to bridges users

Assigned clock IDs to users of shared buses for bridges: HOST1x,
MSELECT, and APE

Bug 1608456

Change-Id: Ie4495c7b65729fd71c98494895af6c379bcc6f60
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/740947
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/drivers/platform/tegra/tegra21_clocks.c b/drivers/platform/tegra/tegra21_clocks.c
index 9ce3d2a1c57ed064f47cdf4cac18f356b807fdc4..904c949d343158348e0756ced2547c1538b58ded 100644 (file)
--- a/drivers/platform/tegra/tegra21_clocks.c
+++ b/drivers/platform/tegra/tegra21_clocks.c
@@ -9587,22 +9587,22 @@ static struct clk tegra_list_clks[] = {
        SHARED_LIMIT("floor.gbus",      "floor.gbus",           NULL,   &tegra_clk_gbus, NULL,  0, 0, 0),
        SHARED_LIMIT("floor.profile.gbus", "profile.gbus",      "floor", &tegra_clk_gbus, NULL, 0, 0, 0),
 
-       SHARED_CLK("nv.host1x", "tegra_host1x",         "host1x", &tegra_clk_host1x, NULL,  0, 0, 0),
-       SHARED_CLK("vi.host1x", "tegra_vi",             "host1x", &tegra_clk_host1x, NULL,  0, 0, 0),
-       SHARED_CLK("vii2c.host1x", "546c0000.i2c",      "host1x", &tegra_clk_host1x, NULL,  0, 0, 0),
+       SHARED_CLK("nv.host1x", "tegra_host1x",         "host1x", &tegra_clk_host1x, NULL,  0, 0, TEGRA210_CLK_ID_HOST1X_NV_USER),
+       SHARED_CLK("vi.host1x", "tegra_vi",             "host1x", &tegra_clk_host1x, NULL,  0, 0, TEGRA210_CLK_ID_HOST1X_VI_USER),
+       SHARED_CLK("vii2c.host1x", "546c0000.i2c",      "host1x", &tegra_clk_host1x, NULL,  0, 0, TEGRA210_CLK_ID_HOST1X_VII2C_USER),
        SHARED_LIMIT("cap.host1x", "cap.host1x",        NULL,     &tegra_clk_host1x, NULL,  0, SHARED_CEILING, 0),
        SHARED_LIMIT("cap.vcore.host1x", "cap.vcore.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING, 0),
        SHARED_LIMIT("floor.host1x", "floor.host1x",    NULL,     &tegra_clk_host1x, NULL,  0, 0, 0),
        SHARED_CLK("override.host1x", "override.host1x", NULL,    &tegra_clk_host1x, NULL,  0, SHARED_OVERRIDE, 0),
 
-       SHARED_CLK("cpu.mselect",         "cpu",        "mselect",   &tegra_clk_mselect, NULL,  0, 0, 0),
-       SHARED_CLK("pcie.mselect",        "tegra_pcie", "mselect",   &tegra_clk_mselect, NULL,  0, 0, 0),
+       SHARED_CLK("cpu.mselect",         "cpu",        "mselect",   &tegra_clk_mselect, NULL,  0, 0, TEGRA210_CLK_ID_MSELECT_CPU_USER),
+       SHARED_CLK("pcie.mselect",        "tegra_pcie", "mselect",   &tegra_clk_mselect, NULL,  0, 0, TEGRA210_CLK_ID_MSELECT_PCIE_USER),
        SHARED_LIMIT("cap.vcore.mselect", "cap.vcore.mselect", NULL, &tegra_clk_mselect, NULL,  0, SHARED_CEILING, 0),
        SHARED_CLK("override.mselect",    "override.mselect",  NULL, &tegra_clk_mselect, NULL,  0, SHARED_OVERRIDE, 0),
 
-       SHARED_CLK("adma.ape",          NULL,           "adma.ape",  &tegra_clk_ape, NULL,  0, 0, 0),
-       SHARED_CLK("adsp.ape",          NULL,           "adsp.ape",  &tegra_clk_ape, NULL,  0, 0, 0),
-       SHARED_CLK("xbar.ape",          NULL,           "xbar.ape",  &tegra_clk_ape, NULL,  0, 0, 0),
+       SHARED_CLK("adma.ape",          NULL,           "adma.ape",  &tegra_clk_ape, NULL,  0, 0, TEGRA210_CLK_ID_APE_ADMA_USER),
+       SHARED_CLK("adsp.ape",          NULL,           "adsp.ape",  &tegra_clk_ape, NULL,  0, 0, TEGRA210_CLK_ID_APE_ADSP_USER),
+       SHARED_CLK("xbar.ape",          NULL,           "xbar.ape",  &tegra_clk_ape, NULL,  0, 0, TEGRA210_CLK_ID_APE_XBAR_USER),
        SHARED_LIMIT("cap.vcore.ape",   "cap.vcore.ape", NULL,       &tegra_clk_ape, NULL,  0, SHARED_CEILING, 0),
        SHARED_CLK("override.ape",      "override.ape",  NULL,       &tegra_clk_ape, NULL,  0, SHARED_OVERRIDE, 0),
 

diff --git a/include/dt-bindings/clk/tegra210-clk.h b/include/dt-bindings/clk/tegra210-clk.h
index b6e3a66f53ebbb1b4709b4e6fb213c2bedb7a6d6..8fd842d30fe504d775897717bc0812a9a40408ca 100644 (file)
--- a/include/dt-bindings/clk/tegra210-clk.h
+++ b/include/dt-bindings/clk/tegra210-clk.h
@@ -303,7 +303,16 @@
 /* IDs 376 ... 389 are reserved */
 #define TEGRA210_CLK_ID_GBUS                           390
 #define TEGRA210_CLK_ID_GBUS_GM20B_USER                        391
+/* IDs 392 ... 399 are reserved */
+#define TEGRA210_CLK_ID_HOST1X_NV_USER                 400
+#define TEGRA210_CLK_ID_HOST1X_VI_USER                 401
+#define TEGRA210_CLK_ID_HOST1X_VII2C_USER              402
+#define TEGRA210_CLK_ID_MSELECT_CPU_USER               403
+#define TEGRA210_CLK_ID_MSELECT_PCIE_USER              404
+#define TEGRA210_CLK_ID_APE_ADMA_USER                  405
+#define TEGRA210_CLK_ID_APE_ADSP_USER                  406
+#define TEGRA210_CLK_ID_APE_XBAR_USER                  407
 
-/* FIXME: IDs 392 ... 479 to be assigned */
+/* FIXME: IDs 408 ... 479 to be assigned */
 
 #endif /* _DT_BINDINGS_CLK_TEGRA210_CLK_ID_H */