]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
arm: tegra: Ram repair for slow cluster
authorBibek Basu <bbasu@nvidia.com>
Tue, 2 Sep 2014 10:18:09 +0000 (15:48 +0530)
committerMatthew Pedro <mapedro@nvidia.com>
Wed, 17 Sep 2014 05:17:17 +0000 (22:17 -0700)
Do ram repair for slow cluster also during
boot

Bug 1528461

Change-Id: I71ed7891aaff48f0b87438ad029b22ced9be0f04
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/494787
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/pm.h

index 275e4035b0063ff86c7554e85181725ba43badbc..7e98f7c570f96cfc7000df23ca8cbbbcc5e23f07 100644 (file)
@@ -776,13 +776,31 @@ static void __init tegra_perf_init(void)
 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
 static void __init tegra_ramrepair_init(void)
 {
+#define RAM_REPAIR_TIMEOUT 500 /*usec */
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
        if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
 #endif
                u32 reg;
+               u32 timeout = RAM_REPAIR_TIMEOUT;
+               /* ram repair for Fast Cluster0*/
                reg = readl(FLOW_CTRL_RAM_REPAIR);
                reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
                writel(reg, FLOW_CTRL_RAM_REPAIR);
+
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+               /* Ram Repair for Slow Cluster1 */
+               reg = readl(FLOW_CTRL_RAM_REPAIR_1);
+               reg |= FLOW_CTRL_RAM_REPAIR_REQ;
+               writel(reg, FLOW_CTRL_RAM_REPAIR_1);
+               do {
+                       udelay(1);
+                       reg = readl(FLOW_CTRL_RAM_REPAIR_1);
+               } while (!(reg & FLOW_CTRL_RAM_REPAIR_STS) && (timeout--));
+               if (!timeout) {
+                       pr_err("Slow Cluster Ram Repair failed");
+                       pr_err("reg 0x%x timeout %d\n", reg, timeout);
+               }
+#endif
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
        }
 #endif
index d2eb583985ae7e52a349601723893caf2f21b551..fe8af42fd67990e820cbaed3fc4cac592abad4b7 100644 (file)
@@ -138,6 +138,9 @@ unsigned long tegra_lp1bb_emc_min_rate_get(void);
 #define FLOW_CTRL_RAM_REPAIR_STS       (1<<1)
 #define FLOW_CTRL_RAM_REPAIR_REQ       (1<<0)
 
+#define FLOW_CTRL_RAM_REPAIR_1 \
+       (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x58)
+
 #define FUSE_SKU_DIRECT_CONFIG \
        (IO_ADDRESS(TEGRA_FUSE_BASE) + 0x1F4)
 #define FUSE_SKU_DISABLE_ALL_CPUS      (1<<5)