SDIO clock gate is enabled for following T12x
boards:
ardbeg
loki
vcm30_t124
bug
1299485
Change-Id: I01f3777269c8d82899ac427c91618f3a2962a2eb
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304727
Reviewed-by: Automatic_Commit_Validation_User
MMC_UHS_MASK_SDR50,
.calib_3v3_offsets = 0x7676,
.calib_1v8_offsets = 0x7676,
- .disable_clock_gate = true,
};
static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
.calib_3v3_offsets = 0x7676,
.calib_1v8_offsets = 0x7676,
- .disable_clock_gate = true,
};
static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
.tap_delay = 0x0F,
.ddr_clk_limit = 30000000,
.is_8bit = false,
- .disable_clock_gate = true,
};
static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {