ARM: tegra: power: Swap ActMon barrier and read fence

To assure completion of the previous writes through Tegra interconnect
activity monitor code used memory write barrier followed by read fence.

Removed the preceding memory barrier, since it has no additional to
read fence effect (given Tegra IO mapping as device). Added barrier
after read fence. The latter is needed to avoid partial overlap of
read operation and propagation delay after read (if any). Such overlap
is possible since architectural timer used as delay counter is not MMIO
register.

Bug 1484343

Change-Id: I71537f5c013ac2c3f04eea600d89ec333ec5ab19
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/390283
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra3_actmon.c b/arch/arm/mach-tegra/tegra3_actmon.c
index c13ae38abd97bae2588e4ccae21b8cc37d431718..afdf5c3b2fbd0767495eb603a315149758bc445d 100644 (file)
--- a/arch/arm/mach-tegra/tegra3_actmon.c
+++ b/arch/arm/mach-tegra/tegra3_actmon.c
@@ -148,8 +148,8 @@ static inline void actmon_writel(u32 val, u32 offset)
 }
 static inline void actmon_wmb(void)
 {
-       wmb();
        actmon_readl(ACTMON_GLB_STATUS);
+       dsb();
 }
 
 #define offs(x)                (dev->reg + x)