struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
void *ctx_ptr = NULL;
u32 data;
- int ret;
-
- c->g->ops.fifo.disable_channel(c);
- ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
- if (ret) {
- gk20a_err(dev_from_gk20a(g),
- "failed to preempt channel\n");
- return ret;
- }
/* Channel gr_ctx buffer is gpu cacheable.
Flush and invalidate before cpu update. */
vunmap(ctx_ptr);
- /* enable channel */
- gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
- gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
- ccsr_channel_enable_set_true_f());
-
return 0;
}