]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
video: tegra: host: use read only flag for firmwares
authorDeepak Nibade <dnibade@nvidia.com>
Fri, 13 Sep 2013 10:12:26 +0000 (15:42 +0530)
committerDan Willemsen <dwillemsen@nvidia.com>
Fri, 27 Sep 2013 02:45:57 +0000 (19:45 -0700)
- make use of read only flag from smmu while loading firmwares
- to enable this first add extra parameter 'rw_flag' to function
  nvhost_memmgr_pin() and nvhost_nvmap_pin() to pass read-write flag
- nvhost_nvmap_pin() will then set appropriate attributes based on
  the flag passed

- below are the available flags which can be passed
mem_flag_none : do not mark anything
mem_flag_read_only : mark read only
mem_flag_write_only : mark write only

- make use of 'mem_flag_read_only' for MSENC, TSEC and VIC firmwares
  by passing this parameter from below :
msenc_read_ucode()
vic03_read_ucode()
tsec_read_ucode()

- add 'mem_flag_none' in all other calls to nvhost_memmgr_pin()

Bug 1309863

Change-Id: I7c3d3525e403fd46921a30502f70e79ecf74fca8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/274282
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
16 files changed:
drivers/video/tegra/host/gk20a/gr_gk20a.c
drivers/video/tegra/host/gk20a/mm_gk20a.c
drivers/video/tegra/host/gr3d/gr3d.c
drivers/video/tegra/host/gr3d/gr3d_t114.c
drivers/video/tegra/host/gr3d/gr3d_t20.c
drivers/video/tegra/host/gr3d/gr3d_t30.c
drivers/video/tegra/host/host1x/host1x_cdma.c
drivers/video/tegra/host/mpe/mpe.c
drivers/video/tegra/host/msenc/msenc.c
drivers/video/tegra/host/nvhost_memmgr.c
drivers/video/tegra/host/nvhost_memmgr.h
drivers/video/tegra/host/nvmap.c
drivers/video/tegra/host/nvmap.h
drivers/video/tegra/host/tsec/tsec.c
drivers/video/tegra/host/user_hwctx.c
drivers/video/tegra/host/vic03/vic03.c

index 86c56a7e4920371b7a7d79829f05ef54cddf59c2..d81318a2efea7ccbb5b335c3142403382be8a8a6 100644 (file)
@@ -2544,7 +2544,7 @@ static int gr_gk20a_init_comptag(struct gk20a *g, struct gr_gk20a *gr)
 
        gr->compbit_store.mem.sgt =
                nvhost_memmgr_pin(memmgr, gr->compbit_store.mem.ref,
-                               dev_from_gk20a(g));
+                               dev_from_gk20a(g), mem_flag_none);
        if (IS_ERR(gr->compbit_store.mem.sgt)) {
                ret = PTR_ERR(gr->compbit_store.mem.sgt);
                goto clean_up;
index 287043066b0b51d9c53d0bb3b498fc43416e5fde..f9a59ec9ea394556f9cded645361c34cdb7f0164 100644 (file)
@@ -374,7 +374,7 @@ static int alloc_gmmu_pages(struct vm_gk20a *vm, u32 order,
        memset(va, 0, len);
        nvhost_memmgr_munmap(r, va);
 
-       *sgt = nvhost_memmgr_pin(client, r, dev_from_vm(vm));
+       *sgt = nvhost_memmgr_pin(client, r, dev_from_vm(vm), mem_flag_none);
        if (IS_ERR(*sgt)) {
                *sgt = NULL;
                goto err_alloced;
@@ -967,7 +967,7 @@ static u64 gk20a_vm_map(struct vm_gk20a *vm,
        }
 
        /* pin buffer to get phys/iovmm addr */
-       bfr.sgt = nvhost_memmgr_pin(memmgr, r, d);
+       bfr.sgt = nvhost_memmgr_pin(memmgr, r, d, mem_flag_none);
        if (IS_ERR(bfr.sgt)) {
                /* Falling back to physical is actually possible
                 * here in many cases if we use 4K phys pages in the
index 4f8fb5eb5160e35ea93b98ea1c104a32ed108d5b..1a4edc9646f1b6614c258d1b920c8849a83c86fc 100644 (file)
@@ -108,7 +108,7 @@ struct host1x_hwctx *nvhost_3dctx_alloc_common(struct host1x_hwctx_handler *p,
                ctx->restore_virt = NULL;
 
        ctx->restore_sgt = nvhost_memmgr_pin(memmgr, ctx->restore,
-                       &ch->dev->dev);
+                       &ch->dev->dev, mem_flag_none);
        if (IS_ERR(ctx->restore_sgt))
                goto fail_pin;
        ctx->restore_phys = nvhost_memmgr_dma_addr(ctx->restore_sgt);
index 8469beda3a2027c612071b82f674b87d1465f4ee..fc99a4948623a1b35f60734f8ab02f64d46c6652 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host 3d hardware context
  *
- * Copyright (c) 2011-2013 NVIDIA Corporation.
+ * Copyright (c) 2011-2013 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -440,7 +440,8 @@ struct nvhost_hwctx_handler *nvhost_gr3d_t114_ctxhandler_init(
        if (!save_ptr)
                goto fail_mmap;
 
-       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev);
+       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev,
+                                                               mem_flag_none);
        if (IS_ERR(p->save_sgt))
                goto fail_pin;
        p->save_phys = nvhost_memmgr_dma_addr(p->save_sgt);
index 1ef37357f2e5b93e992b7ae0ca2c16fa6bd5c375..49e424fe9035e5fdd725d553307b69665c4a9740 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host 3D for Tegra2
  *
- * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -385,7 +385,8 @@ struct nvhost_hwctx_handler *nvhost_gr3d_t20_ctxhandler_init(
        if (!save_ptr)
                goto fail_mmap;
 
-       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev);
+       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev,
+                                                               mem_flag_none);
        if (IS_ERR(p->save_sgt))
                goto fail_pin;
        p->save_phys = nvhost_memmgr_dma_addr(p->save_sgt);
index c26d80e76db2553c308814077be25e9c3da3b4b4..00cd0812f2d7db9902b1c103afdd7ad4d0b0d820 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host 3D for Tegra3
  *
- * Copyright (c) 2011-2013 NVIDIA Corporation.
+ * Copyright (c) 2011-2013 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -423,7 +423,8 @@ struct nvhost_hwctx_handler *nvhost_gr3d_t30_ctxhandler_init(
        if (!save_ptr)
                goto fail_mmap;
 
-       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev);
+       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev,
+                                                               mem_flag_none);
        if (IS_ERR(p->save_sgt))
                goto fail_pin;
        p->save_phys = nvhost_memmgr_dma_addr(p->save_sgt);
@@ -509,7 +510,8 @@ int nvhost_gr3d_t30_read_reg(
        }
        cmdbuf_ptr = mem_ptr + 1;
 
-       mem_sgt = nvhost_memmgr_pin(memmgr, mem, &channel->dev->dev);
+       mem_sgt = nvhost_memmgr_pin(memmgr, mem, &channel->dev->dev,
+                                                       mem_flag_none);
        if (IS_ERR(mem_sgt)) {
                err = -ENOMEM;
                mem_sgt = NULL;
index c71277e5945c86c4917c4f93e52d7342ca988339..3948574b104a8f806d118956c8f3f64c2f8755ef 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Command DMA
  *
- * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -92,7 +92,7 @@ static int push_buffer_init(struct push_buffer *pb)
 
        /* pin pushbuffer and get physical address */
        pb->sgt = nvhost_memmgr_pin(mgr, pb->mem,
-                       &cdma_to_dev(cdma)->dev->dev);
+                       &cdma_to_dev(cdma)->dev->dev, mem_flag_none);
        if (IS_ERR(pb->sgt)) {
                err = PTR_ERR(pb->sgt);
                pb->sgt = 0;
index 05bfce79404a96dd6dcc099e98ff92cde2e0bbab..ef629c5d28760dfb9ef4e51135c67eff553329c9 100644 (file)
@@ -475,7 +475,7 @@ static struct nvhost_hwctx *ctxmpe_alloc(struct nvhost_hwctx_handler *h,
                goto fail_mmap;
 
        ctx->restore_sgt = nvhost_memmgr_pin(memmgr, ctx->restore,
-                       &ch->dev->dev);
+                       &ch->dev->dev, mem_flag_none);
        if (IS_ERR(ctx->restore_sgt))
                goto fail_pin;
        ctx->restore_phys = sg_dma_address(ctx->restore_sgt->sgl);
@@ -605,7 +605,8 @@ struct nvhost_hwctx_handler *nvhost_mpe_ctxhandler_init(u32 syncpt,
        if (!save_ptr)
                goto fail_mmap;
 
-       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev);
+       p->save_sgt = nvhost_memmgr_pin(memmgr, p->save_buf, &ch->dev->dev,
+                                                               mem_flag_none);
        if (IS_ERR(p->save_sgt))
                goto fail_pin;
        p->save_phys = sg_dma_address(p->save_sgt->sgl);
index 8e3873b482119674187bfeeb543ce0e928dc7dbd..5efa99ce7185e3fad03c67149a81db8b61fd5353 100644 (file)
@@ -286,7 +286,7 @@ int msenc_read_ucode(struct platform_device *dev, const char *fw_name)
        }
 
        m->pa = nvhost_memmgr_pin(nvhost_get_host(dev)->memmgr, m->mem_r,
-                       &dev->dev);
+                       &dev->dev, mem_flag_read_only);
        if (IS_ERR(m->pa)) {
                dev_err(&dev->dev, "nvmap pin failed for ucode");
                err = PTR_ERR(m->pa);
index ff777483353c4b8c11a7c5dd04e3acc04aa696ad..4787ddbed1afc066205abd4ae3ae61019890fa98 100644 (file)
@@ -145,12 +145,12 @@ void nvhost_memmgr_put(struct mem_mgr *mgr, struct mem_handle *handle)
 }
 
 struct sg_table *nvhost_memmgr_pin(struct mem_mgr *mgr,
-               struct mem_handle *handle, struct device *dev)
+               struct mem_handle *handle, struct device *dev, int rw_flag)
 {
        switch (nvhost_memmgr_type((u32)((uintptr_t)handle))) {
 #ifdef CONFIG_TEGRA_GRHOST_USE_NVMAP
        case mem_mgr_type_nvmap:
-               return nvhost_nvmap_pin(mgr, handle, dev);
+               return nvhost_nvmap_pin(mgr, handle, dev, rw_flag);
                break;
 #endif
 #ifdef CONFIG_TEGRA_GRHOST_USE_DMABUF
@@ -327,7 +327,7 @@ int nvhost_memmgr_pin_array_ids(struct mem_mgr *mgr,
                if (IS_ERR(h))
                        return -EINVAL;
 
-               sgt = nvhost_memmgr_pin(mgr, h, &dev->dev);
+               sgt = nvhost_memmgr_pin(mgr, h, &dev->dev, mem_flag_none);
                if (IS_ERR(sgt))
                        return PTR_ERR(sgt);
 
index 22e0838e00135f0f376350478f8ad201eeb09bc4..8843ff8fce18ff3df840c6e72f362c2f04c2acdd 100644 (file)
@@ -51,6 +51,12 @@ enum mem_mgr_flag {
        mem_mgr_flag_write_combine = 1,
 };
 
+enum mem_rw_flag {
+       mem_flag_none = 0,
+       mem_flag_read_only = 1,
+       mem_flag_write_only = 2,
+};
+
 enum mem_mgr_type {
        mem_mgr_type_nvmap = 0,
        mem_mgr_type_dmabuf = 1,
@@ -72,7 +78,8 @@ struct mem_handle *nvhost_memmgr_get(struct mem_mgr *,
 void nvhost_memmgr_put(struct mem_mgr *mgr, struct mem_handle *handle);
 struct sg_table *nvhost_memmgr_pin(struct mem_mgr *,
                struct mem_handle *handle,
-               struct device *dev);
+               struct device *dev,
+               int rw_flag);
 void nvhost_memmgr_unpin(struct mem_mgr *mgr,
                struct mem_handle *handle, struct device *dev,
                struct sg_table *sgt);
index 87c0b8e8dc4d6d57dd7e439b275764c02ac597d4..593360a0c8a94a02f355d14ac8334e60fe3bff2d 100644 (file)
@@ -119,7 +119,8 @@ void delete_priv(void *_priv)
 
 struct sg_table *nvhost_nvmap_pin(struct mem_mgr *mgr,
                struct mem_handle *handle,
-               struct device *dev)
+               struct device *dev,
+               int rw_flag)
 {
        struct nvmap_handle_ref *ref = (struct nvmap_handle_ref *)handle;
        struct nvmap_client *nvmap = (struct nvmap_client *)mgr;
@@ -217,6 +218,11 @@ struct sg_table *nvhost_nvmap_pin(struct mem_mgr *mgr,
                DEFINE_DMA_ATTRS(attrs);
                dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
 
+               if (rw_flag == mem_flag_read_only)
+                       dma_set_attr(DMA_ATTR_READ_ONLY, &attrs);
+               else if (rw_flag == mem_flag_write_only)
+                       dma_set_attr(DMA_ATTR_WRITE_ONLY, &attrs);
+
                ents = dma_map_sg_attrs(dev, sgt->sgl, sgt->nents, 0, &attrs);
                if (!ents) {
                        mutex_unlock(&priv->lock);
index 6af7ab8aadfbc37883ce2262f9eeae92eb2e0c43..4bfc069804eabf33ee3282d393c2b897f069608e 100644 (file)
@@ -35,7 +35,7 @@ struct mem_handle *nvhost_nvmap_alloc(struct mem_mgr *mgr,
                size_t size, size_t align, int flags, unsigned int heap_flags);
 void nvhost_nvmap_put(struct mem_mgr *mgr, struct mem_handle *handle);
 struct sg_table *nvhost_nvmap_pin(struct mem_mgr *mgr,
-               struct mem_handle *handle, struct device *dev);
+               struct mem_handle *handle, struct device *dev, int rw_flag);
 void nvhost_nvmap_unpin(struct mem_mgr *mgr, struct mem_handle *handle,
                struct device *dev, struct sg_table *sgt);
 void *nvhost_nvmap_mmap(struct mem_handle *handle);
index 7f42cc33b0b6fbfd59a10eecb880edd0d632e986..15ded7bf671df89862965e89a10924fb391ca7f0 100644 (file)
@@ -412,7 +412,7 @@ int tsec_read_ucode(struct platform_device *dev, const char *fw_name)
        }
 
        m->pa = nvhost_memmgr_pin(nvhost_get_host(dev)->memmgr, m->mem_r,
-                       &dev->dev);
+                       &dev->dev, mem_flag_read_only);
        if (IS_ERR(m->pa)) {
                dev_err(&dev->dev, "nvmap pin failed for ucode");
                err = PTR_ERR(m->pa);
index c7717371688a9cd3a7f82ad69d980bfa4d87c5c8..2f2c4f63ad633b3a2c5a406ce84d480b23d41b35 100644 (file)
@@ -121,7 +121,7 @@ int user_hwctx_set_save(struct user_hwctx *ctx,
                return PTR_ERR(buf);
 
        sgt = nvhost_memmgr_pin(ctx->hwctx.memmgr, buf,
-                       &ctx->hwctx.channel->dev->dev);
+                       &ctx->hwctx.channel->dev->dev, mem_flag_none);
        if (IS_ERR(sgt))
                return PTR_ERR(sgt);
 
@@ -157,7 +157,7 @@ int user_hwctx_set_restore(struct user_hwctx *ctx,
                return PTR_ERR(buf);
 
        sgt = nvhost_memmgr_pin(ctx->hwctx.memmgr, buf,
-                       &ctx->hwctx.channel->dev->dev);
+                       &ctx->hwctx.channel->dev->dev, mem_flag_none);
        if (IS_ERR(sgt))
                return PTR_ERR(sgt);
 
index cd909d6aded551677cc76f5ef4fe37c4f370f5ed..adc205c8ff99980790d8e0f5c5a2ebe1feec0b6d 100644 (file)
@@ -241,7 +241,7 @@ static int vic03_read_ucode(struct platform_device *dev)
        }
 
        v->ucode.sgt = nvhost_memmgr_pin(v->host->memmgr, v->ucode.mem_r,
-               &dev->dev);
+               &dev->dev, mem_flag_read_only);
        if (IS_ERR(v->ucode.sgt)) {
                nvhost_err(&dev->dev, "nvmap pin failed for ucode, %ld",
                        PTR_ERR(v->ucode.sgt));
@@ -489,7 +489,7 @@ static struct nvhost_hwctx *vic03_alloc_hwctx(struct nvhost_hwctx_handler *h,
        ctx->hwctx.save_slots = 0;
 
        ctx->restore_sgt = nvhost_memmgr_pin(nvmap,
-                       ctx->restore, &ch->dev->dev);
+                       ctx->restore, &ch->dev->dev, mem_flag_none);
        if (IS_ERR(ctx->restore_sgt))
                goto fail_pin;
        ctx->restore_phys = nvhost_memmgr_dma_addr(ctx->restore_sgt);