ARM: tegra: power: Add read fences in power gating

To assure post of the previous writes through Tegra interconnect
added read fences in the following power gating code paths:

- Seconadry CPU boot ungating (path taken on Tegra11, Tegra14, Tegra12)
- GPU rail clamps gating/ungating (path taken on Tegra12, Tegra13)
- MC client ungating flush done (path taken on all platforms)

Bug 1484343

Change-Id: Ie09ef37135beae0ed0beb1cd4d7e96187ba9be26
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/385403
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 50659cab17c49194eb69ef65481ae3e36daa2385..f755f939ffbf5386322266831d34b98f53644988 100644 (file)
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -269,6 +269,7 @@ static int tegra11x_power_up_cpu(unsigned int cpu)
 
                reg = PMC_TOGGLE_START | TEGRA_CPU_POWERGATE_ID(cpu);
                pmc_writel(reg, PWRGATE_TOGGLE);
+               pmc_readl(PWRGATE_TOGGLE);
        }
 
        return 0;

diff --git a/arch/arm/mach-tegra/powergate-t11x.c b/arch/arm/mach-tegra/powergate-t11x.c
index b846660c2a034d59566fdf875afa8fecb570817a..954d3a39610609d3ac2806fdcb01a47968967cd8 100644 (file)
--- a/arch/arm/mach-tegra/powergate-t11x.c
+++ b/arch/arm/mach-tegra/powergate-t11x.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -505,6 +505,7 @@ int tegra11x_powergate_mc_flush_done(int id)
                rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
                rst_ctrl &= ~(1 << mcClientBit);
                mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
+               mc_read(MC_CLIENT_HOTRESET_CTRL);
 
                spin_unlock_irqrestore(&tegra11x_powergate_lock, flags);
        }

diff --git a/arch/arm/mach-tegra/powergate-t12x.c b/arch/arm/mach-tegra/powergate-t12x.c
index 4998e2cd24a98a63c24f944529686950ad7f307f..05764ccdd45d7966d2e9e75e49348d8d51137ed5 100644 (file)
--- a/arch/arm/mach-tegra/powergate-t12x.c
+++ b/arch/arm/mach-tegra/powergate-t12x.c
@@ -393,6 +393,7 @@ int tegra12x_powergate_mc_flush_done(int id)
                rst_ctrl = mc_read(rst_ctrl_reg);
                rst_ctrl &= ~(1 << mcClientBit);
                mc_write(rst_ctrl, rst_ctrl_reg);
+               mc_read(rst_ctrl_reg);
 
                spin_unlock_irqrestore(&tegra12x_powergate_lock, flags);
        }
@@ -416,6 +417,7 @@ static int tegra12x_gpu_powergate(int id, struct powergate_partition_info *pg_in
 
        /* enable clamp */
        pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
+       pmc_read(PMC_GPU_RG_CNTRL_0);
 
        udelay(10);
 
@@ -488,6 +490,7 @@ static int tegra12x_gpu_unpowergate(int id,
 
        /* disable clamp */
        pmc_write(0, PMC_GPU_RG_CNTRL_0);
+       pmc_read(PMC_GPU_RG_CNTRL_0);
 
        udelay(10);
 

diff --git a/arch/arm/mach-tegra/powergate-t14x.c b/arch/arm/mach-tegra/powergate-t14x.c
index cb1e1e232395c536fb567a178429484817edb887..2ee85b593e3534f194b465e6dcbe8433f32b3c34 100644 (file)
--- a/arch/arm/mach-tegra/powergate-t14x.c
+++ b/arch/arm/mach-tegra/powergate-t14x.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -459,6 +459,7 @@ int tegra14x_powergate_mc_flush_done(int id)
                rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
                rst_ctrl &= ~(1 << mcClientBit);
                mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
+               mc_read(MC_CLIENT_HOTRESET_CTRL);
 
                spin_unlock_irqrestore(&tegra14x_powergate_lock, flags);
        }

diff --git a/arch/arm/mach-tegra/powergate-t30.c b/arch/arm/mach-tegra/powergate-t30.c
index 14a5f7529ae41df57ae6bcc6678cc891924972e2..8612873fcd5ce33c82b678b117bc44c8b27e0c7d 100644 (file)
--- a/arch/arm/mach-tegra/powergate-t30.c
+++ b/arch/arm/mach-tegra/powergate-t30.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-214, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -308,7 +308,7 @@ int tegra3_powergate_mc_flush_done(int id)
                rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
                rst_ctrl &= ~(1 << mcClientBit);
                mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
-
+               mc_read(MC_CLIENT_HOTRESET_CTRL);
                spin_unlock_irqrestore(&tegra3_powergate_lock, flags);
        }
 

diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index cf576fcae96ce58262c53f3221648afd51cd3c19..1c41ae37ff64ce04d2da8ba3c13639d6ea07bd71 100644 (file)
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -85,6 +85,7 @@ int tegra_powergate_set(int id, bool new_state)
                /* CPU ungated in s/w only during boot/resume with outer
                   waiting loop and no contention from other CPUs */
                pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
+               pmc_read(PWRGATE_TOGGLE);
                spin_unlock_irqrestore(lock, flags);
                return 0;
        }