arm: tegra: t124: Enable SMMU for SDMMC

Enable SMMU for SDMMC2 and SDMMC3. IOVA space
is seperate for each SDMMC.

Bug 1380096

Change-Id: I63689196e11914646c61eaa8cddad9e75d6cce30
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/400926
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
GVS: Gerrit_Virtual_Submit

diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 8d64768504082f4efd174a69d386a48655b84d0c..05580b44a9a46eefea30b1c90451f060f02f859d 100644 (file)
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -1871,6 +1871,8 @@ struct swgid_fixup tegra_swgid_fixup_t124[] = {
        { .name = "mpe",        .swgids = SWGID(MPE), },
        { .name = "tegra-aes",  .swgids = SWGID(VDE), },
        { .name = "nvavp",      .swgids = SWGID(AVPC) | SWGID(A9AVP), },
+       { .name = "sdhci-tegra.1",      .swgids = SWGID(SDMMC2A) },
+       { .name = "sdhci-tegra.2",      .swgids = SWGID(SDMMC3A) },
        { .name = "serial8250", .swgids = SWGID(PPCS), },
        { .name = "serial-tegra",       .swgids = SWGID(PPCS), },
        { .name = "dtv",        .swgids = SWGID(PPCS), },