arm: tegra12: support for 0x80 embedded SKU

Added DVFS support for CD575MI SKU 0x80 always on personality
CPU DVFS: Max Freq 1912Mhz. Switch to PLLX below 0 DegC
          and fixed voltage
SOC DVFS: Vmax 1000mv constant. Lesser freq below 0 DegC
          EMC dvfs max freq 792Mhz
GPU DVFS: Max Freq 756Mhz and thermal bump up of voltage
          by 50mv below 0 DegC

Added DVFS support for CD575MI SKU 0x80 default personality
CPU DVFS: Max Freq 2116Mhz. Switch to PLLX below 0 DegC
          and fixed voltage
SOC DVFS: Vmax @ 1100mv below 0 DegC, scaling eanbled
          EMC dvfs max freq 924Mhz
GPU DVFS: Max Freq 924Mhz and thermal bump up of voltage
          by 50mv below 0 DegC. Max gpu freq below 0degC is 852Mhz

Bug 1563635

Change-Id: I3f05d4b7b4a0f86785a9cf9076c9c8b0c3fd18f0
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/657110
(cherry picked from commit 6c235706a1eca1fe64b476e6368cb432051aa94d)
Reviewed-on: http://git-master/r/716286
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Tested-by: Venkat Moganty <vmoganty@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pmic-pm375-0000-c00-00.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pmic-pm375-0000-c00-00.dtsi
index 9a36dc4f814d7d140304087fd145299fea8f6b19..8bca8fa574c5f9cf681ec8798239ae75f01308d1 100644 (file)
--- a/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pmic-pm375-0000-c00-00.dtsi
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pmic-pm375-0000-c00-00.dtsi
@@ -93,6 +93,7 @@
                                    regulator-max-microvolt = <1350000>;
                                    regulator-min-microamp = <3500000>;
                                    regulator-max-microamp = <3500000>;
+                                   regulator-init-microvolt = <1000000>;
                                    regulator-always-on;
                                    regulator-boot-on;
                                    ams,ext-control = <AS3722_EXT_CONTROL_ENABLE1>;

diff --git a/arch/arm/mach-tegra/board-norrin-power.c b/arch/arm/mach-tegra/board-norrin-power.c
index 28e8b59416c448bbb4786b33d55268257c696791..ef174540ba25d00dea602c5744005c06f04ba6eb 100644 (file)
--- a/arch/arm/mach-tegra/board-norrin-power.c
+++ b/arch/arm/mach-tegra/board-norrin-power.c
@@ -366,6 +366,7 @@ int __init norrin_soctherm_init(void)
        }
 
        if (board_info.board_id == BOARD_PM374 ||
+               board_info.board_id == BOARD_PM375 ||
                board_info.board_id == BOARD_E1971 ||
                board_info.board_id == BOARD_E1991) {
                tegra_add_cpu_vmin_trips(
@@ -379,9 +380,14 @@ int __init norrin_soctherm_init(void)
                        &norrin_soctherm_data.therm[THERM_PLL].num_trips);
        }
 
+       if (board_info.board_id == BOARD_PM375)
+               tegra_add_cpu_clk_switch_trips(
+                       norrin_soctherm_data.therm[THERM_CPU].trips,
+                       &norrin_soctherm_data.therm[THERM_CPU].num_trips);
        tegra_get_pmu_board_info(&pmu_board_info);
 
-       if (pmu_board_info.board_id == BOARD_PM374)
+       if ((pmu_board_info.board_id == BOARD_PM374) ||
+               (pmu_board_info.board_id == BOARD_PM375))
                norrin_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
        else
                pr_warn("soctherm THERMTRIP not supported on PMU (BOARD_P%d)\n",

diff --git a/arch/arm/mach-tegra/tegra12_speedo.c b/arch/arm/mach-tegra/tegra12_speedo.c
index 4ce03cec989b02c408b39db7d6a66428a2fb858f..8e53df717326484e9df8e30e043ad2c64ad4b537 100644 (file)
--- a/arch/arm/mach-tegra/tegra12_speedo.c
+++ b/arch/arm/mach-tegra/tegra12_speedo.c
@@ -142,6 +142,17 @@ static void rev_sku_to_speedo_ids(int rev, int sku)
                gpu_speedo_id = 3;
                threshold_index = 1;
                break;
+       case 0x80:
+               cpu_speedo_id = 8;
+               soc_speedo_id = 4;
+               gpu_speedo_id = 6;
+               if (chip_personality == always_on) {
+                       cpu_speedo_id = 7;
+                       soc_speedo_id = 3;
+                       gpu_speedo_id = 5;
+               }
+               threshold_index = 0;
+               break;
        default:
                pr_warn("Tegra12: Unknown SKU %d\n", sku);
                cpu_speedo_id = 0;
@@ -328,6 +339,10 @@ int tegra_core_speedo_mv(void)
                return 1150;
        case 2:
                return 1040;
+       case 3:
+               return 1000;
+       case 4:
+               return 1100;
        default:
                BUG();
        }

diff --git a/drivers/platform/tegra/dvfs.c b/drivers/platform/tegra/dvfs.c
index ba3aa7c562bd91244410990b687fe8d1184ba72b..ae1f34e5e46284f92a9608afbd1e0ba3e17b9b31 100644 (file)
--- a/drivers/platform/tegra/dvfs.c
+++ b/drivers/platform/tegra/dvfs.c
@@ -36,6 +36,7 @@
 #include <linux/clk/tegra.h>
 #include <linux/tegra-soc.h>
 #include <linux/of_platform.h>
+#include <linux/tegra-fuse.h>
 
 #include "board.h"
 #include <linux/platform/tegra/clock.h>
@@ -47,6 +48,7 @@
 struct dvfs_rail *tegra_cpu_rail;
 struct dvfs_rail *tegra_core_rail;
 struct dvfs_rail *tegra_gpu_rail;
+int tegra_override_dfll_range;
 
 static LIST_HEAD(dvfs_rail_list);
 static DEFINE_MUTEX(dvfs_lock);
@@ -2583,7 +2585,7 @@ static int tegra_dvfs_rail_set_clk_switch_cdev_state(
         */
        static int first = 1;
 
-       if (CONFIG_TEGRA_USE_DFLL_RANGE == TEGRA_USE_DFLL_CDEV_CNTRL) {
+       if (tegra_override_dfll_range == TEGRA_USE_DFLL_CDEV_CNTRL) {
                if ((rail->therm_scale_idx != cur_state) || first) {
                        rail->therm_scale_idx = cur_state;
                        if (rail->therm_scale_idx == 0)

diff --git a/drivers/platform/tegra/tegra12_clocks.c b/drivers/platform/tegra/tegra12_clocks.c
index 2a2b6c20dcf09525c346027d1206af773999e20c..6a7205db6b50a2f099deddd47eb14952212d9b41 100644 (file)
--- a/drivers/platform/tegra/tegra12_clocks.c
+++ b/drivers/platform/tegra/tegra12_clocks.c
@@ -4412,7 +4412,7 @@ static int tegra12_use_dfll_cb(const char *arg, const struct kernel_param *kp)
 {
        int ret = 0;
        unsigned int old_use_dfll;
-       if (CONFIG_TEGRA_USE_DFLL_RANGE != TEGRA_USE_DFLL_CDEV_CNTRL) {
+       if (tegra_override_dfll_range != TEGRA_USE_DFLL_CDEV_CNTRL) {
                old_use_dfll = use_dfll;
                param_set_int(arg, kp);
                ret =  tegra_clk_dfll_range_control(use_dfll);
@@ -8999,7 +8999,7 @@ static void __init tegra12_dfll_cpu_late_init(struct clk *c)
        if (!ret) {
                c->state = OFF;
                if (tegra_platform_is_silicon()) {
-                       if (CONFIG_TEGRA_USE_DFLL_RANGE !=
+                       if (tegra_override_dfll_range !=
                                        TEGRA_USE_DFLL_CDEV_CNTRL)
                                use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
 #ifdef CONFIG_ARCH_TEGRA_13x_SOC

diff --git a/drivers/platform/tegra/tegra12_dvfs.c b/drivers/platform/tegra/tegra12_dvfs.c
index ff1853d1519dbcc5b12fcb8ed8b413f10e2a151f..bd8b1ab51863ac9089e9ab62e2e7a14190d9669f 100644 (file)
--- a/drivers/platform/tegra/tegra12_dvfs.c
+++ b/drivers/platform/tegra/tegra12_dvfs.c
@@ -48,9 +48,21 @@ static int gpu_vmin_offsets[] = { 0, -20, };
 static int vdd_core_vmin_trips_table[MAX_THERMAL_LIMITS] = { 20, };
 static int vdd_core_therm_floors_table[MAX_THERMAL_LIMITS] = { 950, };
 
+static int vdd_core_vmin_trips_table_sku80[MAX_THERMAL_LIMITS] = { 0, };
+static int vdd_core_therm_floors_table_sku80[MAX_THERMAL_LIMITS] = { 1100, };
+
+static int vdd_core_vmin_trips_table_sku80_alwayson[MAX_THERMAL_LIMITS] = { 0, };
+static int vdd_core_therm_floors_table_sku80_alwayson[MAX_THERMAL_LIMITS] = { 1000, };
+
 static int vdd_core_vmax_trips_table[MAX_THERMAL_LIMITS] = { 62,   72,   82, };
 static int vdd_core_therm_caps_table[MAX_THERMAL_LIMITS] = { 1130, 1100, 1060, };
 
+static int vdd_core_vmax_trips_table_sku80_alwayson[] = { -40, 0, };
+static int vdd_core_therm_caps_table_sku80_alwayson[] = { 950, 1000, };
+
+static int vdd_core_vmax_trips_table_sku80[] = { -40, 0, 70};
+static int vdd_core_therm_caps_table_sku80[] = { 1050, 1100, 1050};
+
 #ifndef CONFIG_TEGRA_CPU_VOLT_CAP
 static int vdd_cpu_vmax_trips_table[MAX_THERMAL_LIMITS] = { 62,   72,   82, };
 static int vdd_cpu_therm_caps_table[MAX_THERMAL_LIMITS] = { 1230, 1210, 1180, };
@@ -152,8 +164,8 @@ void __init tegra12x_vdd_cpu_align(int step_uv, int offset_uv)
 
 /* CPU DVFS tables */
 static unsigned long cpu_max_freq[] = {
-/* speedo_id   0        1        2        3        4        5       6          */
-               2014500, 2320500, 2116500, 2524500, 1811000, 2218500, 1912500,
+/* speedo_id   0        1        2        3        4        5        6         7        8*/
+               2014500, 2320500, 2116500, 2524500, 1811000, 2218500, 1912500, 1912500, 2116500,
 };
 
 static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
@@ -189,6 +201,137 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
                 */
                .clk_switch_trips = {34,}
        },
+       /* Entry for Embedded SKU CD575M Always On*/
+       {
+               .speedo_id = 6,
+               .process_id = -1,
+               .dfll_tune_data  = {
+                       .tune0          = 0x005020FF,
+                       .tune0_high_mv  = 0x005040FF,
+                       .tune1          = 0x00000060,
+                       .droop_rate_min = 1000000,
+                       .tune_high_min_millivolts = 900,
+                       .min_millivolts = 720,
+               },
+               .max_mv = 1120,
+               .freqs_mult = KHZ,
+               .speedo_scale = 100,
+               .voltage_scale = 1000,
+               .cvb_table = {
+                       /*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
+                       {204000,        {1112619, -29295, 402}, {950000, 0, 0}},
+                       {306000,        {1150460, -30585, 402}, {950000, 0, 0}},
+                       {408000,        {1190122, -31865, 402}, {950000, 0, 0}},
+                       {510000,        {1231606, -33155, 402}, {950000, 0, 0}},
+                       {612000,        {1274912, -34435, 402}, {950000, 0, 0}},
+                       {714000,        {1320040, -35725, 402}, {950000, 0, 0}},
+                       {816000,        {1366990, -37005, 402}, {950000, 0, 0}},
+                       {918000,        {1415762, -38295, 402}, {950000, 0, 0}},
+                       {1020000,       {1466355, -39575, 402}, {950000, 0, 0}},
+                       {1122000,       {1518771, -40865, 402}, {950000, 0, 0}},
+                       {1224000,       {1573009, -42145, 402}, {970000, 0, 0}},
+                       {1326000,       {1629068, -43435, 402}, {1100000, 0, 0}},
+                       {1428000,       {1686950, -44715, 402}, {1100000, 0, 0}},
+                       {1530000,       {1746653, -46005, 402}, {1100000, 0, 0}},
+                       {1632000,       {1808179, -47285, 402}, {1200000, 0, 0}},
+                       {1734000,       {1871526, -48575, 402}, {1200000, 0, 0}},
+                       {1836000,       {1936696, -49855, 402}, {1200000, 0, 0}},
+                       {1912500,       {2003687, -51145, 402}, {1200000, 0, 0}},
+                       {      0 ,      {      0,      0,   0}, {}},
+               },
+               .vmin_trips_table = { 20, 35, 55, 75, 120 },
+               .therm_floors_table = { 900, 800, 790, 770, 750, },
+       },
+       /* Entry for Embedded SKU CD575MI Always On*/
+       {
+               .speedo_id = 7,
+               .process_id = -1,
+               .dfll_tune_data  = {
+                       .tune0          = 0x005040FF,
+                       .tune0_high_mv  = 0x005040FF,
+                       .tune1          = 0x00000060,
+                       .droop_rate_min = 1000000,
+                       .tune_high_min_millivolts = 950,
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1100,
+               .freqs_mult = KHZ,
+               .speedo_scale = 100,
+               .voltage_scale = 1000,
+               .cvb_table = {
+                       /*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
+                       {204000,        {1112619, -29295, 402}, {950000, 0, 0}},
+                       {306000,        {1150460, -30585, 402}, {950000, 0, 0}},
+                       {408000,        {1190122, -31865, 402}, {950000, 0, 0}},
+                       {510000,        {1231606, -33155, 402}, {950000, 0, 0}},
+                       {612000,        {1274912, -34435, 402}, {950000, 0, 0}},
+                       {714000,        {1320040, -35725, 402}, {950000, 0, 0}},
+                       {816000,        {1366990, -37005, 402}, {950000, 0, 0}},
+                       {918000,        {1415762, -38295, 402}, {950000, 0, 0}},
+                       {1020000,       {1466355, -39575, 402}, {950000, 0, 0}},
+                       {1122000,       {1518771, -40865, 402}, {950000, 0, 0}},
+                       {1224000,       {1573009, -42145, 402}, {970000, 0, 0}},
+                       {1326000,       {1629068, -43435, 402}, {1100000, 0, 0}},
+                       {1428000,       {1686950, -44715, 402}, {1100000, 0, 0}},
+                       {1530000,       {1746653, -46005, 402}, {1100000, 0, 0}},
+                       {1632000,       {1808179, -47285, 402}, {1200000, 0, 0}},
+                       {1734000,       {1871526, -48575, 402}, {1200000, 0, 0}},
+                       {1836000,       {1936696, -49855, 402}, {1200000, 0, 0}},
+                       {1912500,       {2003687, -51145, 402}, {1200000, 0, 0}},
+                       {      0 ,      {      0,      0,   0}, {}},
+               },
+               /*
+                * < 0 : Set CPU clock source as PLLX
+                * > 0 : Set CPU clock source as DFLL
+                */
+               .clk_switch_trips = {0,}
+       },
+       /* Entry for Embedded SKU CD575MI */
+       {
+               .speedo_id = 8,
+               .process_id = -1,
+               .dfll_tune_data  = {
+                       .tune0          = 0x005040FF,
+                       .tune0_high_mv  = 0x005040FF,
+                       .tune1          = 0x00000060,
+                       .droop_rate_min = 1000000,
+                       .tune_high_min_millivolts = 950,
+                       .min_millivolts = 950,
+               },
+               .max_mv = 1210,
+               .freqs_mult = KHZ,
+               .speedo_scale = 100,
+               .voltage_scale = 1000,
+               .cvb_table = {
+                       /*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
+                       {204000,        {1112619, -29295, 402}, {950000, 0, 0}},
+                       {306000,        {1150460, -30585, 402}, {950000, 0, 0}},
+                       {408000,        {1190122, -31865, 402}, {950000, 0, 0}},
+                       {510000,        {1231606, -33155, 402}, {950000, 0, 0}},
+                       {612000,        {1274912, -34435, 402}, {950000, 0, 0}},
+                       {714000,        {1320040, -35725, 402}, {950000, 0, 0}},
+                       {816000,        {1366990, -37005, 402}, {950000, 0, 0}},
+                       {918000,        {1415762, -38295, 402}, {950000, 0, 0}},
+                       {1020000,       {1466355, -39575, 402}, {950000, 0, 0}},
+                       {1122000,       {1518771, -40865, 402}, {950000, 0, 0}},
+                       {1224000,       {1573009, -42145, 402}, {970000, 0, 0}},
+                       {1326000,       {1629068, -43435, 402}, {1100000, 0, 0}},
+                       {1428000,       {1686950, -44715, 402}, {1100000, 0, 0}},
+                       {1530000,       {1746653, -46005, 402}, {1100000, 0, 0}},
+                       {1632000,       {1808179, -47285, 402}, {1130000, 0, 0}},
+                       {1734000,       {1871526, -48575, 402}, {1130000, 0, 0}},
+                       {1836000,       {1936696, -49855, 402}, {1210000, 0, 0}},
+                       {1938000,       {2003687, -51145, 402}, {1300000, 0, 0}},
+                       {2014500,       {2054787, -52095, 402}, {1300000, 0, 0}},
+                       {2116500,       {2124957, -53385, 402}, {1300000, 0, 0}},
+                       {      0 ,      {      0,      0,   0}, {}},
+               },
+               /*
+                * < 0 : Set CPU clock source as PLLX
+                * > 0 : Set CPU clock source as DFLL
+                */
+               .clk_switch_trips = {0,}
+       },
        {
                .speedo_id = -1,
                .process_id = -1,
@@ -249,7 +392,7 @@ static struct dvfs cpu_dvfs = {
 };
 
 /* Core DVFS tables */
-static const int core_millivolts[MAX_DVFS_FREQS] = {
+static int core_millivolts[MAX_DVFS_FREQS] = {
        800, 850, 900, 950, 1000, 1040, 1050, 1100, 1150};
 
 #define CORE_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \
@@ -387,6 +530,148 @@ static struct dvfs core_dvfs_table[] = {
        OVRRD_DVFS("sdmmc4",         -1, -1, 1, KHZ,      1,      1,  82000,  82000,  136000, 136000,  136000, 136000,  200000),
 };
 
+/* CD575MI Always On Personality */
+static struct dvfs core_dvfs_table_embedded_alwayson[] = {
+       /* Core voltages (mV):                   800,    850,    900,    950,    1000 */
+       /* Clock limits for internal blocks, PLLs */
+
+       CORE_DVFS("emc",        3, -1, 1, KHZ, 1,      1,      1,      600000,   792000),
+
+        CORE_DVFS("cpu_lp",     3, -1, 1, KHZ,  1,      1,      1,      804000, 912000),
+
+        CORE_DVFS("sbus",       3, -1, 1, KHZ,  1,      1,      1,      264000,         312000),
+
+       CORE_DVFS("vic03",      3, -1, 1, KHZ,  1,      1,      1,      492000,  588000),
+
+       CORE_DVFS("tsec",       3, -1, 1, KHZ,  1,      1,      1,      492000,  588000),
+
+       CORE_DVFS("msenc",      3, -1, 1, KHZ,  1,      1,      1,      384000,  384000),
+
+       CORE_DVFS("se",         3, -1, 1, KHZ,  1,      1,      1,      336000,  384000),
+
+       CORE_DVFS("vde",        3, -1, 1, KHZ,  1,      1,      1,      336000,  384000),
+
+        CORE_DVFS("host1x",     3, -1, 1, KHZ,  1,      1,      1,      240000,         348000),
+
+       CORE_DVFS("vi",         3, -1, 1, KHZ,  1,      1,      1,      600000,  600000),
+
+       CORE_DVFS("isp",        3, -1, 1, KHZ,  1,      1,      1,      600000,  600000),
+
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+        CORE_DVFS("c2bus",      3, -1, 1, KHZ,  1,      1,      1,      336000,         384000),
+
+        CORE_DVFS("c3bus",      3, -1, 1, KHZ,  1,      1,      1,      492000,         588000),
+#else
+       CORE_DVFS("cbus",      3, -1, 1, KHZ,  1,      1,      1,      168000,   216000),
+#endif
+
+       CORE_DVFS("c4bus",      3, -1, 1, KHZ,  1,      1,      1,      600000,  600000),
+
+       CORE_DVFS("pll_m",  3, -1, 1, KHZ,   1,      1,      1,      1066000,    1066000),
+       CORE_DVFS("pll_c",  3, -1, 1, KHZ,   1,      1,      1,      1066000,    1066000),
+       CORE_DVFS("pll_c2", 3, -1, 1, KHZ,   1,      1,      1,      1066000,    1066000),
+       CORE_DVFS("pll_c3", 3, -1, 1, KHZ,   1,      1,      1,      1066000,    1066000),
+
+       /* Core voltages (mV):                   800,    850,    900,    950,    1000 */
+       /* Clock limits for I/O peripherals */
+       CORE_DVFS("dsia",   3, -1, 1, KHZ,   1,      1,      1,      750000,      750000),
+       CORE_DVFS("dsib",   3, -1, 1, KHZ,   1,      1,      1,      750000,      750000),
+       CORE_DVFS("dsialp", 3, -1, 1, KHZ,   1,      1,      1,      102000,      156000),
+       CORE_DVFS("dsiblp", 3, -1, 1, KHZ,   1,      1,      1,      102000,      156000),
+       CORE_DVFS("hdmi",   3, -1, 1, KHZ,   1,      1,      1,      297000,      297000),
+
+       CORE_DVFS("pciex",  3,  -1, 1, KHZ,   1,      1,      1,     250000,      500000),
+       CORE_DVFS("mselect", 3, -1, 1, KHZ,  1,      1,      1,      204000,      408000),
+
+       /* Core voltages (mV):                          800,    850,    900,     950,    1000 */
+       /* xusb clocks */
+       CORE_DVFS("xusb_falcon_src", 3, -1, 1, KHZ,       1,      1,      1,      336000,        336000),
+       CORE_DVFS("xusb_host_src",   3, -1, 1, KHZ,       1,      1,      1,      112000,        112000),
+       CORE_DVFS("xusb_dev_src",    3, -1, 1, KHZ,       1,      1,      1,      112000,        112000),
+       CORE_DVFS("xusb_ss_src",     3, -1, 1, KHZ,       1,      1,      1,      12000,         120000),
+       CORE_DVFS("xusb_fs_src",     3, -1, 1, KHZ,       1,      1,      1,      48000,          48000),
+       CORE_DVFS("xusb_hs_src",     3, -1, 1, KHZ,       1,      1,      1,      60000,          60000),
+
+       CORE_DVFS("hda",             3, -1, 1, KHZ,       1,      1,      1,      108000,        108000),
+       CORE_DVFS("hda2codec_2x",    3, -1, 1, KHZ,       1,      1,      1,      48000,          48000),
+
+       CORE_DVFS("sor0",            3, -1, 1, KHZ,       1,      1,      1,      540000,        540000),
+       OVRRD_DVFS("sdmmc1",         3, -1, 1, KHZ,      1,      1,       1,    82000,          136000),
+       OVRRD_DVFS("sdmmc3",         3, -1, 1, KHZ,      1,      1,       1,    82000,          136000),
+       OVRRD_DVFS("sdmmc4",         3, -1, 1, KHZ,      1,      1,       1,    82000,          136000),
+};
+
+/* CD575MI */
+static struct dvfs core_dvfs_table_embedded[] = {
+       /* Core voltages (mV):                   800,    850,    900,    950,    1000,   1040,  1050,     1100  */
+       /* Clock limits for internal blocks, PLLs */
+
+       CORE_DVFS("emc",        4, -1, 1, KHZ, 1,      1,      1,      1,       1,       1,     792000, 924000),
+
+        CORE_DVFS("cpu_lp",     4, -1, 1, KHZ,  1,      1,      1,      1,     1,      1,      1044000, 1044000),
+
+        CORE_DVFS("sbus",       4, -1, 1, KHZ,  1,      1,      1,      1,     1,      1,       348000, 372000),
+
+       CORE_DVFS("vic03",      4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       660000, 708000),
+
+       CORE_DVFS("tsec",       4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       660000, 708000),
+
+       CORE_DVFS("msenc",      4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       432000, 456000),
+
+       CORE_DVFS("se",         4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       432000, 456000),
+
+       CORE_DVFS("vde",        4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       432000, 456000),
+
+        CORE_DVFS("host1x",     4, -1, 1, KHZ,  1,      1,      1,      1,     1,      1,       372000, 408000),
+
+       CORE_DVFS("vi",         4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       600000, 600000),
+
+       CORE_DVFS("isp",        4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       600000, 600000),
+
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+        CORE_DVFS("c2bus",      4, -1, 1, KHZ,  1,      1,      1,      1,     1,      1,       432000, 456000),
+
+        CORE_DVFS("c3bus",      4, -1, 1, KHZ,  1,      1,      1,      1,     1,      1,       660000, 708000),
+#else
+       CORE_DVFS("cbus",      4, -1, 1, KHZ,  1,      1,      1,      1,       1,      1,       216000, 372000),
+#endif
+
+       CORE_DVFS("c4bus",      4, -1, 1, KHZ,  1,      1,      1,      1,      1,      1,       600000, 600000),
+
+       CORE_DVFS("pll_m",  4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       1066000, 1200000),
+       CORE_DVFS("pll_c",  4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       1066000, 1066000),
+       CORE_DVFS("pll_c2", 4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       1066000, 1066000),
+       CORE_DVFS("pll_c3", 4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       1066000, 1066000),
+
+       /* Core voltages (mV):               800,    850,    900,    950,       1000    1050    1100*/
+       /* Clock limits for I/O peripherals */
+       CORE_DVFS("dsia",   4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       750000, 750000),
+       CORE_DVFS("dsib",   4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       750000, 750000),
+       CORE_DVFS("dsialp", 4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       156000, 156000),
+       CORE_DVFS("dsiblp", 4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       156000, 156000),
+       CORE_DVFS("hdmi",   4, -1, 1, KHZ,   1,      1,      1,      1,         1,      1,       297000, 297000),
+
+       CORE_DVFS("pciex",  4,  -1, 1, KHZ,   1,      1,      1,     1,         1,      1,       500000, 500000),
+       CORE_DVFS("mselect", 4, -1, 1, KHZ,  1,      1,      1,      1,         1,      1,       204000, 408000),
+
+       /* Core voltages (mV):                          800,    850,    900,     950,    1000   1040    1050    1100*/
+       /* xusb clocks */
+       CORE_DVFS("xusb_falcon_src", 4, -1, 1, KHZ,       1,      1,      1,      1,    1,      1,       336000 ,  336000),
+       CORE_DVFS("xusb_host_src",   4, -1, 1, KHZ,       1,      1,      1,      1,    1,      1,       112000 ,  112000),
+       CORE_DVFS("xusb_dev_src",    4, -1, 1, KHZ,       1,      1,      1,      1,    1,      1,       112000 ,  112000),
+       CORE_DVFS("xusb_ss_src",     4, -1, 1, KHZ,       1,      1,      1,      1,    1,      1,       120000 ,  120000),
+       CORE_DVFS("xusb_fs_src",     4, -1, 1, KHZ,       1,      1,      1,      1,     1,     1,        48000 ,   48000),
+       CORE_DVFS("xusb_hs_src",     4, -1, 1, KHZ,       1,      1,      1,      1,     1,     1,        60000 ,   60000),
+
+       CORE_DVFS("hda",             4, -1, 1, KHZ,       1,      1,      1,      1,    1,      1,      108000 ,  108000),
+       CORE_DVFS("hda2codec_2x",    4, -1, 1, KHZ,       1,      1,      1,      1,     1,     1,       48000 ,   48000),
+
+       CORE_DVFS("sor0",            4, -1, 1, KHZ,       1,      1,      1,      1,    1,      1,       540000,  540000),
+       OVRRD_DVFS("sdmmc1",         4, -1, 1, KHZ,      1,      1,     1,      1,      1,      1,       136000, 136000),
+        OVRRD_DVFS("sdmmc3",         4, -1, 1, KHZ,      1,      1,    1,      1,      1,      1,      136000, 136000),
+        OVRRD_DVFS("sdmmc4",         4, -1, 1, KHZ,      1,      1,    1,      1,      1,      1,      136000, 136000),
+};
+
 /*
  * DVFS table for Automotive platforms.
  *
@@ -403,7 +688,6 @@ static struct dvfs core_dvfs_table[] = {
  *    corresponding to that voltage only.
  * 2. This table is also used to determine rate of shared PLLs (PLLCx) and SCPU.
  */
-
 static struct dvfs core_dvfs_table_automotive[] = {
        /* Core voltages (mV):                      800,    850,    900,    950,    1000,  1040,   1050,    1100,     1150 */
        /* Clock limits for internal blocks, PLLs */
@@ -496,8 +780,8 @@ static int resolve_core_override(int min_override_mv)
 
 /* GPU DVFS tables */
 static unsigned long gpu_max_freq[] = {
-/* speedo_id   0       1       2        3      4       */
-               648000, 852000, 1008000, 780000, 804000
+/* speedo_id   0       1       2        3      4       5       6*/
+               648000, 852000, 1008000, 780000, 804000, 756000, 852000
 };
 static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
        {
@@ -522,7 +806,98 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
                },
                .vts_trips_table = { -40, 34, },
        },
-
+       {
+               /* Embedded SKU CD575M Always On*/
+               .speedo_id =  4,
+               .process_id = -1,
+               .max_mv = 1090,
+               .freqs_mult = KHZ,
+               .speedo_scale = 100,
+               .thermal_scale = 10,
+               .voltage_scale = 1000,
+               .cvb_table = {
+                       /*f        dfll  pll:   c0,     c1,   c2,   c3,      c4,   c5 */
+                       {   72000, {  }, { 1209886, -36468,  515,   417, -13123,  203}, },
+                       {  108000, {  }, { 1130804, -27659,  296,   298, -10834,  221}, },
+                       {  180000, {  }, { 1162871, -27110,  247,   238, -10681,  268}, },
+                       {  252000, {  }, { 1220458, -28654,  247,   179, -10376,  298}, },
+                       {  324000, {  }, { 1280953, -30204,  247,   119,  -9766,  304}, },
+                       {  396000, {  }, { 1344547, -31777,  247,   119,  -8545,  292}, },
+                       {  468000, {  }, { 1420168, -34227,  269,    60,  -7172,  256}, },
+                       {  540000, {  }, { 1490757, -35955,  274,    60,  -5188,  197}, },
+                       {  612000, {  }, { 1599112, -42583,  398,     0,  -1831,  119}, },
+                       {  648000, {  }, { 1366986, -16459, -274,     0,  -3204,   72}, },
+                       {  684000, {  }, { 1391884, -17078, -274,   -60,  -1526,   30}, },
+                       {  708000, {  }, { 1415522, -17497, -274,   -60,   -458,    0}, },
+                       {  756000, {  }, { 1464061, -18331, -274,  -119,   1831,  -72}, },
+                       {  804000, {  }, { 1524225, -20064, -254,  -119,   4272, -155}, },
+                       {       0, {  }, { }, },
+               },
+               .cvb_vmin =  {  0, {  }, { 1180000, -18900,    0,     0,  -6110,    0}, },
+               .vmin_trips_table = { 15, },
+               .therm_floors_table = { 900, },
+               .vts_trips_table = { -10, 10, 30, 50, 70, },
+       },
+       {
+               /* Embedded SKU CD575MI Always On*/
+               .speedo_id =  5,
+               .process_id = -1,
+               .max_mv = 1070,
+               .freqs_mult = KHZ,
+               .speedo_scale = 100,
+               .thermal_scale = 10,
+               .voltage_scale = 1000,
+               .cvb_table = {
+                       /*f        dfll  pll:   c0,     c1,   c2,   c3,      c4,   c5 */
+                       {   72000, {  }, { 1209886, -36468,  515,  }, },
+                       {  108000, {  }, { 1130804, -27659,  296,  }, },
+                       {  180000, {  }, { 1162871, -27110,  247,  }, },
+                       {  252000, {  }, { 1220458, -28654,  247,  }, },
+                       {  324000, {  }, { 1280953, -30204,  247,  }, },
+                       {  396000, {  }, { 1344547, -31777,  247,  }, },
+                       {  468000, {  }, { 1420168, -34227,  269,  }, },
+                       {  540000, {  }, { 1490757, -35955,  274,  }, },
+                       {  612000, {  }, { 1599112, -42583,  398,  }, },
+                       {  648000, {  }, { 1366986, -16459, -274,  }, },
+                       {  684000, {  }, { 1391884, -17078, -274,  }, },
+                       {  708000, {  }, { 1415522, -17497, -274,  }, },
+                       {  756000, {  }, { 1494061, -18331, -274,  }, },
+                       {       0, {  }, { }, },
+               },
+               .cvb_vmin =  { 0, { } , { 950000, }, },
+               .vts_trips_table = { -40, 0,},
+       },
+       {
+               /* Embedded SKU CD575MI */
+               .speedo_id =  6,
+               .process_id = -1,
+               .max_mv = 1200,
+               .freqs_mult = KHZ,
+               .speedo_scale = 100,
+               .thermal_scale = 10,
+               .voltage_scale = 1000,
+               .cvb_table = {
+                       /*f        dfll  pll:   c0,     c1,   c2,   c3,      c4,   c5 */
+                       {   72000, {  }, { 1209886, -36468,  515,  }, },
+                       {  108000, {  }, { 1130804, -27659,  296,  }, },
+                       {  180000, {  }, { 1162871, -27110,  247,  }, },
+                       {  252000, {  }, { 1220458, -28654,  247,  }, },
+                       {  324000, {  }, { 1280953, -30204,  247,  }, },
+                       {  396000, {  }, { 1344547, -31777,  247,  }, },
+                       {  468000, {  }, { 1420168, -34227,  269,  }, },
+                       {  540000, {  }, { 1490757, -35955,  274,  }, },
+                       {  612000, {  }, { 1599112, -42583,  398,  }, },
+                       {  648000, {  }, { 1366986, -16459, -274,  }, },
+                       {  684000, {  }, { 1391884, -17078, -274,  }, },
+                       {  708000, {  }, { 1415522, -17497, -274,  }, },
+                       {  756000, {  }, { 1494061, -18331, -274,  }, },
+                       {  804000, {  }, { 1524225, -20064, -254,  }, },
+                        {  852000, {  }, { 1608418, -21643, -269,  }, },
+                       {       0, {  }, { }, },
+               },
+               .cvb_vmin =  { 0, { } , { 950000, }, },
+               .vts_trips_table = { -40, 0,},
+       },
        {
                .speedo_id =  -1,
                .process_id = -1,
@@ -825,7 +1200,8 @@ static int __init set_cpu_dvfs_data(unsigned long max_freq,
                rail, &d->dfll_tune_data);
 #endif
 
-       if (tegra_is_soc_automotive_speedo()) {
+       if (tegra_is_soc_automotive_speedo() || cpu_dvfs->speedo_id == 7 ||
+                       cpu_dvfs->speedo_id == 8) {
                rail->clk_switch_cdev = &cpu_clk_switch_cdev;
                ret = tegra_dvfs_rail_init_clk_switch_thermal_profile(
                                d->clk_switch_trips, rail);
@@ -1022,15 +1398,22 @@ static int __init set_gpu_dvfs_data(unsigned long max_freq,
                        int t = rail->vts_cdev->trip_temperatures[j];
 
                        /* get thermal offset for this trip-point */
-                       mvj += get_cvb_t_voltage(speedo, d->speedo_scale,
-                               t, d->thermal_scale, &table->cvb_pll_param);
+                       if ((d->speedo_id == 5 || d->speedo_id == 6) && (j == 0)) {
+                               mvj += 50 * d->voltage_scale;
+                               if (mvj > (d->max_mv * 1000))
+                                       mvj -= 50 * d->voltage_scale;
+                       } else
+                               mvj += get_cvb_t_voltage(speedo, d->speedo_scale,
+                                       t, d->thermal_scale, &table->cvb_pll_param);
                        mvj = round_cvb_voltage(mvj, d->voltage_scale, align);
 
                        /* clip to minimum, abort if above maximum */
                        mvj_offs = max(mvj, gpu_vmin[j] + simon_offs);
                        mvj = max(mvj, gpu_vmin[j]);
-                       if (mvj > d->max_mv)
-                               break;
+                       if ((d->speedo_id != 5) || (j != 0)) {
+                               if (mvj > d->max_mv)
+                                       break;
+                       }
 
                        /* update voltage for adjacent ranges bounded by this
                           trip-point (cvb & dvfs are transpose matrices) */
@@ -1176,6 +1559,7 @@ void __init tegra12x_init_dvfs(void)
        int core_process_id = tegra_core_process_id();
        int gpu_speedo_id = tegra_gpu_speedo_id();
        int gpu_process_id = tegra_gpu_process_id();
+       int chip_personality = tegra_get_chip_personality();
 
        int i, ret;
        int core_nominal_mv_index;
@@ -1211,8 +1595,22 @@ void __init tegra12x_init_dvfs(void)
 #ifndef CONFIG_TEGRA_CORE_DVFS
        tegra_dvfs_core_disabled = true;
 #endif
-
-
+       if (cpu_speedo_id == 7 || cpu_speedo_id == 8)
+               tegra_dvfs_cpu_disabled = true;
+       if (cpu_speedo_id == 7 || cpu_speedo_id == 8 ||
+               CONFIG_TEGRA_USE_DFLL_RANGE == TEGRA_USE_DFLL_CDEV_CNTRL)
+               tegra_override_dfll_range = TEGRA_USE_DFLL_CDEV_CNTRL;
+       if (soc_speedo_id == 3)
+               tegra_dvfs_core_disabled = true;
+       /* update core dvfs nominal voltage for CD575M always on profile */
+       if (soc_speedo_id == 0 && chip_personality == always_on) {
+               for (i = 0; i < MAX_DVFS_FREQS; i++) {
+                       if (core_millivolts[i] == 1000) {
+                               core_millivolts[i] = 1010;
+                               break;
+                       }
+               }
+       }
        /*
         * Find nominal voltages for core (1st) and cpu rails before rail
         * init. Nominal voltage index in core scaling ladder can also be
@@ -1278,10 +1676,32 @@ void __init tegra12x_init_dvfs(void)
        BUG_ON((i == ARRAY_SIZE(gpu_cvb_dvfs_table)) || ret);
 
        /* Init core thermal profile */
-       tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table,
-               vdd_core_therm_floors_table, &tegra12_dvfs_rail_vdd_core, NULL);
-       tegra_dvfs_rail_init_vmax_thermal_profile(vdd_core_vmax_trips_table,
-               vdd_core_therm_caps_table, &tegra12_dvfs_rail_vdd_core, NULL);
+       if (soc_speedo_id == 3) {
+               tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table_sku80_alwayson,
+                               vdd_core_therm_floors_table_sku80_alwayson, &tegra12_dvfs_rail_vdd_core, NULL);
+               tegra12_dvfs_rail_vdd_core.therm_mv_caps = vdd_core_therm_caps_table_sku80_alwayson;
+               tegra12_dvfs_rail_vdd_core.therm_mv_caps_num = ARRAY_SIZE(vdd_core_therm_caps_table_sku80_alwayson);
+               if (tegra12_dvfs_rail_vdd_core.vmax_cdev) {
+                       tegra12_dvfs_rail_vdd_core.vmax_cdev->trip_temperatures_num =
+                               ARRAY_SIZE(vdd_core_vmax_trips_table_sku80_alwayson);
+                       tegra12_dvfs_rail_vdd_core.vmax_cdev->trip_temperatures = vdd_core_vmax_trips_table_sku80_alwayson;
+               }
+       } else if (soc_speedo_id == 4) {
+               tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table_sku80,
+                               vdd_core_therm_floors_table_sku80, &tegra12_dvfs_rail_vdd_core, NULL);
+               tegra12_dvfs_rail_vdd_core.therm_mv_caps = vdd_core_therm_caps_table_sku80;
+               tegra12_dvfs_rail_vdd_core.therm_mv_caps_num = ARRAY_SIZE(vdd_core_therm_caps_table_sku80);
+               if (tegra12_dvfs_rail_vdd_core.vmax_cdev) {
+                       tegra12_dvfs_rail_vdd_core.vmax_cdev->trip_temperatures_num =
+                               ARRAY_SIZE(vdd_core_vmax_trips_table_sku80);
+                       tegra12_dvfs_rail_vdd_core.vmax_cdev->trip_temperatures = vdd_core_vmax_trips_table_sku80;
+               }
+       } else {
+               tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table,
+                               vdd_core_therm_floors_table, &tegra12_dvfs_rail_vdd_core, NULL);
+               tegra_dvfs_rail_init_vmax_thermal_profile(vdd_core_vmax_trips_table,
+                               vdd_core_therm_caps_table, &tegra12_dvfs_rail_vdd_core, NULL);
+       }
 
        /* Init rail structures and dependencies */
        tegra_dvfs_init_rails(tegra12_dvfs_rails,
@@ -1294,6 +1714,14 @@ void __init tegra12x_init_dvfs(void)
                        /* Use automotive core dvfs table */
                        INIT_CORE_DVFS_TABLE(core_dvfs_table_automotive,
                                     ARRAY_SIZE(core_dvfs_table_automotive));
+               } else if (soc_speedo_id == 3) {
+                       /* Use embedded core dvfs table alwayson personality */
+                       INIT_CORE_DVFS_TABLE(core_dvfs_table_embedded_alwayson,
+                                    ARRAY_SIZE(core_dvfs_table_embedded_alwayson));
+               } else if (soc_speedo_id == 4) {
+                       /* Use embedded core dvfs table */
+                       INIT_CORE_DVFS_TABLE(core_dvfs_table_embedded,
+                                    ARRAY_SIZE(core_dvfs_table_embedded));
                } else {
 
                        INIT_CORE_DVFS_TABLE(core_dvfs_table,

diff --git a/include/linux/platform/tegra/dvfs.h b/include/linux/platform/tegra/dvfs.h
index 30759b0a59cf1051ea50fddde56a1dba8575147f..6e54e7e1bd77a244b9bf8404012642c18234f61d 100644 (file)
--- a/include/linux/platform/tegra/dvfs.h
+++ b/include/linux/platform/tegra/dvfs.h
@@ -153,6 +153,8 @@ enum dfll_range {
 /* DFLL usage is under thermal cooling device control */
 #define TEGRA_USE_DFLL_CDEV_CNTRL 3
 
+extern int tegra_override_dfll_range;
+
 /* DVFS settings specific for DFLL clock source */
 struct dvfs_dfll_data {
        u32             tune0;