ARM64: tegra21: Set Vmin for PWM DFLL calibration

Selected set Vmin option for DFLL calibration on Tegra21 platforms with
PWM regulator.

Bug 1632845

Change-Id: I48f3d0157ac4f069020bed859bb2ad83e469b24d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/730006
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-power-dvfs-e2174-1101-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-power-dvfs-e2174-1101-a00.dtsi
index 772455d2df506b607bc95bda815ea2c287f8aa67..ea42e61f63a0f7f299adbbc7c8f73fb06dfaa4a1 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-power-dvfs-e2174-1101-a00.dtsi
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-power-dvfs-e2174-1101-a00.dtsi
@@ -43,6 +43,7 @@
                         <&tegra_car TEGRA210_CLK_ID_CPU_G>,
                         <&tegra_car TEGRA210_CLK_ID_I2C5>;
                clock-names = "dfll_cpu", "soc", "ref", "safe_dvfs", "i2c";
+               calibrate-force-vmin;
                board-params = <&dfll_ovr_params>;
 
                pwm_dfll: pwm-pmic-integration {