This patch sets max clk limit to 200MHz for SDMMC3 for PM375.
Requesting 208MHz results in getting 204MHz from PLL_P and CRC
errors are seen.
Bug
1505798
Change-Id: I14825335fa5895ef2dde905f1e3cd568d2dafa62
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/422034
(cherrypicked from commit
8ec9033e13c639419d351ad9d1b6ac92f3da4cb6)
Reviewed-on: http://git-master/r/424133
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
board_info.board_id == BOARD_PM359)
tegra_sdhci_platform_data0.disable_clock_gate = 1;
+ /*
+ * FIXME: Set max clk limit to 200MHz for SDMMC3 for PM375.
+ * Requesting 208MHz results in getting 204MHz from PLL_P
+ * and CRC errors are seen with same.
+ */
+ if (board_info.board_id == BOARD_PM375)
+ tegra_sdhci_platform_data2.max_clk_limit = 200000000;
+
speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
tegra_sdhci_platform_data0.cpu_speedo = speedo;
tegra_sdhci_platform_data2.cpu_speedo = speedo;