ARM: tegra11:clock:update UTMIPLL register program

Update the UTMIPLL register programming sequence
to let hardware control UTMIPLL.

Bug 1057339

Change-Id: I38cca059b3f263de8382f56a5f2a0247e0df8743
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/159449
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
Rebase-Id: R24146394216696fe34fabc4c3cbe7498af48fe97

diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c
index 580f6489a509bf4a961eba08b1a46ec25449a52a..5d90d581cf83e39b99e50a5d3b87d049654fab1b 100644 (file)
--- a/arch/arm/mach-tegra/tegra11_clocks.c
+++ b/arch/arm/mach-tegra/tegra11_clocks.c
@@ -390,6 +390,7 @@
 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP        (1 << 15)
 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN      (1 << 14)
 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN      (1 << 12)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP              (1 << 17)
 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN            (1 << 16)
 
 /* PLLE */
@@ -453,6 +454,7 @@
 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL    (1<<2)
 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL    (1<<0)
 
+#define USB_PLLS_SEQ_START_STATE               (1<<25)
 #define USB_PLLS_SEQ_ENABLE                    (1<<24)
 #define USB_PLLS_USE_LOCKDET                   (1<<6)
 #define USB_PLLS_ENABLE_SWCTL                  ((1<<2) | (1<<0))
@@ -1724,6 +1726,7 @@ static void usb_plls_hw_control_enable(u32 reg)
        u32 val = clk_readl(reg);
        val |= USB_PLLS_USE_LOCKDET;
        val &= ~USB_PLLS_ENABLE_SWCTL;
+       val |= USB_PLLS_SEQ_START_STATE;
        pll_writel_delay(val, reg);
 
        val |= USB_PLLS_SEQ_ENABLE;
@@ -1782,25 +1785,36 @@ static void tegra11_utmi_param_configure(struct clk *c)
        /* Remove power downs from UTMIP PLL control bits */
        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+       reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
-
        clk_writel(reg, UTMIP_PLL_CFG1);
 
        /* Setup HW control of UTMIPLL */
        reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
-       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
        reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
        reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
+       clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
+
+       reg = clk_readl(UTMIP_PLL_CFG1);
+       reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+       reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+       clk_writel(reg, UTMIP_PLL_CFG1);
+
+       udelay(1);
+
+       /* Setup SW override of UTMIPLL assuming USB2.0
+          ports are assigned to USB2 */
+       reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
+       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
        clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
 
        udelay(1);
 
+       /* Enable HW control UTMIPLL */
        reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
        reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
-       reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE;
-       reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL;
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
        clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
 }
 
@@ -1843,10 +1857,12 @@ static void tegra11_pll_clk_init(struct clk *c)
        }
 
        if (c->flags & PLLU) {
-               /* Configure UTMI PLL power management, and put PLLU under
-                  h/w control */
+               /* Configure UTMI PLL power management */
                tegra11_utmi_param_configure(c);
+
+               /* Put PLLU under h/w control */
                usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
+
                val = clk_readl(c->reg + PLL_BASE);
                val &= ~PLLU_BASE_OVERRIDE;
                clk_writel(val, c->reg + PLL_BASE);