]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
ARM: tegra: chip-specific power detect cells
authorBitan Biswas <bbiswas@nvidia.com>
Wed, 26 Jun 2013 04:44:29 +0000 (10:14 +0530)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:28:18 +0000 (13:28 -0700)
T14x specific power detect cells only must be used. The
implementation needs all supported power detect cells
specific to chip. If extra entries are declared for a
chip the initialization fails.

bug 1231612
bug 1236429
bug 1231668

Change-Id: Iffe8271c77f1b382972f29f20dc0a4094b270490
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/242233
(cherry picked from commit 11d6341368449513f9ba56ab868cf05ff0002300)
Reviewed-on: http://git-master/r/247140
Reviewed-by: Automatic_Commit_Validation_User
arch/arm/mach-tegra/powerdetect.c

index 05d886a6331a811b1e7a33296995ad4315df0cb4..5db49481a3c2460beee660167351a3ccffd7025f 100644 (file)
@@ -76,9 +76,13 @@ static inline u32 pmc_readl(unsigned long addr)
 /* Some IO pads does not have power detect cells, but still can/should be
  * turned off when no power - set pwrdet_mask=0 for such pads */
 static struct pwr_detect_cell pwr_detect_cells[] = {
+#ifndef CONFIG_ARCH_TEGRA_14x_SOC
        POWER_CELL("pwrdet_nand",       (0x1 <<  1), (0x1 <<  1), 0xFFFFFFFF),
+#endif
        POWER_CELL("pwrdet_uart",       (0x1 <<  2), (0x1 <<  2), 0xFFFFFFFF),
+#ifndef CONFIG_ARCH_TEGRA_14x_SOC
        POWER_CELL("pwrdet_bb",         (0x1 <<  3), (0x1 <<  3), 0xFFFFFFFF),
+#endif
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
        POWER_CELL("pwrdet_vi",                   0, (0x1 <<  4), 0xFFFFFFFF),
 #else
@@ -92,7 +96,9 @@ static struct pwr_detect_cell pwr_detect_cells[] = {
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
        POWER_CELL("pwrdet_sd",                   0, (0x1 <<  8), 0xFFFFFFFF),
 #endif
+#ifndef CONFIG_ARCH_TEGRA_14x_SOC
        POWER_CELL("pwrdet_mipi",                 0, (0x1 <<  9), 0xFFFFFFFF),
+#endif
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
        POWER_CELL("pwrdet_cam",        (0x1 << 10), (0x1 << 10), 0xFFFFFFFF),
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC