video: tegra: dsi: re-init DSI in seamless

This patch re-initializes dsi in the kernel even
in seamless mode. This helps reduce the dependency
with bootloader set dsi configuration

Bug 200006804
Bug 1510417

Change-Id: I2f9ae5efd467b95b5d3b0f6568c2379f4f68522e
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/418332
(cherry picked from commit 4e9583d8ceeabb393d355a53641b12c03d8be0e2)
Reviewed-on: http://git-master/r/419278
Reviewed-by: Robert Shih <rshih@nvidia.com>
Tested-by: Robert Shih <rshih@nvidia.com>
Reviewed-by: Eric Chuang <echuang@nvidia.com>

diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 5408e002d017316df53e0f9bdebcdccfdbfac966..32331b955fd1ec7459b5b70c23c5ca752e70e046 100644 (file)
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -1972,15 +1972,24 @@ static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
                                                u8 driven_mode)
 {
-       u32 dsi_control;
-       u32 host_dsi_control;
-       u32 max_threshold;
-       u32 dcs_cmd;
-
-       dsi_control = dsi->dsi_control_val;
-       host_dsi_control = HOST_DSI_CTRL_COMMON;
-       max_threshold = 0;
-       dcs_cmd = 0;
+       u32 dsi_control = dsi->dsi_control_val;
+       u32 host_dsi_control = HOST_DSI_CTRL_COMMON;
+       u32 max_threshold = 0;
+       u32 dcs_cmd = 0;
+
+       if (dsi->dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
+               if (dsi->info.video_clock_mode ==
+                               TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
+                       dsi_control |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
+                       dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
+               } else {
+                       dsi_control |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
+                       dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
+               }
+               host_dsi_control |=
+                       DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
+               dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
+       }
 
        if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
                dsi_control |= DSI_CTRL_HOST_DRIVEN;
@@ -3803,6 +3812,24 @@ static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
        }
 }
 
+static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
+{
+       int err = 0;
+
+       if (dsi->avdd_dsi_csi)
+               err = regulator_enable(dsi->avdd_dsi_csi);
+       dev_warn(&dsi->dc->ndev->dev,
+               "unable to enable regulator err = %d", err);
+
+       dsi->status.init = DSI_MODULE_INIT;
+
+       tegra_dsi_clk_enable(dsi);
+       tegra_dsi_set_to_hs_mode(dsi->dc, dsi, TEGRA_DSI_DRIVEN_BY_DC);
+
+       dsi->host_suspended = false;
+       dsi->enabled = true;
+}
+
 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
 {
        struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
@@ -3811,6 +3838,11 @@ static void tegra_dc_dsi_enable(struct tegra_dc *dc)
        mutex_lock(&dsi->lock);
        tegra_dc_io_start(dc);
 
+       if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
+               tegra_dsi_setup_initialized_panel(dsi);
+               goto fail;
+       }
+
        /* Stop DC stream before configuring DSI registers
         * to avoid visible glitches on panel during transition
         * from bootloader to kernel driver
@@ -3908,6 +3940,9 @@ static void tegra_dc_dsi_postpoweron(struct tegra_dc *dc)
        struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
        int err = 0;
 
+       if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
+               return;
+
        mutex_lock(&dsi->lock);
        tegra_dc_io_start(dc);