ARM: tegra11: clock: Put UTMIPLL under h/w control

Programming UTMIPLL register to let hardware to
control UTMIPLL.

Bug 1057339

Reviewed-on: http://git-master/r/141559
(cherry picked from commit 6ff04c9acbb229e22410f7d70e4e127dc6768a34)

Change-Id: Ied7b0e2a34148f70fc982ee5f66c30128fb43df0
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/146346
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Rebase-Id: Ra3e095625cd44c445da3265d4badef712fd10fbc

diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c
index 7dd6ad7e01878d20c5aa36c9202dcac4af26b774..28b2f69b408b2940a5d97cc3ac582777dc30a500 100644 (file)
--- a/arch/arm/mach-tegra/tegra11_clocks.c
+++ b/arch/arm/mach-tegra/tegra11_clocks.c
@@ -387,6 +387,7 @@
 #define UTMIP_PLL_CFG1                                 0x484
 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x)             (((x) & 0x1f) << 27)
 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP        (1 << 15)
 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN      (1 << 14)
 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN      (1 << 12)
 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN            (1 << 16)
@@ -437,9 +438,13 @@
 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL     (1<<0)
 
 #define UTMIPLL_HW_PWRDN_CFG0                  0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE  (1<<25)
 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE       (1<<24)
 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET      (1<<6)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE    (1<<5)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL     (1<<4)
 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE    (1<<1)
 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL       (1<<0)
 
 #define PLLU_HW_PWRDN_CFG0                     0x530
@@ -1775,6 +1780,23 @@ static void tegra11_utmi_param_configure(struct clk *c)
        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
 
        clk_writel(reg, UTMIP_PLL_CFG1);
+
+       /* Setup HW control of UTMIPLL */
+       reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
+       reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+       clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
+
+       udelay(1);
+
+       reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+       reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL;
+       reg &= ~UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
+       clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
 }
 
 static void tegra11_pll_clk_init(struct clk *c)