arm64: tegra: jetson-cv: use pll_c4_out1 as the clock source

Need to use pll_c4_out1 for HS533 mode. pll_c4_out2 is only
capable for HS400 mode. Remove the wrongly override in jetson-cv
top dts since it's already configured correctly in sub dtsi.

Bug 200116501

Change-Id: I514698bfd8f57c68c7d0958f65cff351a6beaff9
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/764062
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

diff --git a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index dc4d393101e1fbadc1a8383610b90e6377ff4ff3..b4af5d23e712597fe0bd4c549267e3514c28b213 100644 (file)
--- a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -75,7 +75,6 @@
        sdhci@700b0600 { /* SDMMC4 for EMMC */
                uhs-mask = <0x0>;
                built-in;
-               pll_source = "pll_p", "pll_c4_out2";
                power-off-rail;
                status = "okay";
        };