.cfg_param = &laguna_cl_dvfs_param,
};
+static const struct of_device_id dfll_of_match[] = {
+ { .compatible = "nvidia,tegra124-dfll", },
+ { .compatible = "nvidia,tegra132-dfll", },
+ { },
+};
+
static int __init laguna_cl_dvfs_init(void)
{
+ struct device_node *dn = of_find_matching_node(NULL, dfll_of_match);
+
+ /*
+ * Laguna platforms maybe used with different DT variants. Some of them
+ * include DFLL data in DT, some - not. Check DT here, and continue with
+ * platform device registration only if DT DFLL node is not present.
+ */
+ if (dn) {
+ bool available = of_device_is_available(dn);
+ of_node_put(dn);
+ if (available)
+ return 0;
+ }
+
fill_reg_map();
laguna_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
status = "okay";
};
- xusb@70090000 {
+ xusb@70090000 {
/* nvidia,uses_external_pmic; */
nvidia,gpio_controls_muxed_ss_lanes;
nvidia,gpio_ss1_sata = <&tca6416 9 0>;
"slow-charger", "apple-500ma", "apple-1a",
"apple-2a", "y-cable";
};
+
+ dfll@70040084 {
+ board-params = <&{/cpu_dfll_board_params}>;
+ i2c-pmic-integration = <&{/cpu_dfll_pmic_integration}>;
+ monitor-data-new-workaround;
+ status = "okay";
+ };
+
+ cpu_dfll_board_params {
+ sample-rate = <12500>;
+ fixed-output-forcing;
+ cf = <10>;
+ ci = <0>;
+ cg = <2>;
+ droop-cut-value = <0xf>;
+ droop-restore-ramp = <0x0>;
+ scale-out-ramp = <0x0>;
+ };
+
+ cpu_dfll_pmic_integration {
+ pmic-i2c-address = <0x80>;
+ pmic-i2c-voltage-register = <0x00>;
+ i2c-fs-rate = <400000>;
+ sel-conversion-slope = <1>;
+ };
};