ARM: tegra: dvfs: Calibrate DFLL tuning threshold

ARM: tegra: dvfs: Calibrate DFLL tuning threshold

Currently switch from low to high voltage tuning ranges is based on
fixed characterized V/F curve: high range tuning settings are used if
predicted voltage for DFLL target rate is above high range floor plus
fixed margin. If margin is too low this result in CL-DVFS saturation
at floor voltage with actual frequency above the target. If margin is
too high the low tuning range is over-extended with DFLL running at
unnecessary high voltages.

Tuning range selection algorithm introduced by this commit: high range
tuning settings are selected if predicted voltage for DFLL target rate
is above high range floor level (no margin). Actual DFLL rate at high
range floor is calibrated using existing DVCO minimum rate calibration
procedure. Fixed margin is used only for initial approximation of floor
rate before calibration starts.

All target rates between fixed estimated floor and calibrated high
range minimum rate are achieved using output skipper at floor voltage.
Thus, necessary accuracy of output rate is assured with high range
tuning settings and low output voltage.

Bug 1492902

Change-Id: I7ac27f62423e67a3f09213033c32aaad7871da2b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/393224
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>