drivers/usb/host/xhci-tegra.c

   1 /*
   2  * xhci-tegra.c - Nvidia xHCI host controller driver
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/clk.h>
  24 #include <linux/ioport.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/irq.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/platform_data/tegra_usb.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/kthread.h>
  34 #include <linux/gpio.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-powergate.h>
  38 #include <linux/firmware.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_gpio.h>
  43
  44 #include <mach/tegra_usb_pad_ctrl.h>
  45 #include <mach/tegra_usb_pmc.h>
  46 #include <mach/pm_domains.h>
  47 #include <mach/mc.h>
  48 #include <mach/xusb.h>
  49
  50 #include "xhci-tegra.h"
  51 #include "xhci.h"
  52 #include "../../../arch/arm/mach-tegra/fuse.h"
  53
  54 /* macros */
  55 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
  56 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
  57 #define FW_IOCTL_DATA_SHIFT             (0)
  58 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
  59 #define FW_IOCTL_TYPE_SHIFT             (24)
  60 #define FW_IOCTL_TYPE_MASK              (0xff000000)
  61 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
  62 #define FW_LOG_COUNT                    (4096)
  63 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
  64 #define FW_LOG_PAYLOAD_SIZE             (27)
  65 #define DRIVER                          (0x01)
  66 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
  67 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
  68
  69 /* tegra_xhci_firmware_log.flags bits */
  70 #define FW_LOG_CONTEXT_VALID            (0)
  71 #define FW_LOG_FILE_OPENED              (1)
  72
  73 #define PAGE_SELECT_MASK                        0xFFFFFE00
  74 #define PAGE_SELECT_SHIFT                       9
  75 #define PAGE_OFFSET_MASK                        0x000001FF
  76 #define CSB_PAGE_SELECT(_addr)                                          \
  77         ({                                                              \
  78                 typecheck(u32, _addr);                                  \
  79                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
  80         })
  81 #define CSB_PAGE_OFFSET(_addr)                                          \
  82         ({                                                              \
  83                 typecheck(u32, _addr);                                  \
  84                 (_addr & PAGE_OFFSET_MASK);                             \
  85         })
  86
  87 #define reg_dump(_dev, _base, _reg)                                     \
  88         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
  89                 _reg, readl(_base + _reg))
  90
  91 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
  92
  93 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
  94 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
  95 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
  96
  97 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
  98
  99 /* private data types */
 100 /* command requests from the firmware */
 101 enum MBOX_CMD_TYPE {
 102         MBOX_CMD_MSG_ENABLED = 1,
 103         MBOX_CMD_INC_FALC_CLOCK,
 104         MBOX_CMD_DEC_FALC_CLOCK,
 105         MBOX_CMD_INC_SSPI_CLOCK,
 106         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
 107         MBOX_CMD_SET_BW,
 108         MBOX_CMD_SET_SS_PWR_GATING,
 109         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
 110         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 111         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 112         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
 113         MBOX_CMD_STAR_HSIC_IDLE,
 114         MBOX_CMD_STOP_HSIC_IDLE,
 115         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 116         MBOX_CMD_HSIC_PRETEND_CONNECT,
 117
 118         /* needs to be the last cmd */
 119         MBOX_CMD_MAX,
 120
 121         /* resp msg to ack above commands */
 122         MBOX_CMD_ACK = 128,
 123         MBOX_CMD_NACK
 124 };
 125
 126 struct log_entry {
 127         u32 sequence_no;
 128         u8 data[FW_LOG_PAYLOAD_SIZE];
 129         u8 owner;
 130 };
 131
 132 /* Usb3 Firmware Cfg Table */
 133 struct cfgtbl {
 134         u32 boot_loadaddr_in_imem;
 135         u32 boot_codedfi_offset;
 136         u32 boot_codetag;
 137         u32 boot_codesize;
 138
 139         /* Physical memory reserved by Bootloader/BIOS */
 140         u32 phys_memaddr;
 141         u16 reqphys_memsize;
 142         u16 alloc_phys_memsize;
 143
 144         /* .rodata section */
 145         u32 rodata_img_offset;
 146         u32 rodata_section_start;
 147         u32 rodata_section_end;
 148         u32 main_fnaddr;
 149
 150         u32 fwimg_cksum;
 151         u32 fwimg_created_time;
 152
 153         /* Fields that get filled by linker during linking phase
 154          * or initialized in the FW code.
 155          */
 156         u32 imem_resident_start;
 157         u32 imem_resident_end;
 158         u32 idirect_start;
 159         u32 idirect_end;
 160         u32 l2_imem_start;
 161         u32 l2_imem_end;
 162         u32 version_id;
 163         u8 init_ddirect;
 164         u8 reserved[3];
 165         u32 phys_addr_log_buffer;
 166         u32 total_log_entries;
 167         u32 dequeue_ptr;
 168
 169         /*      Below two dummy variables are used to replace
 170          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
 171          *      retain the size of struct _CFG_TBL used by other AP/Module.
 172          */
 173         u32 dummy_var1;
 174         u32 dummy_var2;
 175
 176         /* fwimg_len */
 177         u32 fwimg_len;
 178         u8 magic[8];
 179         u32 SS_low_power_entry_timeout;
 180         u8 num_hsic_port;
 181         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
 182 };
 183
 184 struct xusb_save_regs {
 185         u32 msi_bar_sz;
 186         u32 msi_axi_barst;
 187         u32 msi_fpci_barst;
 188         u32 msi_vec0;
 189         u32 msi_en_vec0;
 190         u32 fpci_error_masks;
 191         u32 intr_mask;
 192         u32 ipfs_intr_enable;
 193         u32 ufpci_config;
 194         u32 clkgate_hysteresis;
 195         u32 xusb_host_mccif_fifo_cntrl;
 196
 197         /* PG does not mention below */
 198         u32 hs_pls;
 199         u32 fs_pls;
 200         u32 hs_fs_speed;
 201         u32 hs_fs_pp;
 202         u32 cfg_aru;
 203         u32 cfg_order;
 204         u32 cfg_fladj;
 205         u32 cfg_sid;
 206         /* DFE and CTLE */
 207         u32 tap1_val[XUSB_SS_PORT_COUNT];
 208         u32 amp_val[XUSB_SS_PORT_COUNT];
 209         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
 210         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
 211 };
 212
 213 struct tegra_xhci_firmware {
 214         void *data; /* kernel virtual address */
 215         size_t size; /* firmware size */
 216         dma_addr_t dma; /* dma address for controller */
 217 };
 218
 219 struct tegra_xhci_firmware_log {
 220         dma_addr_t phys_addr;           /* dma-able address */
 221         void *virt_addr;                /* kernel va of the shared log buffer */
 222         struct log_entry *dequeue;      /* current dequeue pointer (va) */
 223         struct circ_buf circ;           /* big circular buffer */
 224         u32 seq;                        /* log sequence number */
 225
 226         struct task_struct *thread;     /* a thread to consume log */
 227         struct mutex mutex;
 228         wait_queue_head_t read_wait;
 229         wait_queue_head_t write_wait;
 230         wait_queue_head_t intr_wait;
 231         struct dentry *path;
 232         struct dentry *log_file;
 233         unsigned long flags;
 234 };
 235
 236 /* structure to hold the offsets of padctl registers */
 237 struct tegra_xusb_padctl_regs {
 238         u16 boot_media_0;
 239         u16 usb2_pad_mux_0;
 240         u16 usb2_port_cap_0;
 241         u16 snps_oc_map_0;
 242         u16 usb2_oc_map_0;
 243         u16 ss_port_map_0;
 244         u16 oc_det_0;
 245         u16 elpg_program_0;
 246         u16 usb2_bchrg_otgpad0_ctl0_0;
 247         u16 usb2_bchrg_otgpad0_ctl1_0;
 248         u16 usb2_bchrg_otgpad1_ctl0_0;
 249         u16 usb2_bchrg_otgpad1_ctl1_0;
 250         u16 usb2_bchrg_otgpad2_ctl0_0;
 251         u16 usb2_bchrg_otgpad2_ctl1_0;
 252         u16 usb2_bchrg_bias_pad_0;
 253         u16 usb2_bchrg_tdcd_dbnc_timer_0;
 254         u16 iophy_pll_p0_ctl1_0;
 255         u16 iophy_pll_p0_ctl2_0;
 256         u16 iophy_pll_p0_ctl3_0;
 257         u16 iophy_pll_p0_ctl4_0;
 258         u16 iophy_usb3_pad0_ctl1_0;
 259         u16 iophy_usb3_pad1_ctl1_0;
 260         u16 iophy_usb3_pad0_ctl2_0;
 261         u16 iophy_usb3_pad1_ctl2_0;
 262         u16 iophy_usb3_pad0_ctl3_0;
 263         u16 iophy_usb3_pad1_ctl3_0;
 264         u16 iophy_usb3_pad0_ctl4_0;
 265         u16 iophy_usb3_pad1_ctl4_0;
 266         u16 iophy_misc_pad_p0_ctl1_0;
 267         u16 iophy_misc_pad_p1_ctl1_0;
 268         u16 iophy_misc_pad_p0_ctl2_0;
 269         u16 iophy_misc_pad_p1_ctl2_0;
 270         u16 iophy_misc_pad_p0_ctl3_0;
 271         u16 iophy_misc_pad_p1_ctl3_0;
 272         u16 iophy_misc_pad_p0_ctl4_0;
 273         u16 iophy_misc_pad_p1_ctl4_0;
 274         u16 iophy_misc_pad_p0_ctl5_0;
 275         u16 iophy_misc_pad_p1_ctl5_0;
 276         u16 iophy_misc_pad_p0_ctl6_0;
 277         u16 iophy_misc_pad_p1_ctl6_0;
 278         u16 usb2_otg_pad0_ctl0_0;
 279         u16 usb2_otg_pad1_ctl0_0;
 280         u16 usb2_otg_pad2_ctl0_0;
 281         u16 usb2_otg_pad0_ctl1_0;
 282         u16 usb2_otg_pad1_ctl1_0;
 283         u16 usb2_otg_pad2_ctl1_0;
 284         u16 usb2_bias_pad_ctl0_0;
 285         u16 usb2_bias_pad_ctl1_0;
 286         u16 usb2_hsic_pad0_ctl0_0;
 287         u16 usb2_hsic_pad1_ctl0_0;
 288         u16 usb2_hsic_pad0_ctl1_0;
 289         u16 usb2_hsic_pad1_ctl1_0;
 290         u16 usb2_hsic_pad0_ctl2_0;
 291         u16 usb2_hsic_pad1_ctl2_0;
 292         u16 ulpi_link_trim_ctl0;
 293         u16 ulpi_null_clk_trim_ctl0;
 294         u16 hsic_strb_trim_ctl0;
 295         u16 wake_ctl0;
 296         u16 pm_spare0;
 297         u16 iophy_misc_pad_p2_ctl1_0;
 298         u16 iophy_misc_pad_p3_ctl1_0;
 299         u16 iophy_misc_pad_p4_ctl1_0;
 300         u16 iophy_misc_pad_p2_ctl2_0;
 301         u16 iophy_misc_pad_p3_ctl2_0;
 302         u16 iophy_misc_pad_p4_ctl2_0;
 303         u16 iophy_misc_pad_p2_ctl3_0;
 304         u16 iophy_misc_pad_p3_ctl3_0;
 305         u16 iophy_misc_pad_p4_ctl3_0;
 306         u16 iophy_misc_pad_p2_ctl4_0;
 307         u16 iophy_misc_pad_p3_ctl4_0;
 308         u16 iophy_misc_pad_p4_ctl4_0;
 309         u16 iophy_misc_pad_p2_ctl5_0;
 310         u16 iophy_misc_pad_p3_ctl5_0;
 311         u16 iophy_misc_pad_p4_ctl5_0;
 312         u16 iophy_misc_pad_p2_ctl6_0;
 313         u16 iophy_misc_pad_p3_ctl6_0;
 314         u16 iophy_misc_pad_p4_ctl6_0;
 315         u16 usb3_pad_mux_0;
 316         u16 iophy_pll_s0_ctl1_0;
 317         u16 iophy_pll_s0_ctl2_0;
 318         u16 iophy_pll_s0_ctl3_0;
 319         u16 iophy_pll_s0_ctl4_0;
 320         u16 iophy_misc_pad_s0_ctl1_0;
 321         u16 iophy_misc_pad_s0_ctl2_0;
 322         u16 iophy_misc_pad_s0_ctl3_0;
 323         u16 iophy_misc_pad_s0_ctl4_0;
 324         u16 iophy_misc_pad_s0_ctl5_0;
 325         u16 iophy_misc_pad_s0_ctl6_0;
 326 };
 327
 328 struct tegra_xhci_hcd {
 329         struct platform_device *pdev;
 330         struct xhci_hcd *xhci;
 331         u16 device_id;
 332
 333         spinlock_t lock;
 334         struct mutex sync_lock;
 335
 336         int smi_irq;
 337         int padctl_irq;
 338         int usb3_irq;
 339         int usb2_irq;
 340
 341         bool ss_wake_event;
 342         bool ss_pwr_gated;
 343         bool host_pwr_gated;
 344         bool hs_wake_event;
 345         bool host_resume_req;
 346         bool lp0_exit;
 347         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
 348         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
 349         unsigned long last_jiffies;
 350         unsigned long host_phy_base;
 351         unsigned long host_phy_size;
 352         void __iomem *host_phy_virt_base;
 353
 354         void __iomem *padctl_base;
 355         void __iomem *fpci_base;
 356         void __iomem *ipfs_base;
 357
 358         struct tegra_xusb_platform_data *pdata;
 359         struct tegra_xusb_board_data *bdata;
 360         struct tegra_xusb_chip_calib *cdata;
 361         struct tegra_xusb_padctl_regs *padregs;
 362         const struct tegra_xusb_soc_config *soc_config;
 363         u64 tegra_xusb_dmamask;
 364
 365         /* mailbox variables */
 366         struct mutex mbox_lock;
 367         u32 mbox_owner;
 368         u32 cmd_type;
 369         u32 cmd_data;
 370
 371         struct regulator *xusb_utmi_vbus_regs[XUSB_UTMI_COUNT];
 372
 373         struct regulator *xusb_s1p05v_reg;
 374         struct regulator *xusb_s3p3v_reg;
 375         struct regulator *xusb_s1p8v_reg;
 376         struct regulator *vddio_hsic_reg;
 377         int vddio_hsic_refcnt;
 378
 379         struct work_struct mbox_work;
 380         struct work_struct ss_elpg_exit_work;
 381         struct work_struct host_elpg_exit_work;
 382
 383         struct clk *host_clk;
 384         struct clk *ss_clk;
 385
 386         /* XUSB Falcon SuperSpeed Clock */
 387         struct clk *falc_clk;
 388
 389         /* EMC Clock */
 390         struct clk *emc_clk;
 391         /* XUSB SS PI Clock */
 392         struct clk *ss_src_clk;
 393         /* PLLE Clock */
 394         struct clk *plle_clk;
 395         struct clk *pll_u_480M;
 396         struct clk *clk_m;
 397         /* refPLLE clk */
 398         struct clk *pll_re_vco_clk;
 399         /*
 400          * XUSB/IPFS specific registers these need to be saved/restored in
 401          * addition to spec defined registers
 402          */
 403         struct xusb_save_regs sregs;
 404         bool usb2_rh_suspend;
 405         bool usb3_rh_suspend;
 406         bool hc_in_elpg;
 407
 408         /* otg transceiver */
 409         struct usb_phy *transceiver;
 410         struct notifier_block otgnb;
 411
 412         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
 413         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
 414         /* firmware loading related */
 415         struct tegra_xhci_firmware firmware;
 416
 417         struct tegra_xhci_firmware_log log;
 418
 419         bool init_done;
 420 };
 421
 422 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
 423 static int tegra_xhci_remove(struct platform_device *pdev);
 424 static void init_filesystem_firmware_done(const struct firmware *fw,
 425                                         void *context);
 426
 427 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
 428 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
 429 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
 430         u8 port)  __attribute__ ((unused));
 431
 432 #ifdef CONFIG_TEGRA_XUSB_USB_BOOTLOADER_FIRMWARE
 433 static bool use_bootloader_firmware = true;
 434 #else
 435 static bool use_bootloader_firmware;
 436 #endif
 437 module_param(use_bootloader_firmware, bool, S_IRUGO);
 438 MODULE_PARM_DESC(use_bootloader_firmware, "take bootloader initialized firmware");
 439
 440 #define FIRMWARE_FILE CONFIG_TEGRA_XUSB_FIRMWARE_FILE
 441 static char *firmware_file = FIRMWARE_FILE;
 442 #define FIRMWARE_FILE_HELP      \
 443         "used to specify firmware file of Tegra XHCI host controller. "\
 444         "This takes effect only if \"use_bootloader_firmware\" is \"N\". " \
 445         "Default value is \"" FIRMWARE_FILE "\"."
 446
 447 module_param(firmware_file, charp, S_IRUGO);
 448 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
 449
 450 /* functions */
 451 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
 452 {
 453         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
 454 }
 455
 456 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
 457 {
 458 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
 459         WARN_ON(tegra->sync_lock.owner != current);
 460 #endif
 461 }
 462
 463 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
 464         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
 465             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
 466             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
 467
 468 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
 469                                                 int start, int last)
 470 {
 471         unsigned long portmap = tegra->bdata->portmap;
 472         return find_next_bit(&portmap, last , start);
 473 }
 474
 475 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
 476                                                 int curr_pad)
 477 {
 478         int start = XUSB_HSIC_INDEX + curr_pad;
 479         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
 480
 481         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
 482                 return -1;
 483
 484         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
 485 }
 486
 487 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
 488 {
 489         int err = 0;
 490
 491         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
 492                 return;
 493
 494         if (tegra->bdata->lane_owner & BIT(0)) {
 495                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
 496                  * GPIO P11 to '0'
 497                  */
 498                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
 499                         "gpio_ss1_sata");
 500                 if (err < 0)
 501                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
 502                                 __func__, err);
 503                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
 504                         & 0xffff), 1);
 505                 if (err < 0)
 506                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
 507                                 __func__, err);
 508                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
 509                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
 510         }
 511 }
 512
 513 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
 514 {
 515         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
 516         __le32 __iomem *addr;
 517
 518         if (port >= num_ports) {
 519                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
 520                 return -1;
 521         }
 522
 523         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
 524         return xhci_readl(xhci, addr);
 525 }
 526
 527 static void debug_print_portsc(struct xhci_hcd *xhci)
 528 {
 529         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
 530         u32 reg;
 531         int i;
 532         int ports;
 533
 534         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 535         for (i = 0; i < ports; i++) {
 536                 reg = xhci_read_portsc(xhci, i);
 537                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
 538                                 addr, i, (unsigned int) reg);
 539                 addr += NUM_PORT_REGS;
 540         }
 541 }
 542 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
 543
 544 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
 545 {
 546         if (!tegra->transceiver)
 547                 return true;
 548         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
 549                 return true;
 550         else
 551                 return false;
 552 }
 553
 554 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
 555 {
 556         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
 557         u32 portsc;
 558
 559         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
 560         if (DEV_FULLSPEED(portsc))
 561                 return USB_PMC_PORT_SPEED_FULL;
 562         else if (DEV_HIGHSPEED(portsc))
 563                 return USB_PMC_PORT_SPEED_HIGH;
 564         else if (DEV_LOWSPEED(portsc))
 565                 return USB_PMC_PORT_SPEED_LOW;
 566         else if (DEV_SUPERSPEED(portsc))
 567                 return USB_PMC_PORT_SPEED_SUPER;
 568         else
 569                 return USB_PMC_PORT_SPEED_UNKNOWN;
 570 }
 571
 572 static void pmc_init(struct tegra_xhci_hcd *tegra)
 573 {
 574         struct tegra_usb_pmc_data *pmc;
 575         struct device *dev = &tegra->pdev->dev;
 576         int pad;
 577
 578         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 579                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 580                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 581                         pmc = &pmc_data[pad];
 582                         if (tegra->soc_config->pmc_portmap)
 583                                 pmc->instance = PMC_PORTMAP_MASK(
 584                                                 tegra->soc_config->pmc_portmap,
 585                                                 pad);
 586                         else
 587                                 pmc->instance = pad;
 588                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
 589                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
 590                         pmc->controller_type = TEGRA_USB_3_0;
 591                         tegra_usb_pmc_init(pmc);
 592                 }
 593         }
 594
 595         for_each_enabled_hsic_pad(pad, tegra) {
 596                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 597                 pmc = &pmc_hsic_data[pad];
 598                 pmc->instance = pad + 1;
 599                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
 600                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
 601                 pmc->controller_type = TEGRA_USB_3_0;
 602                 tegra_usb_pmc_init(pmc);
 603         }
 604 }
 605
 606 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
 607 {
 608         struct tegra_usb_pmc_data *pmc;
 609         struct device *dev = &tegra->pdev->dev;
 610         u32 portsc;
 611         int port;
 612         int pad;
 613
 614         for_each_enabled_hsic_pad(pad, tegra) {
 615                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 616
 617                 pmc = &pmc_hsic_data[pad];
 618                 port = hsic_pad_to_port(pad);
 619                 portsc = xhci_read_portsc(tegra->xhci, port);
 620                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
 621                         __func__, pad, portsc);
 622
 623                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
 624                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 625         }
 626
 627         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 628                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 629                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 630                         pmc = &pmc_data[pad];
 631                         pmc->port_speed = update_speed(tegra, pad);
 632                         if (pad == 0) {
 633                                 if (is_otg_host(tegra))
 634                                         pmc->pmc_ops->setup_pmc_wake_detect(
 635                                                                         pmc);
 636                         } else
 637                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 638                 }
 639         }
 640 }
 641
 642 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
 643 {
 644         struct tegra_usb_pmc_data *pmc;
 645         struct device *dev = &tegra->pdev->dev;
 646         int pad;
 647
 648         for_each_enabled_hsic_pad(pad, tegra) {
 649                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 650
 651                 pmc = &pmc_hsic_data[pad];
 652                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 653         }
 654
 655         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 656                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 657                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 658                         pmc = &pmc_data[pad];
 659                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 660                 }
 661         }
 662 }
 663
 664 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
 665 {
 666         void __iomem *fpci_base = tegra->fpci_base;
 667         struct platform_device *pdev = tegra->pdev;
 668         u32 input_addr;
 669         u32 data;
 670         u32 csb_page_select;
 671
 672         /* to select the appropriate CSB page to write to */
 673         csb_page_select = CSB_PAGE_SELECT(addr);
 674
 675         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
 676                         csb_page_select);
 677
 678         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 679
 680         /* selects the appropriate offset in the page to read from */
 681         input_addr = CSB_PAGE_OFFSET(addr);
 682         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 683
 684         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
 685                         input_addr, data);
 686         return data;
 687 }
 688
 689 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
 690 {
 691         void __iomem *fpci_base = tegra->fpci_base;
 692         struct platform_device *pdev = tegra->pdev;
 693         u32 input_addr;
 694         u32 csb_page_select;
 695
 696         /* to select the appropriate CSB page to write to */
 697         csb_page_select = CSB_PAGE_SELECT(addr);
 698
 699         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
 700                         csb_page_select);
 701
 702         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 703
 704         /* selects the appropriate offset in the page to write to */
 705         input_addr = CSB_PAGE_OFFSET(addr);
 706         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 707
 708         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
 709                         input_addr, data);
 710 }
 711
 712 static int fw_message_send(struct tegra_xhci_hcd *tegra,
 713         enum MBOX_CMD_TYPE type, u32 data)
 714 {
 715         struct device *dev = &tegra->pdev->dev;
 716         void __iomem *base = tegra->fpci_base;
 717         unsigned long target;
 718         u32 reg;
 719
 720         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
 721
 722         mutex_lock(&tegra->mbox_lock);
 723
 724         target = jiffies + msecs_to_jiffies(20);
 725         /* wait mailbox to become idle, timeout in 20ms */
 726         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
 727                 time_is_after_jiffies(target)) {
 728                 mutex_unlock(&tegra->mbox_lock);
 729                 usleep_range(100, 200);
 730                 mutex_lock(&tegra->mbox_lock);
 731         }
 732
 733         if (reg != 0) {
 734                 dev_err(dev, "%s mailbox is still busy\n", __func__);
 735                 goto timeout;
 736         }
 737
 738         target = jiffies + msecs_to_jiffies(10);
 739         /* acquire mailbox , timeout in 10ms */
 740         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 741         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
 742                 && time_is_after_jiffies(target)) {
 743                 mutex_unlock(&tegra->mbox_lock);
 744                 usleep_range(100, 200);
 745                 mutex_lock(&tegra->mbox_lock);
 746                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 747         }
 748
 749         if (reg != MBOX_OWNER_SW) {
 750                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
 751                 goto timeout;
 752         }
 753
 754         reg = CMD_TYPE(type) | CMD_DATA(data);
 755         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
 756
 757         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 758         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
 759         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 760
 761         mutex_unlock(&tegra->mbox_lock);
 762         return 0;
 763
 764 timeout:
 765         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
 766         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
 767         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
 768         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
 769         mutex_unlock(&tegra->mbox_lock);
 770         return -ETIMEDOUT;
 771 }
 772
 773 /**
 774  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
 775  *      This function takes care of wrapping. That means when current log entry
 776  *      is the last one, it returns with the first one.
 777  *
 778  * @param log   The tegra_xhci_firmware_log context.
 779  * @param this  The current log entry.
 780  * @return      The log entry which is next to the current one.
 781  */
 782 static inline struct log_entry *fw_log_next(
 783                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
 784 {
 785         struct log_entry *first = (struct log_entry *) log->virt_addr;
 786         struct log_entry *last = first + FW_LOG_COUNT - 1;
 787
 788         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
 789
 790         return (this == last) ? first : (this + 1);
 791 }
 792
 793 /**
 794  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
 795  *      tegra_xhci_firmware_log.dequeue.
 796  *
 797  * @param log   The tegra_xhci_firmware_log context.
 798  * @param n     Counts of log entries to fast-forward.
 799  */
 800 static inline void fw_log_update_deq_pointer(
 801                 struct tegra_xhci_firmware_log *log, int n)
 802 {
 803         struct tegra_xhci_hcd *tegra =
 804                         container_of(log, struct tegra_xhci_hcd, log);
 805         struct device *dev = &tegra->pdev->dev;
 806         struct log_entry *deq = tegra->log.dequeue;
 807         dma_addr_t physical_addr;
 808         u32 reg;
 809
 810         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
 811         while (n-- > 0)
 812                 deq = fw_log_next(log, deq);
 813
 814         tegra->log.dequeue = deq;
 815         physical_addr = tegra->log.phys_addr +
 816                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
 817
 818         /* update dequeue pointer to firmware */
 819         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
 820         reg |= (physical_addr & 0xffff); /* lower 16-bits */
 821         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 822
 823         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
 824         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
 825         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 826
 827         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, (u32)physical_addr);
 828 }
 829
 830 static inline bool circ_buffer_full(struct circ_buf *circ)
 831 {
 832         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
 833
 834         return (space <= FW_LOG_SIZE);
 835 }
 836
 837 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
 838 {
 839         return (tegra->log.dequeue->owner == DRIVER);
 840 }
 841
 842 /**
 843  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
 844  *      log buffer.
 845  * @param tegra:        tegra_xhci_hcd context
 846  * @param msec:         timeout value in millisecond
 847  * @return true:        shared log buffer is empty,
 848  *         false:       shared log buffer isn't empty.
 849  */
 850 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
 851                 unsigned timeout)
 852 {
 853         unsigned long target = jiffies + msecs_to_jiffies(timeout);
 854         bool ret;
 855
 856         mutex_lock(&tegra->log.mutex);
 857
 858         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
 859                 mutex_unlock(&tegra->log.mutex);
 860                 usleep_range(1000, 2000);
 861                 mutex_lock(&tegra->log.mutex);
 862         }
 863
 864         ret = fw_log_available(tegra);
 865         mutex_unlock(&tegra->log.mutex);
 866
 867         return ret;
 868 }
 869
 870 /**
 871  * fw_log_copy - copy firmware log from device's buffer to driver's circular
 872  *      buffer.
 873  * @param tegra tegra_xhci_hcd context
 874  * @return true,        We still have firmware log in device's buffer to copy.
 875  *                      This function returned due the driver's circular buffer
 876  *                      is full. Caller should invoke this function again as
 877  *                      soon as there is space in driver's circular buffer.
 878  *         false,       Device's buffer is empty.
 879  */
 880 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
 881 {
 882         struct device *dev = &tegra->pdev->dev;
 883         struct circ_buf *circ = &tegra->log.circ;
 884         int head, tail;
 885         int buffer_len, copy_len;
 886         struct log_entry *entry;
 887         struct log_entry *first = tegra->log.virt_addr;
 888
 889         while (fw_log_available(tegra)) {
 890
 891                 /* calculate maximum contiguous driver buffer length */
 892                 head = circ->head;
 893                 tail = ACCESS_ONCE(circ->tail);
 894                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
 895                 /* round down to FW_LOG_SIZE */
 896                 buffer_len -= (buffer_len % FW_LOG_SIZE);
 897                 if (!buffer_len)
 898                         return true; /* log available but no space left */
 899
 900                 /* calculate maximum contiguous log copy length */
 901                 entry = tegra->log.dequeue;
 902                 copy_len = 0;
 903                 do {
 904                         if (tegra->log.seq != entry->sequence_no) {
 905                                 dev_warn(dev,
 906                                 "%s: discontinuous seq no, expect %u get %u\n",
 907                                 __func__, tegra->log.seq, entry->sequence_no);
 908                         }
 909                         tegra->log.seq = entry->sequence_no + 1;
 910
 911                         copy_len += FW_LOG_SIZE;
 912                         buffer_len -= FW_LOG_SIZE;
 913                         if (!buffer_len)
 914                                 break; /* no space left */
 915                         entry = fw_log_next(&tegra->log, entry);
 916                 } while ((entry->owner == DRIVER) && (entry != first));
 917
 918                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
 919                 memset(tegra->log.dequeue, 0, copy_len);
 920                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
 921
 922                 mb();
 923
 924                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
 925
 926                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
 927                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
 928                 wake_up_interruptible(&tegra->log.read_wait);
 929         }
 930
 931         return false;
 932 }
 933
 934 static int fw_log_thread(void *data)
 935 {
 936         struct tegra_xhci_hcd *tegra = data;
 937         struct device *dev = &tegra->pdev->dev;
 938         struct circ_buf *circ = &tegra->log.circ;
 939         bool logs_left;
 940
 941         dev_dbg(dev, "start firmware log thread\n");
 942
 943         do {
 944                 mutex_lock(&tegra->log.mutex);
 945                 if (circ_buffer_full(circ)) {
 946                         mutex_unlock(&tegra->log.mutex);
 947                         dev_info(dev, "%s: circ buffer full\n", __func__);
 948                         wait_event_interruptible(tegra->log.write_wait,
 949                             kthread_should_stop() || !circ_buffer_full(circ));
 950                         mutex_lock(&tegra->log.mutex);
 951                 }
 952
 953                 logs_left = fw_log_copy(tegra);
 954                 mutex_unlock(&tegra->log.mutex);
 955
 956                 /* relax if no logs left  */
 957                 if (!logs_left)
 958                         wait_event_interruptible_timeout(tegra->log.intr_wait,
 959                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
 960         } while (!kthread_should_stop());
 961
 962         dev_dbg(dev, "stop firmware log thread\n");
 963         return 0;
 964 }
 965
 966 static inline bool circ_buffer_empty(struct circ_buf *circ)
 967 {
 968         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
 969 }
 970
 971 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
 972                 size_t count, loff_t *offp)
 973 {
 974         struct tegra_xhci_hcd *tegra = file->private_data;
 975         struct platform_device *pdev = tegra->pdev;
 976         struct circ_buf *circ = &tegra->log.circ;
 977         int head, tail;
 978         size_t n = 0;
 979         int s;
 980
 981         mutex_lock(&tegra->log.mutex);
 982
 983         while (circ_buffer_empty(circ)) {
 984                 mutex_unlock(&tegra->log.mutex);
 985                 if (file->f_flags & O_NONBLOCK)
 986                         return -EAGAIN; /* non-blocking read */
 987
 988                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
 989
 990                 if (wait_event_interruptible(tegra->log.read_wait,
 991                                 !circ_buffer_empty(circ)))
 992                         return -ERESTARTSYS;
 993
 994                 if (mutex_lock_interruptible(&tegra->log.mutex))
 995                         return -ERESTARTSYS;
 996         }
 997
 998         while (count > 0) {
 999                 head = ACCESS_ONCE(circ->head);
1000                 tail = circ->tail;
1001                 s = min_t(int, count,
1002                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
1003
1004                 if (s > 0) {
1005                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
1006                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1007                                 mutex_unlock(&tegra->log.mutex);
1008                                 return -EFAULT;
1009                         }
1010                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1011
1012                         count -= s;
1013                         n += s;
1014                 } else
1015                         break;
1016         }
1017
1018         mutex_unlock(&tegra->log.mutex);
1019
1020         wake_up_interruptible(&tegra->log.write_wait);
1021
1022         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
1023
1024         return n;
1025 }
1026
1027 static int fw_log_file_open(struct inode *inode, struct file *file)
1028 {
1029         struct tegra_xhci_hcd *tegra;
1030         file->private_data = inode->i_private;
1031         tegra = file->private_data;
1032
1033         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1034                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1035                 return -EBUSY;
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int fw_log_file_close(struct inode *inode, struct file *file)
1042 {
1043         struct tegra_xhci_hcd *tegra = file->private_data;
1044
1045         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1046
1047         return 0;
1048 }
1049
1050 static const struct file_operations firmware_log_fops = {
1051                 .open           = fw_log_file_open,
1052                 .release        = fw_log_file_close,
1053                 .read           = fw_log_file_read,
1054                 .owner          = THIS_MODULE,
1055 };
1056
1057 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1058 {
1059         struct platform_device *pdev = tegra->pdev;
1060         int rc = 0;
1061
1062         /* allocate buffer to be shared between driver and firmware */
1063         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1064                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1065
1066         if (!tegra->log.virt_addr) {
1067                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1068                                 FW_LOG_RING_SIZE);
1069                 return -ENOMEM;
1070         }
1071
1072         dev_info(&pdev->dev,
1073                 "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1074                 FW_LOG_RING_SIZE, (u32)tegra->log.phys_addr,
1075                 tegra->log.virt_addr);
1076
1077         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1078         tegra->log.dequeue = tegra->log.virt_addr;
1079
1080         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1081         if (!tegra->log.circ.buf) {
1082                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1083                 rc = -ENOMEM;
1084                 goto error_free_dma;
1085         }
1086
1087         tegra->log.circ.head = 0;
1088         tegra->log.circ.tail = 0;
1089
1090         init_waitqueue_head(&tegra->log.read_wait);
1091         init_waitqueue_head(&tegra->log.write_wait);
1092         init_waitqueue_head(&tegra->log.intr_wait);
1093
1094         mutex_init(&tegra->log.mutex);
1095
1096         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1097         if (IS_ERR_OR_NULL(tegra->log.path)) {
1098                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1099                 rc = -ENOMEM;
1100                 goto error_free_mem;
1101         }
1102
1103         tegra->log.log_file = debugfs_create_file("firmware_log",
1104                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1105         if ((!tegra->log.log_file) ||
1106                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1107                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1108                 rc = -ENOMEM;
1109                 goto error_remove_debugfs_path;
1110         }
1111
1112         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1113         if (IS_ERR(tegra->log.thread)) {
1114                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1115                 rc = -ENOMEM;
1116                 goto error_remove_debugfs_file;
1117         }
1118
1119         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1120         return rc;
1121
1122 error_remove_debugfs_file:
1123         debugfs_remove(tegra->log.log_file);
1124 error_remove_debugfs_path:
1125         debugfs_remove(tegra->log.path);
1126 error_free_mem:
1127         vfree(tegra->log.circ.buf);
1128 error_free_dma:
1129         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1130                         tegra->log.virt_addr, tegra->log.phys_addr);
1131         memset(&tegra->log, sizeof(tegra->log), 0);
1132         return rc;
1133 }
1134
1135 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1136 {
1137         struct platform_device *pdev = tegra->pdev;
1138
1139         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1140
1141                 debugfs_remove(tegra->log.log_file);
1142                 debugfs_remove(tegra->log.path);
1143
1144                 wake_up_interruptible(&tegra->log.read_wait);
1145                 wake_up_interruptible(&tegra->log.write_wait);
1146                 kthread_stop(tegra->log.thread);
1147
1148                 mutex_lock(&tegra->log.mutex);
1149                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1150                         tegra->log.virt_addr, tegra->log.phys_addr);
1151                 vfree(tegra->log.circ.buf);
1152                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1153                 mutex_unlock(&tegra->log.mutex);
1154
1155                 mutex_destroy(&tegra->log.mutex);
1156         }
1157 }
1158
1159 /* hsic pad operations */
1160 /*
1161  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1162  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1163  */
1164 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1165 {
1166         struct device *dev = &tegra->pdev->dev;
1167         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1168         int ret;
1169
1170         if (tegra->vddio_hsic_reg)
1171                 goto done;
1172
1173         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1174         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1175                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1176                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1177                 goto get_failed;
1178         }
1179
1180         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1181         ret = regulator_enable(tegra->vddio_hsic_reg);
1182         if (ret < 0) {
1183                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1184                 goto enable_failed;
1185         }
1186
1187 done:
1188         tegra->vddio_hsic_refcnt++;
1189         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1190                         "vddio_hsic_refcnt exceeds\n");
1191         return 0;
1192
1193 enable_failed:
1194         devm_regulator_put(tegra->vddio_hsic_reg);
1195 get_failed:
1196         tegra->vddio_hsic_reg = NULL;
1197         return ret;
1198 }
1199
1200 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1201 {
1202         struct device *dev = &tegra->pdev->dev;
1203         int ret;
1204
1205         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1206
1207         tegra->vddio_hsic_refcnt--;
1208         if (tegra->vddio_hsic_refcnt)
1209                 return 0;
1210
1211         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1212         ret = regulator_disable(tegra->vddio_hsic_reg);
1213         if (ret < 0) {
1214                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1215                 tegra->vddio_hsic_refcnt++;
1216                 return ret;
1217         }
1218
1219         devm_regulator_put(tegra->vddio_hsic_reg);
1220         tegra->vddio_hsic_reg = NULL;
1221
1222         return 0;
1223 }
1224
1225 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1226 {
1227         struct device *dev = &tegra->pdev->dev;
1228         void __iomem *base = tegra->padctl_base;
1229         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1230         u32 reg;
1231
1232         if (pad >= XUSB_HSIC_COUNT) {
1233                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1234                 return -EINVAL;
1235         }
1236
1237         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1238
1239         reg = readl(base + HSIC_PAD_CTL_2(pad));
1240         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1241         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1242         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1243         writel(reg, base + HSIC_PAD_CTL_2(pad));
1244
1245         reg = readl(base + HSIC_PAD_CTL_0(pad));
1246         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1247         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1248         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1249         reg |= TX_SLEWP(hsic->tx_slew_p);
1250         reg |= TX_SLEWN(hsic->tx_slew_n);
1251         writel(reg, base + HSIC_PAD_CTL_0(pad));
1252
1253         reg = readl(base + HSIC_PAD_CTL_1(pad));
1254         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1255         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1256         if (hsic->auto_term_en)
1257                 reg |= AUTO_TERM_EN;
1258         else
1259                 reg &= ~AUTO_TERM_EN;
1260         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1261         writel(reg, base + HSIC_PAD_CTL_1(pad));
1262
1263         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1264         reg &= ~(STRB_TRIM_VAL(~0));
1265         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1266         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1267
1268         reg = readl(base + USB2_PAD_MUX);
1269         reg |= USB2_HSIC_PAD_PORT(pad);
1270         writel(reg, base + USB2_PAD_MUX);
1271
1272         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1273         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1274         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1275         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1276         reg_dump(dev, base, USB2_PAD_MUX);
1277         return 0;
1278 }
1279
1280 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1281 {
1282         struct device *dev = &tegra->pdev->dev;
1283         struct tegra_xusb_hsic_config *hsic;
1284         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1285         int pad;
1286         u32 portsc;
1287         int port;
1288         int enabled_pads = 0;
1289         unsigned long wait_ports = 0;
1290         unsigned long target;
1291
1292         for_each_enabled_hsic_pad(pad, tegra) {
1293                 hsic = &tegra->bdata->hsic[pad];
1294                 if (hsic->pretend_connect)
1295                         enabled_pads++;
1296         }
1297
1298         if (enabled_pads == 0) {
1299                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1300                 return;
1301         }
1302
1303         usb_disable_autosuspend(hs_root_hub);
1304
1305         for_each_enabled_hsic_pad(pad, tegra) {
1306                 hsic = &tegra->bdata->hsic[pad];
1307                 if (!hsic->pretend_connect)
1308                         continue;
1309
1310                 port = hsic_pad_to_port(pad);
1311                 portsc = xhci_read_portsc(tegra->xhci, port);
1312                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1313
1314                 if (!(portsc & PORT_CONNECT)) {
1315                         /* firmware wants 1-based port index */
1316                         fw_message_send(tegra,
1317                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1318                 }
1319
1320                 set_bit(port, &wait_ports);
1321         }
1322
1323         /* wait till port reaches U0 */
1324         target = jiffies + msecs_to_jiffies(500);
1325         do {
1326                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1327                         portsc = xhci_read_portsc(tegra->xhci, port);
1328                         pad = port_to_hsic_pad(port);
1329                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1330                                 pad, portsc);
1331                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1332                                 clear_bit(port, &wait_ports);
1333                 }
1334
1335                 if (wait_ports)
1336                         usleep_range(1000, 5000);
1337         } while (wait_ports && time_is_after_jiffies(target));
1338
1339         if (wait_ports)
1340                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1341
1342         usb_enable_autosuspend(hs_root_hub);
1343
1344         return;
1345 }
1346
1347 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1348 {
1349         struct device *dev = &tegra->pdev->dev;
1350         void __iomem *base = tegra->padctl_base;
1351         u32 reg;
1352
1353         if (pad >= XUSB_HSIC_COUNT) {
1354                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1355                 return -EINVAL;
1356         }
1357
1358         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1359
1360         reg = readl(base + USB2_PAD_MUX);
1361         reg &= ~USB2_HSIC_PAD_PORT(pad);
1362         writel(reg, base + USB2_PAD_MUX);
1363
1364         reg = readl(base + HSIC_PAD_CTL_1(pad));
1365         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1366         writel(reg, base + HSIC_PAD_CTL_1(pad));
1367
1368         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1369         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1370         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1371         reg_dump(dev, base, USB2_PAD_MUX);
1372         return 0;
1373 }
1374
1375 enum hsic_pad_pupd {
1376         PUPD_DISABLE = 0,
1377         PUPD_IDLE,
1378         PUPD_RESET
1379 };
1380
1381 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1382         enum hsic_pad_pupd pupd)
1383 {
1384         struct device *dev = &tegra->pdev->dev;
1385         void __iomem *base = tegra->padctl_base;
1386         u32 reg;
1387
1388         if (pad >= XUSB_HSIC_COUNT) {
1389                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1390                 return -EINVAL;
1391         }
1392
1393         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1394
1395         reg = readl(base + HSIC_PAD_CTL_1(pad));
1396         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1397
1398         if (pupd == PUPD_IDLE)
1399                 reg |= (RPD_DATA | RPU_STROBE);
1400         else if (pupd == PUPD_RESET)
1401                 reg |= (RPD_DATA | RPD_STROBE);
1402         else if (pupd != PUPD_DISABLE) {
1403                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1404                 return -EINVAL;
1405         }
1406
1407         writel(reg, base + HSIC_PAD_CTL_1(pad));
1408
1409         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1410
1411         return 0;
1412 }
1413
1414
1415 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1416 {
1417         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1418         struct xhci_hcd *xhci = tegra->xhci;
1419         u32 reg;
1420
1421         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1422         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1423         xhci_info(xhci, " PAD MUX = %x\n", reg);
1424         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1425         xhci_info(xhci, " PORT CAP = %x\n", reg);
1426         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1427         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1428         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1429         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1430         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1431         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1432         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1433         xhci_info(xhci, " OC DET 0= %x\n", reg);
1434         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1435         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1436         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1437         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1438         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1439         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1440         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1441         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1442         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1443         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1444         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1445         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1446         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1447         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1448         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1449         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1450         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1451         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1452         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1453 }
1454
1455 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1456 {
1457         u32 reg;
1458
1459         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1460         reg |= IPFS_EN_FPCI;
1461         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1462         udelay(10);
1463
1464         /* Program Bar0 Space */
1465         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1466         reg |= tegra->host_phy_base;
1467         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1468         usleep_range(100, 200);
1469
1470         /* Enable Bus Master */
1471         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1472         reg |= 0x7;
1473         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1474
1475         /* Set intr mask to enable intr assertion */
1476         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1477         reg |= IPFS_IP_INT_MASK;
1478         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1479
1480         /* Set hysteris to 0x80 */
1481         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1482 }
1483
1484 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1485                 struct platform_device *pdev)
1486 {
1487         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1488         int i;
1489         int err = 0;
1490
1491         tegra->xusb_s3p3v_reg =
1492                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1493         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1494                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1495                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1496                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1497                 goto err_null_regulator;
1498         } else {
1499                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1500                 if (err < 0) {
1501                         dev_err(&pdev->dev,
1502                                 "3p3v: regulator enable failed:%d\n", err);
1503                         goto err_null_regulator;
1504                 }
1505         }
1506
1507         /* enable utmi vbuses */
1508         memset(tegra->xusb_utmi_vbus_regs, 0,
1509                         sizeof(tegra->xusb_utmi_vbus_regs));
1510         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1511                 struct regulator *reg = NULL;
1512                 const char *reg_name = supply->utmi_vbuses[i];
1513                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1514                         if (i == 0 && tegra->transceiver)
1515                                 continue;
1516                         reg = devm_regulator_get(&pdev->dev, reg_name);
1517                         if (IS_ERR(reg)) {
1518                                 dev_err(&pdev->dev,
1519                                         "%s regulator not found: %ld.",
1520                                         reg_name, PTR_ERR(reg));
1521                                 err = PTR_ERR(reg);
1522                         } else {
1523                                 err = regulator_enable(reg);
1524                                 if (err < 0) {
1525                                         dev_err(&pdev->dev,
1526                                         "%s: regulator enable failed: %d\n",
1527                                         reg_name, err);
1528                                 }
1529                         }
1530                         if (err)
1531                                 goto err_put_utmi_vbus_reg;
1532                 }
1533                 tegra->xusb_utmi_vbus_regs[i] = reg;
1534         }
1535
1536         tegra->xusb_s1p8v_reg =
1537                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1538         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1539                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1540                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1541                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1542                 goto err_put_utmi_vbus_reg;
1543         } else {
1544                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1545                 if (err < 0) {
1546                         dev_err(&pdev->dev,
1547                         "1p8v: regulator enable failed:%d\n", err);
1548                         goto err_put_utmi_vbus_reg;
1549                 }
1550         }
1551
1552         tegra->xusb_s1p05v_reg =
1553                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1554         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1555                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1556                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1557                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1558                 goto err_put_s1p8v_reg;
1559         } else {
1560                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1561                 if (err < 0) {
1562                         dev_err(&pdev->dev,
1563                         "1p05v: regulator enable failed:%d\n", err);
1564                         goto err_put_s1p8v_reg;
1565                 }
1566         }
1567
1568         return err;
1569
1570 err_put_s1p8v_reg:
1571         regulator_disable(tegra->xusb_s1p8v_reg);
1572 err_put_utmi_vbus_reg:
1573         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1574                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1575                 if (!IS_ERR_OR_NULL(reg))
1576                         regulator_disable(reg);
1577         }
1578         regulator_disable(tegra->xusb_s3p3v_reg);
1579 err_null_regulator:
1580         for (i = 0; i < XUSB_UTMI_COUNT; i++)
1581                 tegra->xusb_utmi_vbus_regs[i] = NULL;
1582         tegra->xusb_s1p05v_reg = NULL;
1583         tegra->xusb_s3p3v_reg = NULL;
1584         tegra->xusb_s1p8v_reg = NULL;
1585         return err;
1586 }
1587
1588 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1589 {
1590         int i;
1591
1592         regulator_disable(tegra->xusb_s1p05v_reg);
1593         regulator_disable(tegra->xusb_s1p8v_reg);
1594
1595         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1596                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1597                         struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1598                         if (!IS_ERR_OR_NULL(reg))
1599                                 regulator_disable(reg);
1600                         tegra->xusb_utmi_vbus_regs[i] = NULL;
1601                 }
1602         }
1603
1604         regulator_disable(tegra->xusb_s3p3v_reg);
1605
1606         tegra->xusb_s1p05v_reg = NULL;
1607         tegra->xusb_s1p8v_reg = NULL;
1608         tegra->xusb_s3p3v_reg = NULL;
1609 }
1610
1611 /*
1612  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1613  * are under hardware control
1614  */
1615 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1616 {
1617         struct platform_device *pdev = tegra->pdev;
1618         int err = 0;
1619
1620         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1621         if (IS_ERR(tegra->plle_clk)) {
1622                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1623                 err = PTR_ERR(tegra->plle_clk);
1624                 return err;
1625         }
1626         err = clk_enable(tegra->plle_clk);
1627         if (err) {
1628                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1629                         __func__);
1630                 return err;
1631         }
1632
1633         return err;
1634 }
1635
1636 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1637 {
1638         clk_disable(tegra->plle_clk);
1639         tegra->plle_clk = NULL;
1640 }
1641
1642 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1643 {
1644         struct platform_device *pdev = tegra->pdev;
1645         int err = 0;
1646
1647         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1648         if (IS_ERR(tegra->emc_clk)) {
1649                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1650                 return PTR_ERR(tegra->emc_clk);
1651         }
1652
1653         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1654                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1655                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1656                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1657                         err = PTR_ERR(tegra->pll_re_vco_clk);
1658                         goto get_pll_re_vco_clk_failed;
1659                 }
1660         }
1661
1662         /* get the clock handle of 120MHz clock source */
1663         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1664         if (IS_ERR(tegra->pll_u_480M)) {
1665                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1666                 err = PTR_ERR(tegra->pll_u_480M);
1667                 goto get_pll_u_480M_failed;
1668         }
1669
1670         /* get the clock handle of 12MHz clock source */
1671         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1672         if (IS_ERR(tegra->clk_m)) {
1673                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1674                 err = PTR_ERR(tegra->clk_m);
1675                 goto clk_get_clk_m_failed;
1676         }
1677
1678         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1679         if (IS_ERR(tegra->ss_src_clk)) {
1680                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1681                 err = PTR_ERR(tegra->ss_src_clk);
1682                 tegra->ss_src_clk = NULL;
1683                 goto get_ss_src_clk_failed;
1684         }
1685
1686         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1687         if (IS_ERR(tegra->host_clk)) {
1688                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1689                 err = PTR_ERR(tegra->host_clk);
1690                 tegra->host_clk = NULL;
1691                 goto get_host_clk_failed;
1692         }
1693
1694         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1695         if (IS_ERR(tegra->ss_clk)) {
1696                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1697                 err = PTR_ERR(tegra->ss_clk);
1698                 tegra->ss_clk = NULL;
1699                 goto get_ss_clk_failed;
1700         }
1701
1702         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1703                 err = clk_enable(tegra->pll_re_vco_clk);
1704                 if (err) {
1705                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1706                         goto enable_pll_re_vco_clk_failed;
1707                 }
1708         }
1709         return 0;
1710
1711 enable_pll_re_vco_clk_failed:
1712         tegra->ss_clk = NULL;
1713
1714 get_ss_clk_failed:
1715         tegra->host_clk = NULL;
1716
1717 get_host_clk_failed:
1718         tegra->ss_src_clk = NULL;
1719
1720 get_ss_src_clk_failed:
1721         tegra->clk_m = NULL;
1722
1723 clk_get_clk_m_failed:
1724         tegra->pll_u_480M = NULL;
1725
1726 get_pll_u_480M_failed:
1727         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1728                 tegra->pll_re_vco_clk = NULL;
1729
1730 get_pll_re_vco_clk_failed:
1731         tegra->emc_clk = NULL;
1732
1733         return err;
1734 }
1735
1736 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1737 {
1738         clk_disable(tegra->ss_clk);
1739         clk_disable(tegra->host_clk);
1740         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1741                 clk_disable(tegra->pll_re_vco_clk);
1742         tegra->ss_clk = NULL;
1743         tegra->host_clk = NULL;
1744         tegra->ss_src_clk = NULL;
1745         tegra->clk_m = NULL;
1746         tegra->pll_u_480M = NULL;
1747         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1748                 tegra->pll_re_vco_clk = NULL;
1749 }
1750
1751 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1752         bool enable)
1753 {
1754         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1755         u32 reg;
1756
1757         /* Issue is only applicable for T114 */
1758         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1759                 return;
1760
1761         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1762                 reg = readl(tegra->padctl_base +
1763                         padregs->iophy_misc_pad_p0_ctl3_0);
1764                 if (enable) {
1765                         reg &= ~RX_IDLE_MODE;
1766                         reg |= RX_IDLE_MODE_OVRD;
1767                 } else {
1768                         reg |= RX_IDLE_MODE;
1769                         reg &= ~RX_IDLE_MODE_OVRD;
1770                 }
1771                 writel(reg, tegra->padctl_base +
1772                         padregs->iophy_misc_pad_p0_ctl3_0);
1773         }
1774
1775         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1776                 reg = readl(tegra->padctl_base +
1777                         padregs->iophy_misc_pad_p1_ctl3_0);
1778                 if (enable) {
1779                         reg &= ~RX_IDLE_MODE;
1780                         reg |= RX_IDLE_MODE_OVRD;
1781                 } else {
1782                         reg |= RX_IDLE_MODE;
1783                         reg &= ~RX_IDLE_MODE_OVRD;
1784                 }
1785                 writel(reg, tegra->padctl_base +
1786                         padregs->iophy_misc_pad_p1_ctl3_0);
1787
1788                 /* SATA lane also if USB3_SS port1 mapped to it */
1789                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1790                                 tegra->bdata->lane_owner & BIT(0)) {
1791                         reg = readl(tegra->padctl_base +
1792                                 padregs->iophy_misc_pad_s0_ctl3_0);
1793                         if (enable) {
1794                                 reg &= ~RX_IDLE_MODE;
1795                                 reg |= RX_IDLE_MODE_OVRD;
1796                         } else {
1797                                 reg |= RX_IDLE_MODE;
1798                                 reg &= ~RX_IDLE_MODE_OVRD;
1799                         }
1800                         writel(reg, tegra->padctl_base +
1801                                 padregs->iophy_misc_pad_s0_ctl3_0);
1802                 }
1803         }
1804 }
1805
1806 /* Enable ss clk, host clk, falcon clk,
1807  * fs clk, dev clk, plle and refplle
1808  */
1809
1810 static int
1811 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1812                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1813 {
1814         int ret = 0;
1815         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1816         int fw_req_rate = rate, cur_rate;
1817
1818         /* Do not handle clock change as needed for HS disconnect issue */
1819         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1820                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1821                 return ret;
1822         }
1823
1824         /* frequency request from firmware is in KHz.
1825          * Convert it to MHz
1826          */
1827
1828         /* get current rate of clock */
1829         cur_rate = clk_get_rate(clk_handle);
1830         cur_rate /= 1000;
1831
1832         if (fw_req_rate == cur_rate) {
1833                 cmd_ack = MBOX_CMD_ACK;
1834
1835         } else {
1836
1837                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1838                         /* Change SS clock source to CLK_M at 12MHz */
1839                         clk_set_parent(clk_handle, tegra->clk_m);
1840                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1841
1842                         /* save leakage power when SS freq is being decreased */
1843                         tegra_xhci_rx_idle_mode_override(tegra, true);
1844                 } else if (clk_handle == tegra->ss_src_clk &&
1845                                 fw_req_rate == 120000) {
1846                         /* Change SS clock source to HSIC_480 at 120MHz */
1847                         clk_set_rate(clk_handle,  3000 * 1000);
1848                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1849
1850                         /* clear ovrd bits when SS freq is being increased */
1851                         tegra_xhci_rx_idle_mode_override(tegra, false);
1852                 }
1853
1854                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1855
1856                 if (cur_rate != fw_req_rate) {
1857                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1858                                 cur_rate, fw_req_rate);
1859                         cmd_ack = MBOX_CMD_NACK;
1860                 }
1861         }
1862         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1863         return ret;
1864 }
1865
1866 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1867 {
1868         unsigned int freq_khz;
1869
1870         freq_khz = tegra_emc_bw_to_freq_req(bw);
1871         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1872 }
1873
1874 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1875         u8 port)
1876 {
1877         struct xhci_hcd *xhci = tegra->xhci;
1878         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1879         u32 offset;
1880         u32 reg;
1881
1882         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1883                 pr_err("%s invalid SS port number %u\n", __func__, port);
1884                 return;
1885         }
1886
1887         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1888
1889         /* if port1 is mapped to SATA lane then read from SATA register */
1890         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1891                         tegra->bdata->lane_owner & BIT(0))
1892                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1893         else
1894                 offset = MISC_PAD_CTL_6_0(port);
1895
1896         /*
1897          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1898          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1899          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1900          */
1901         reg = readl(tegra->padctl_base + offset);
1902         reg &= ~MISC_OUT_SEL(~0);
1903         reg |= MISC_OUT_SEL(0x32);
1904         writel(reg, tegra->padctl_base + offset);
1905
1906         reg = readl(tegra->padctl_base + offset);
1907         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1908
1909         reg = readl(tegra->padctl_base + offset);
1910         reg &= ~MISC_OUT_SEL(~0);
1911         reg |= MISC_OUT_SEL(0x33);
1912         writel(reg, tegra->padctl_base + offset);
1913
1914         reg = readl(tegra->padctl_base + offset);
1915         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1916
1917         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1918         reg &= ~DFE_CNTL_TAP_VAL(~0);
1919         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1920         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1921
1922         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1923         reg &= ~DFE_CNTL_AMP_VAL(~0);
1924         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1925         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1926
1927         tegra->dfe_ctx_saved[port] = true;
1928 }
1929
1930 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1931         u8 port)
1932 {
1933         struct xhci_hcd *xhci = tegra->xhci;
1934         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1935         u32 offset;
1936         u32 reg;
1937
1938         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1939                 pr_err("%s invalid SS port number %u\n", __func__, port);
1940                 return;
1941         }
1942
1943         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1944
1945         /* if port1 is mapped to SATA lane then read from SATA register */
1946         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1947                         tegra->bdata->lane_owner & BIT(0))
1948                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1949         else
1950                 offset = MISC_PAD_CTL_6_0(port);
1951
1952         /*
1953          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1954          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1955          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1956          */
1957         reg = readl(tegra->padctl_base + offset);
1958         reg &= ~MISC_OUT_SEL(~0);
1959         reg |= MISC_OUT_SEL(0xa1);
1960         writel(reg, tegra->padctl_base + offset);
1961
1962         reg = readl(tegra->padctl_base + offset);
1963         reg &= ~MISC_OUT_SEL(~0);
1964         reg |= MISC_OUT_SEL(0x21);
1965         writel(reg, tegra->padctl_base + offset);
1966
1967         reg = readl(tegra->padctl_base + offset);
1968         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1969
1970         reg = readl(tegra->padctl_base + offset);
1971         reg &= ~MISC_OUT_SEL(~0);
1972         reg |= MISC_OUT_SEL(0x48);
1973         writel(reg, tegra->padctl_base + offset);
1974
1975         reg = readl(tegra->padctl_base + offset);
1976         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1977
1978         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1979         reg &= ~RX_EQ_Z_VAL(~0);
1980         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1981         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1982
1983         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1984         reg &= ~RX_EQ_G_VAL(~0);
1985         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1986         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1987
1988         tegra->ctle_ctx_saved[port] = true;
1989 }
1990
1991 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1992         u8 port)
1993 {
1994         struct xhci_hcd *xhci = tegra->xhci;
1995         u32 reg;
1996
1997         /* don't restore if not saved */
1998         if (tegra->dfe_ctx_saved[port] == false)
1999                 return;
2000
2001         xhci_info(xhci, "restoring dfe context of port %d\n", port);
2002
2003         /* restore dfe_cntl for the port */
2004         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2005         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
2006                         DFE_CNTL_TAP_VAL(~0));
2007         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
2008                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2009         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2010 }
2011
2012 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2013         u8 port)
2014 {
2015         struct xhci_hcd *xhci = tegra->xhci;
2016         u32 reg;
2017
2018         /* don't restore if not saved */
2019         if (tegra->ctle_ctx_saved[port] == false)
2020                 return;
2021
2022         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2023
2024         /* restore ctle for the port */
2025         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2026         reg &= ~(RX_EQ_Z_VAL(~0) |
2027                         RX_EQ_G_VAL(~0));
2028         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2029                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2030         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2031 }
2032
2033 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2034         u8 port)
2035 {
2036         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2037         u32 reg;
2038
2039         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2040         reg &= ~USB2_ULPI_PAD;
2041         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2042         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2043
2044         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2045         reg &= ~USB2_ULPI_PORT_CAP;
2046         reg |= (tegra->bdata->ulpicap << 24);
2047         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2048         /* FIXME: Program below when more details available
2049          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2050          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2051          */
2052 }
2053
2054 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2055         u8 port)
2056 {
2057         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2058         u32 reg;
2059         u32 ctl0_offset, ctl1_offset;
2060
2061         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2062         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2063         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2064         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2065
2066         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2067         reg &= ~USB2_PORT_CAP_MASK(port);
2068         reg |= USB2_PORT_CAP_HOST(port);
2069         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2070
2071         /*
2072          * Modify only the bits which belongs to the port
2073          * and enable respective VBUS_PAD for the port
2074          */
2075         if (tegra->bdata->uses_external_pmic == false) {
2076                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2077                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2078                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2079                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2080
2081                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2082                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2083                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2084                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2085         }
2086         /*
2087          * enable respective VBUS_PAD if port is mapped to any SS port
2088          */
2089         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2090         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2091                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2092         reg |= (0x4 | port) << (port * 3);
2093         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2094
2095         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2096                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2097                                 padregs->usb2_otg_pad0_ctl0_0;
2098         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2099                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2100                                 padregs->usb2_otg_pad0_ctl1_0;
2101
2102         reg = readl(tegra->padctl_base + ctl0_offset);
2103         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2104                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2105                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2106
2107         reg |= tegra->soc_config->hs_slew;
2108         reg |= (port == 2) ? tegra->soc_config->ls_rslew_pad2 :
2109                         port ? tegra->soc_config->ls_rslew_pad1 :
2110                         tegra->soc_config->ls_rslew_pad0;
2111         reg |= (port == 2) ? tegra->cdata->hs_curr_level_pad2 :
2112                         port ? tegra->cdata->hs_curr_level_pad1 :
2113                         tegra->cdata->hs_curr_level_pad0;
2114         writel(reg, tegra->padctl_base + ctl0_offset);
2115
2116         reg = readl(tegra->padctl_base + ctl1_offset);
2117         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2118                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2119                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2120                 | USB2_OTG_PD_DR);
2121         reg |= (tegra->cdata->hs_iref_cap << 9) |
2122                 (tegra->cdata->hs_term_range_adj << 3);
2123         writel(reg, tegra->padctl_base + ctl1_offset);
2124
2125         /*Release OTG port if not in host mode*/
2126
2127         if ((port == 0) && !is_otg_host(tegra))
2128                 tegra_xhci_release_otg_port(true);
2129 }
2130
2131 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2132 {
2133         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2134         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2135                 && (tegra->bdata->lane_owner & BIT(0))));
2136 }
2137
2138 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2139         u8 port)
2140 {
2141         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2142         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2143         u32 reg;
2144
2145         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2146                         padregs->iophy_usb3_pad0_ctl2_0;
2147         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2148                         padregs->iophy_usb3_pad0_ctl4_0;
2149         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2150                         padregs->iophy_misc_pad_p0_ctl5_0;
2151
2152         reg = readl(tegra->padctl_base + ctl2_offset);
2153         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2154                 IOPHY_USB3_CDRCNTL);
2155         reg |= tegra->soc_config->rx_wander | tegra->soc_config->rx_eq |
2156                 tegra->soc_config->cdr_cntl;
2157         writel(reg, tegra->padctl_base + ctl2_offset);
2158
2159         reg = readl(tegra->padctl_base + ctl4_offset);
2160         reg = tegra->soc_config->dfe_cntl;
2161         writel(reg, tegra->padctl_base + ctl4_offset);
2162
2163         reg = readl(tegra->padctl_base + ctl5_offset);
2164         reg |= RX_QEYE_EN;
2165         writel(reg, tegra->padctl_base + ctl5_offset);
2166
2167         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2168         reg &= ~SPARE_IN(~0);
2169         reg |= SPARE_IN(tegra->soc_config->spare_in);
2170         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2171
2172         if (xusb_use_sata_lane(tegra)) {
2173                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2174                 reg |= RX_QEYE_EN;
2175                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2176
2177                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2178                 reg &= ~SPARE_IN(~0);
2179                 reg |= SPARE_IN(tegra->soc_config->spare_in);
2180                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2181         }
2182
2183         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2184         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2185         reg |= (tegra->bdata->ss_portmap &
2186                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2187         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2188
2189         tegra_xhci_restore_dfe_context(tegra, port);
2190         tegra_xhci_restore_ctle_context(tegra, port);
2191 }
2192
2193 /* This function assigns the USB ports to the controllers,
2194  * then programs the port capabilities and pad parameters
2195  * of ports assigned to XUSB after booted to OS.
2196  */
2197 void
2198 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2199 {
2200         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2201         u32 reg, oc_bits = 0;
2202         unsigned pad;
2203
2204         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2205         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2206         reg |= tegra->cdata->hs_squelch_level | tegra->soc_config->hs_disc_lvl;
2207         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2208
2209         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2210         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2211         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2212         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2213
2214         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2215         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2216         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2217                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2218         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2219
2220         /* check if over current seen. Clear if present */
2221         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2222                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2223         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2224                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2225         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2226                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2227
2228         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2229         if (reg & oc_bits) {
2230                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2231                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2232
2233                 usleep_range(100, 200);
2234
2235                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2236                 if (reg & oc_bits)
2237                         xhci_info(tegra->xhci, "Over current still present\n");
2238         }
2239
2240         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2241         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2242         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2243                 reg |= USB2_OC_MAP_PORT2;
2244         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2245
2246         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2247                 tegra_xhci_program_utmip_pad(tegra, 0);
2248         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2249                 tegra_xhci_program_utmip_pad(tegra, 1);
2250         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2251                 tegra_xhci_program_utmip_pad(tegra, 2);
2252
2253         for_each_enabled_hsic_pad(pad, tegra)
2254                 hsic_pad_enable(tegra, pad);
2255
2256         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2257                 tegra_xhci_program_ulpi_pad(tegra, 0);
2258
2259         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2260                 tegra_xhci_program_ss_pad(tegra, 0);
2261         } else {
2262                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2263                 reg = readl(tegra->padctl_base +
2264                         padregs->iophy_misc_pad_p0_ctl3_0);
2265                 reg &= ~RX_IDLE_MODE;
2266                 reg |= RX_IDLE_MODE_OVRD;
2267                 writel(reg, tegra->padctl_base +
2268                         padregs->iophy_misc_pad_p0_ctl3_0);
2269         }
2270
2271         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2272                 tegra_xhci_program_ss_pad(tegra, 1);
2273         } else {
2274                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2275                 reg = readl(tegra->padctl_base +
2276                         padregs->iophy_misc_pad_p1_ctl3_0);
2277                 reg &= ~RX_IDLE_MODE;
2278                 reg |= RX_IDLE_MODE_OVRD;
2279                 writel(reg, tegra->padctl_base +
2280                         padregs->iophy_misc_pad_p1_ctl3_0);
2281
2282                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2283                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2284                                 tegra->bdata->lane_owner & BIT(0)) {
2285                         reg = readl(tegra->padctl_base +
2286                                 padregs->iophy_misc_pad_s0_ctl3_0);
2287                         reg &= ~RX_IDLE_MODE;
2288                         reg |= RX_IDLE_MODE_OVRD;
2289                         writel(reg, tegra->padctl_base +
2290                                 padregs->iophy_misc_pad_s0_ctl3_0);
2291                 }
2292         }
2293         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2294                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2295                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2296         }
2297 }
2298
2299 /* This function read XUSB registers and stores in device context */
2300 static void
2301 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2302 {
2303
2304         /* a. Save the IPFS registers */
2305         tegra->sregs.msi_bar_sz =
2306                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2307
2308         tegra->sregs.msi_axi_barst =
2309                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2310
2311         tegra->sregs.msi_fpci_barst =
2312                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2313
2314         tegra->sregs.msi_vec0 =
2315                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2316
2317         tegra->sregs.msi_en_vec0 =
2318                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2319
2320         tegra->sregs.fpci_error_masks =
2321                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2322
2323         tegra->sregs.intr_mask =
2324                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2325
2326         tegra->sregs.ipfs_intr_enable =
2327                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2328
2329         tegra->sregs.ufpci_config =
2330                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2331
2332         tegra->sregs.clkgate_hysteresis =
2333                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2334
2335         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2336                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2337
2338         /* b. Save the CFG registers */
2339
2340         tegra->sregs.hs_pls =
2341                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2342
2343         tegra->sregs.fs_pls =
2344                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2345
2346         tegra->sregs.hs_fs_speed =
2347                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2348
2349         tegra->sregs.hs_fs_pp =
2350                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2351
2352         tegra->sregs.cfg_aru =
2353                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2354
2355         tegra->sregs.cfg_order =
2356                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2357
2358         tegra->sregs.cfg_fladj =
2359                 readl(tegra->fpci_base + XUSB_CFG_24);
2360
2361         tegra->sregs.cfg_sid =
2362                 readl(tegra->fpci_base + XUSB_CFG_16);
2363 }
2364
2365 /* This function restores XUSB registers from device context */
2366 static void
2367 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2368 {
2369         /* Restore Cfg registers */
2370         writel(tegra->sregs.hs_pls,
2371                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2372
2373         writel(tegra->sregs.fs_pls,
2374                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2375
2376         writel(tegra->sregs.hs_fs_speed,
2377                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2378
2379         writel(tegra->sregs.hs_fs_pp,
2380                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2381
2382         writel(tegra->sregs.cfg_aru,
2383                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2384
2385         writel(tegra->sregs.cfg_order,
2386                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2387
2388         writel(tegra->sregs.cfg_fladj,
2389                 tegra->fpci_base + XUSB_CFG_24);
2390
2391         writel(tegra->sregs.cfg_sid,
2392                 tegra->fpci_base + XUSB_CFG_16);
2393
2394         /* Restore IPFS registers */
2395
2396         writel(tegra->sregs.msi_bar_sz,
2397                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2398
2399         writel(tegra->sregs.msi_axi_barst,
2400                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2401
2402         writel(tegra->sregs.msi_fpci_barst,
2403                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2404
2405         writel(tegra->sregs.msi_vec0,
2406                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2407
2408         writel(tegra->sregs.msi_en_vec0,
2409                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2410
2411         writel(tegra->sregs.fpci_error_masks,
2412                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2413
2414         writel(tegra->sregs.intr_mask,
2415                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2416
2417         writel(tegra->sregs.ipfs_intr_enable,
2418                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2419
2420         writel(tegra->sregs.ufpci_config,
2421                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2422
2423         writel(tegra->sregs.clkgate_hysteresis,
2424                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2425
2426         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2427                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2428 }
2429
2430 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2431 {
2432         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2433 }
2434
2435 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2436 {
2437         struct platform_device *pdev = tegra->pdev;
2438         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2439         u32 phys_addr_lo;
2440         u32 HwReg;
2441         u16 nblocks;
2442         time_t fw_time;
2443         struct tm fw_tm;
2444         u8 hc_caplength;
2445         u32 usbsts, count = 0xff;
2446         struct xhci_cap_regs __iomem *cap_regs;
2447         struct xhci_op_regs __iomem *op_regs;
2448
2449         /* enable mbox interrupt */
2450         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2451                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2452
2453         /* First thing, reset the ARU. By the time we get to
2454          * loading boot code below, reset would be complete.
2455          * alternatively we can busy wait on rst pending bit.
2456          */
2457         /* Don't reset during ELPG/LP0 exit path */
2458         if (resetARU) {
2459                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2460                 usleep_range(1000, 2000);
2461         }
2462
2463         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2464                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2465                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2466                 return 0;
2467         }
2468
2469         /* update the phys_log_buffer and total_entries here */
2470         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2471         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2472
2473         phys_addr_lo = tegra->firmware.dma;
2474         phys_addr_lo += sizeof(struct cfgtbl);
2475
2476         /* Program the size of DFI into ILOAD_ATTR */
2477         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2478
2479         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2480          * to get to the start of the dfi in system memory.
2481          */
2482         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2483
2484         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2485         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2486
2487         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2488         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2489
2490         /* Invalidate L2IMEM. */
2491         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2492
2493         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2494          * Program BootCode location and size in system memory.
2495          */
2496         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2497                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2498                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2499         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2500                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2501                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2502         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2503
2504         /* Trigger L2IMEM Load operation. */
2505         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2506
2507         /* Setup Falcon Auto-fill */
2508         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2509         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2510                 nblocks += 1;
2511         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2512
2513         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2514         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2515                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2516         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2517
2518         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2519         msleep(50);
2520
2521         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2522
2523         /* Start Falcon CPU */
2524         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2525         usleep_range(1000, 2000);
2526
2527         fw_time = cfg_tbl->fwimg_created_time;
2528         time_to_tm(fw_time, 0, &fw_tm);
2529         dev_info(&pdev->dev,
2530                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2531                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2532                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2533                 fw_tm.tm_min, fw_tm.tm_sec,
2534                 csb_read(tegra, XUSB_FALC_CPUCTL));
2535
2536         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2537
2538         /* return fail if firmware status is not good */
2539         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2540                 return -EFAULT;
2541
2542         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2543         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2544         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2545
2546         /* wait for USBSTS_CNR to get set */
2547         do {
2548                 usbsts = ioread32(&op_regs->status);
2549         } while ((usbsts & STS_CNR) && count--);
2550
2551         if (!count && (usbsts & STS_CNR)) {
2552                 dev_err(&pdev->dev, "Controller not ready\n");
2553                 return -EFAULT;
2554         }
2555
2556         return 0;
2557 }
2558
2559 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2560         bool release)
2561 {
2562         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2563         u32 reg;
2564
2565         /* Issue is only applicable for T114 */
2566         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2567                 return;
2568
2569         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2570         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2571                         USB2_OTG_PAD_PORT_MASK(2));
2572
2573         if (!release) {
2574                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2575                         if (is_otg_host(tegra))
2576                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2577                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2578                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2579                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2580                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2581         }
2582
2583         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2584 }
2585 /* SS ELPG Entry initiated by fw */
2586 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2587 {
2588         struct xhci_hcd *xhci = tegra->xhci;
2589         u32 ret = 0;
2590
2591         must_have_sync_lock(tegra);
2592
2593         /* update maximum BW requirement to 0 */
2594         tegra_xusb_set_bw(tegra, 0);
2595
2596         /* This is SS partition ELPG entry
2597          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2598          */
2599
2600         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2601          * only if it is sw initiated one
2602          */
2603
2604         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2605          * SuperSpeed partition ELPG entry via mailbox protocol
2606          */
2607
2608         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2609          * enable the XUSB wakeup interrupts for the SuperSpeed
2610          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2611          */
2612         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2613
2614         /* STEP 3: xHCI PEP driver initiates the signal sequence
2615          * to enable the XUSB SSwake detection logic for the
2616          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2617          */
2618         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2619
2620         /* STEP 4: System Power Management driver asserts reset
2621          * to XUSB SuperSpeed partition then disables its clocks
2622          */
2623         tegra_periph_reset_assert(tegra->ss_clk);
2624         clk_disable(tegra->ss_clk);
2625
2626         usleep_range(100, 200);
2627
2628         /* STEP 5: System Power Management driver disables the
2629          * XUSB SuperSpeed partition power rails.
2630          */
2631         debug_print_portsc(xhci);
2632
2633         /* tegra_powergate_partition also does partition reset assert */
2634         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2635         if (ret) {
2636                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2637                                 __func__);
2638                 /* TODO: error recovery? */
2639         }
2640         tegra->ss_pwr_gated = true;
2641
2642         /* STEP 6: xHCI PEP driver initiates the signal sequence
2643          * to enable the XUSB SSwake detection logic for the
2644          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2645          */
2646         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2647
2648         return ret;
2649 }
2650
2651 /* Host ELPG Entry */
2652 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2653 {
2654         struct xhci_hcd *xhci = tegra->xhci;
2655         u32 ret;
2656
2657         must_have_sync_lock(tegra);
2658
2659         /* If ss is already powergated skip ss ctx save stuff */
2660         if (tegra->ss_pwr_gated) {
2661                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2662                         __func__);
2663         } else {
2664                 ret = tegra_xhci_ss_elpg_entry(tegra);
2665                 if (ret) {
2666                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2667                                 __func__, ret);
2668                         return ret;
2669                 }
2670         }
2671
2672         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2673
2674         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2675         tegra_xhci_save_xusb_ctx(tegra);
2676
2677         /* calculate rctrl_val and tctrl_val */
2678         tegra_xhci_war_for_tctrl_rctrl(tegra);
2679
2680         pmc_setup_wake_detect(tegra);
2681
2682         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2683         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2684                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2685
2686         /* tegra_powergate_partition also does partition reset assert */
2687         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2688         if (ret) {
2689                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2690                         __func__, ret);
2691                 /* TODO: error handling? */
2692                 return ret;
2693         }
2694         tegra->host_pwr_gated = true;
2695         clk_disable(tegra->host_clk);
2696
2697         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2698                 clk_disable(tegra->pll_re_vco_clk);
2699         clk_disable(tegra->emc_clk);
2700         /* set port ownership to SNPS */
2701         tegra_xhci_release_port_ownership(tegra, true);
2702
2703         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2704                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2705
2706         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2707         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2708                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2709         return ret;
2710 }
2711
2712 /* SS ELPG Exit triggered by PADCTL irq */
2713 /**
2714  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2715  *
2716  * This function must be called with tegra->sync_lock acquired.
2717  *
2718  * @tegra: xhci controller context
2719  * @return 0 for success, or error numbers
2720  */
2721 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2722 {
2723         struct xhci_hcd *xhci = tegra->xhci;
2724         int ret = 0;
2725
2726         must_have_sync_lock(tegra);
2727
2728         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2729                         tegra->hs_wake_event || tegra->host_resume_req)) {
2730
2731                 /*
2732                  * PWR_UNGATE SS partition. XUSBA
2733                  * tegra_unpowergate_partition also does partition reset
2734                  * deassert
2735                  */
2736                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2737                 if (ret) {
2738                         xhci_err(xhci,
2739                         "%s: could not unpowergate xusba partition %d\n",
2740                         __func__, ret);
2741                         goto out;
2742                 }
2743                 if (tegra->ss_wake_event)
2744                         tegra->ss_wake_event = false;
2745
2746         } else {
2747                 xhci_info(xhci, "%s: ss already power gated\n",
2748                         __func__);
2749                 return ret;
2750         }
2751
2752         /* Step 3: Enable clock to ss partition */
2753         clk_enable(tegra->ss_clk);
2754
2755         /* Step 4: Disable ss wake detection logic */
2756         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2757
2758         /* Step 4.1: Disable ss wake detection logic */
2759         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2760
2761         /* wait 150us */
2762         usleep_range(150, 200);
2763
2764         /* Step 4.2: Disable ss wake detection logic */
2765         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2766
2767         /* Step 6 Deassert reset for ss clks */
2768         tegra_periph_reset_deassert(tegra->ss_clk);
2769
2770         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2771         tegra->ss_pwr_gated = false;
2772 out:
2773         return ret;
2774 }
2775
2776 static void ss_partition_elpg_exit_work(struct work_struct *work)
2777 {
2778         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2779                 ss_elpg_exit_work);
2780
2781         mutex_lock(&tegra->sync_lock);
2782         tegra_xhci_ss_partition_elpg_exit(tegra);
2783         mutex_unlock(&tegra->sync_lock);
2784 }
2785
2786 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2787 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2788 {
2789         struct xhci_hcd *xhci = tegra->xhci;
2790         u32 wake2_status;
2791         int port;
2792
2793 #define PMC_WAKE2_STATUS        0x168
2794 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2795
2796         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2797
2798         if (wake2_status & PADCTL_WAKE) {
2799                 /* FIXME: This is customized for Dalmore, find a generic way */
2800                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2801                 /* clear wake status */
2802                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2803         }
2804
2805         /* set all usb2 ports with RESUME link state as wakup ports  */
2806         for (port = 0; port < xhci->num_usb2_ports; port++) {
2807                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2808                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2809                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2810         }
2811
2812         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2813                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2814         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2815                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2816 }
2817
2818 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2819 {
2820         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2821         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2822         int port, num_ports;
2823         unsigned long *remote_wakeup_ports;
2824         u32 portsc;
2825         __le32 __iomem  **port_array;
2826         unsigned char *rh;
2827         unsigned int retry = 64;
2828         struct xhci_bus_state *bus_state;
2829
2830         bus_state = &xhci->bus_state[hcd_index(hcd)];
2831
2832         if (hcd == xhci->shared_hcd) {
2833                 port_array = xhci->usb3_ports;
2834                 num_ports = xhci->num_usb3_ports;
2835                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2836                 rh = "usb3 roothub";
2837         } else {
2838                 port_array = xhci->usb2_ports;
2839                 num_ports = xhci->num_usb2_ports;
2840                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2841                 rh = "usb2 roothub";
2842         }
2843
2844         while (*remote_wakeup_ports && retry--) {
2845                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2846                         bool can_continue;
2847
2848                         portsc = xhci_readl(xhci, port_array[port]);
2849
2850                         if (!(portsc & PORT_CONNECT)) {
2851                                 /* nothing to do if already disconnected */
2852                                 clear_bit(port, remote_wakeup_ports);
2853                                 continue;
2854                         }
2855
2856                         if (hcd == xhci->shared_hcd) {
2857                                 can_continue =
2858                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2859                         } else {
2860                                 unsigned long flags;
2861
2862                                 spin_lock_irqsave(&xhci->lock, flags);
2863                                 can_continue =
2864                                 test_bit(port, &bus_state->resuming_ports);
2865                                 spin_unlock_irqrestore(&xhci->lock, flags);
2866                         }
2867
2868                         if (can_continue)
2869                                 clear_bit(port, remote_wakeup_ports);
2870                         else
2871                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2872                                         __func__, rh, port, portsc);
2873                 }
2874
2875                 if (*remote_wakeup_ports)
2876                         msleep(20); /* give some time, irq will direct U0 */
2877         }
2878
2879         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2880                         *remote_wakeup_ports);
2881 }
2882
2883 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2884 {
2885         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2886         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2887
2888         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2889         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2890                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2891
2892         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2893                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2894                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2895         }
2896
2897         /* Use xusb padctl space only when xusb owns all UTMIP port */
2898         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2899         if ((pad_mux & portmux) == portowner) {
2900                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2901                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2902                  */
2903                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2904                 reg &= ~((1 << 12) | (1 << 13));
2905                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2906
2907                 /* wait 20us */
2908                 usleep_range(20, 30);
2909
2910                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2911                  * :: TCTRL and RCTRL
2912                  */
2913                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2914                 utmip_rctrl_val = RCTRL(reg);
2915                 utmip_tctrl_val = TCTRL(reg);
2916
2917                 /*
2918                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2919                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2920                  */
2921                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2922                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2923                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2924                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2925                                         utmip_rctrl_val, utmip_tctrl_val);
2926
2927                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2928                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2929                  */
2930                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2931                 reg |= (1 << 13);
2932                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2933
2934                 /* Program these values into PMC regiseter and program the
2935                  * PMC override.
2936                  */
2937                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2938                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2939                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2940                                         0xffffffff, reg);
2941                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2942                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2943         } else {
2944                 /* Use common PMC API to use SNPS register space */
2945                 utmi_phy_set_snps_trking_data();
2946         }
2947 }
2948
2949 /* Host ELPG Exit triggered by PADCTL irq */
2950 /**
2951  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2952  *
2953  * This function must be called with tegra->sync_lock acquired.
2954  *
2955  * @tegra: xhci controller context
2956  * @return 0 for success, or error numbers
2957  */
2958 static int
2959 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2960 {
2961         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2962         struct xhci_hcd *xhci = tegra->xhci;
2963         int ret = 0;
2964
2965         must_have_sync_lock(tegra);
2966
2967         if (!tegra->hc_in_elpg)
2968                 return 0;
2969
2970         clk_enable(tegra->emc_clk);
2971         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2972                 clk_enable(tegra->pll_re_vco_clk);
2973
2974         if (tegra->lp0_exit) {
2975                 u32 reg, oc_bits = 0;
2976
2977                 /* Issue is only applicable for T114 */
2978                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2979                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2980                 /* check if over current seen. Clear if present */
2981                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2982                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2983                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2984                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2985                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2986                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2987
2988                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2989                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2990                 if (reg & oc_bits) {
2991                         xhci_info(xhci, "Over current detected. Clearing...\n");
2992                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2993
2994                         usleep_range(100, 200);
2995
2996                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2997                         if (reg & oc_bits)
2998                                 xhci_info(xhci, "Over current still present\n");
2999                 }
3000                 tegra_xhci_padctl_portmap_and_caps(tegra);
3001                 /* release clamps post deassert */
3002                 tegra->lp0_exit = false;
3003         }
3004
3005         /* Clear FLUSH_ENABLE of MC client */
3006         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
3007
3008         /* set port ownership back to xusb */
3009         tegra_xhci_release_port_ownership(tegra, false);
3010
3011         /*
3012          * PWR_UNGATE Host partition. XUSBC
3013          * tegra_unpowergate_partition also does partition reset deassert
3014          */
3015         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3016         if (ret) {
3017                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3018                         __func__, ret);
3019                 goto out;
3020         }
3021         clk_enable(tegra->host_clk);
3022
3023         /* Step 4: Deassert reset to host partition clk */
3024         tegra_periph_reset_deassert(tegra->host_clk);
3025
3026         /* Step 6.1: IPFS and XUSB BAR initialization */
3027         tegra_xhci_cfg(tegra);
3028
3029         /* Step 6.2: IPFS and XUSB related restore */
3030         tegra_xhci_restore_ctx(tegra);
3031
3032         /* Step 8: xhci spec related ctx restore
3033          * will be done in xhci_resume().Do it here.
3034          */
3035
3036         tegra_xhci_ss_partition_elpg_exit(tegra);
3037
3038         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3039         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3040                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3041                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3042         }
3043
3044         /* clear ovrd bits */
3045         tegra_xhci_rx_idle_mode_override(tegra, false);
3046
3047         /* Load firmware */
3048         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3049                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3050                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3051                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3052                         __func__,
3053                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3054                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3055                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3056                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3057                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3058                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3059                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3060                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3061                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3062         debug_print_portsc(xhci);
3063
3064         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3065         if (ret < 0) {
3066                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3067                         __func__, ret);
3068                 goto out;
3069         }
3070
3071         pmc_disable_bus_ctrl(tegra);
3072
3073         tegra->hc_in_elpg = false;
3074         ret = xhci_resume(tegra->xhci, 0);
3075         if (ret) {
3076                 xhci_err(xhci, "%s: could not resume right %d\n",
3077                                 __func__, ret);
3078                 goto out;
3079         }
3080
3081         update_remote_wakeup_ports(tegra);
3082
3083         if (tegra->hs_wake_event)
3084                 tegra->hs_wake_event = false;
3085
3086         if (tegra->host_resume_req)
3087                 tegra->host_resume_req = false;
3088
3089         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3090                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3091
3092         tegra->host_pwr_gated = false;
3093 out:
3094         return ret;
3095 }
3096
3097 static void host_partition_elpg_exit_work(struct work_struct *work)
3098 {
3099         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3100                 host_elpg_exit_work);
3101
3102         mutex_lock(&tegra->sync_lock);
3103         tegra_xhci_host_partition_elpg_exit(tegra);
3104         mutex_unlock(&tegra->sync_lock);
3105 }
3106
3107 /* Mailbox handling function. This function handles requests
3108  * from firmware and communicates with clock and powergating
3109  * module to alter clock rates and to power gate/ungate xusb
3110  * partitions.
3111  *
3112  * Following is the structure of mailbox messages.
3113  * bit 31:28 - msg type
3114  * bits 27:0 - mbox data
3115  * FIXME:  Check if we can just call clock functions like below
3116  * or should we schedule it for calling later ?
3117  */
3118
3119 static void
3120 tegra_xhci_process_mbox_message(struct work_struct *work)
3121 {
3122         u32 sw_resp = 0, cmd, data_in, fw_msg;
3123         int ret = 0;
3124         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3125                                         mbox_work);
3126         struct xhci_hcd *xhci = tegra->xhci;
3127         int pad, port;
3128         unsigned long ports;
3129
3130         mutex_lock(&tegra->mbox_lock);
3131
3132         /* get the mbox message from firmware */
3133         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3134
3135         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3136         if (data_in) {
3137                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3138                         __func__, data_in);
3139                 mutex_unlock(&tegra->mbox_lock);
3140                 return;
3141         }
3142
3143         /* get cmd type and cmd data */
3144         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3145         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3146
3147         /* decode the message and make appropriate requests to
3148          * clock or powergating module.
3149          */
3150
3151         switch (tegra->cmd_type) {
3152         case MBOX_CMD_INC_FALC_CLOCK:
3153         case MBOX_CMD_DEC_FALC_CLOCK:
3154                 ret = tegra_xusb_request_clk_rate(
3155                                 tegra,
3156                                 tegra->falc_clk,
3157                                 tegra->cmd_data,
3158                                 &sw_resp);
3159                 if (ret)
3160                         xhci_err(xhci, "%s: could not set required falc rate\n",
3161                                 __func__);
3162                 goto send_sw_response;
3163         case MBOX_CMD_INC_SSPI_CLOCK:
3164         case MBOX_CMD_DEC_SSPI_CLOCK:
3165                 ret = tegra_xusb_request_clk_rate(
3166                                 tegra,
3167                                 tegra->ss_src_clk,
3168                                 tegra->cmd_data,
3169                                 &sw_resp);
3170                 if (ret)
3171                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3172                                 __func__);
3173                 goto send_sw_response;
3174
3175         case MBOX_CMD_SET_BW:
3176                 /* fw sends BW request in MByte/sec */
3177                 mutex_lock(&tegra->sync_lock);
3178                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3179                 mutex_unlock(&tegra->sync_lock);
3180                 break;
3181
3182         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3183                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3184                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3185                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3186                 goto send_sw_response;
3187
3188         case MBOX_CMD_STAR_HSIC_IDLE:
3189                 ports = tegra->cmd_data;
3190                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3191                         pad = port_to_hsic_pad(port - 1);
3192                         mutex_lock(&tegra->sync_lock);
3193                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3194                         mutex_unlock(&tegra->sync_lock);
3195                         if (ret)
3196                                 break;
3197                 }
3198
3199                 sw_resp = CMD_DATA(tegra->cmd_data);
3200                 if (!ret)
3201                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3202                 else
3203                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3204
3205                 goto send_sw_response;
3206
3207         case MBOX_CMD_STOP_HSIC_IDLE:
3208                 ports = tegra->cmd_data;
3209                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3210                         pad = port_to_hsic_pad(port - 1);
3211                         mutex_lock(&tegra->sync_lock);
3212                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3213                         mutex_unlock(&tegra->sync_lock);
3214                         if (ret)
3215                                 break;
3216                 }
3217
3218                 sw_resp = CMD_DATA(tegra->cmd_data);
3219                 if (!ret)
3220                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3221                 else
3222                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3223                 goto send_sw_response;
3224
3225         case MBOX_CMD_ACK:
3226                 xhci_dbg(xhci, "%s firmware responds with ACK\n", __func__);
3227                 break;
3228         case MBOX_CMD_NACK:
3229                 xhci_warn(xhci, "%s firmware responds with NACK\n", __func__);
3230                 break;
3231         default:
3232                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3233                                 __func__, tegra->cmd_type);
3234         }
3235
3236         /* clear MBOX_SMI_INT_EN bit */
3237         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3238         cmd &= ~MBOX_SMI_INT_EN;
3239         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3240
3241         /* clear mailbox ownership */
3242         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3243
3244         mutex_unlock(&tegra->mbox_lock);
3245         return;
3246
3247 send_sw_response:
3248         if (((sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK) == MBOX_CMD_NACK)
3249                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3250                                 __func__, fw_msg);
3251
3252         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3253         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3254         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3255         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3256
3257         mutex_unlock(&tegra->mbox_lock);
3258 }
3259
3260 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3261 {
3262         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3263         struct xhci_hcd *xhci = tegra->xhci;
3264
3265         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3266         return IRQ_HANDLED;
3267 }
3268
3269 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3270 {
3271         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3272         struct xhci_hcd *xhci = tegra->xhci;
3273         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3274         u32 elpg_program0 = 0;
3275
3276         spin_lock(&tegra->lock);
3277
3278         tegra->last_jiffies = jiffies;
3279
3280         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3281         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3282
3283         /* Clear the interrupt cause. We already read the intr status. */
3284         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3285         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3286
3287         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3288         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3289                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3290         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3291                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3292         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3293                 __func__,
3294                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3295         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3296                 __func__,
3297                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3298         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3299                 __func__,
3300                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3301
3302         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3303                 tegra->ss_wake_event = true;
3304         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3305                         USB2_PORT1_WAKEUP_EVENT |
3306                         USB2_PORT2_WAKEUP_EVENT |
3307                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3308                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3309                 tegra->hs_wake_event = true;
3310
3311         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3312                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3313                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3314                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3315                 } else if (tegra->ss_pwr_gated
3316                                 && tegra->host_pwr_gated) {
3317                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3318                                 __func__);
3319                         schedule_work(&tegra->host_elpg_exit_work);
3320                 }
3321         } else {
3322                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3323                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3324         }
3325         spin_unlock(&tegra->lock);
3326         return IRQ_HANDLED;
3327 }
3328
3329 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3330 {
3331         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3332         u32 temp;
3333
3334         spin_lock(&tegra->lock);
3335
3336         /* clear the mbox intr status 1st thing. Other
3337          * bits are W1C bits, so just write to SMI bit.
3338          */
3339
3340         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3341
3342         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3343         temp = MBOX_SMI_INTR_EN;
3344         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3345
3346         schedule_work(&tegra->mbox_work);
3347
3348         spin_unlock(&tegra->lock);
3349         return IRQ_HANDLED;
3350 }
3351
3352 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3353 {
3354         /*
3355          * As of now platform drivers don't provide MSI support so we ensure
3356          * here that the generic code does not try to make a pci_dev from our
3357          * dev struct in order to setup MSI
3358          */
3359         xhci->quirks |= XHCI_PLAT;
3360         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3361 }
3362
3363 /* called during probe() after chip reset completes */
3364 static int xhci_plat_setup(struct usb_hcd *hcd)
3365 {
3366         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3367 }
3368
3369 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3370         int num, void __iomem **region)
3371 {
3372         struct resource *res;
3373         void __iomem *mem;
3374
3375         res = platform_get_resource(pdev, IORESOURCE_MEM, num);
3376         if (!res) {
3377                 dev_err(&pdev->dev, "memory resource %d doesn't exist\n", num);
3378                 return -ENODEV;
3379         }
3380
3381         mem = devm_request_and_ioremap(&pdev->dev, res);
3382         if (!mem) {
3383                 dev_err(&pdev->dev, "failed to ioremap for %d\n", num);
3384                 return -EFAULT;
3385         }
3386         *region = mem;
3387
3388         return 0;
3389 }
3390
3391 static int tegra_xhci_request_irq(struct platform_device *pdev,
3392         int num, irq_handler_t handler, unsigned long irqflags,
3393         const char *devname, int *irq_no)
3394 {
3395         int ret;
3396         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3397         struct resource *res;
3398
3399         res = platform_get_resource(pdev, IORESOURCE_IRQ, num);
3400         if (!res) {
3401                 dev_err(&pdev->dev, "irq resource %d doesn't exist\n", num);
3402                 return -ENODEV;
3403         }
3404
3405         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3406                         devname, tegra);
3407         if (ret != 0) {
3408                 dev_err(&pdev->dev,
3409                         "failed to request_irq for %s (irq %d), error = %d\n",
3410                         devname, (int)res->start, ret);
3411                 return ret;
3412         }
3413         *irq_no = res->start;
3414
3415         return 0;
3416 }
3417
3418 #ifdef CONFIG_PM
3419
3420 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3421 {
3422         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3423         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3424         int err = 0;
3425         unsigned long flags;
3426
3427         mutex_lock(&tegra->sync_lock);
3428
3429         if (xhci->shared_hcd == hcd) {
3430                 tegra->usb3_rh_suspend = true;
3431                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3432         } else if (xhci->main_hcd == hcd) {
3433                 tegra->usb2_rh_suspend = true;
3434                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3435         }
3436
3437         WARN_ON(tegra->hc_in_elpg);
3438
3439         /* suspend xhci bus. This will also set remote mask */
3440         err = xhci_bus_suspend(hcd);
3441         if (err) {
3442                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3443                                 __func__, err);
3444                 goto xhci_bus_suspend_failed;
3445         }
3446
3447         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3448                 goto done; /* one of the root hubs is still working */
3449
3450         spin_lock_irqsave(&tegra->lock, flags);
3451         tegra->hc_in_elpg = true;
3452         spin_unlock_irqrestore(&tegra->lock, flags);
3453
3454         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3455
3456         /* save xhci spec ctx. Already done by xhci_suspend */
3457         err = xhci_suspend(tegra->xhci);
3458         if (err) {
3459                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3460                 goto xhci_suspend_failed;
3461         }
3462
3463         /* Powergate host. Include ss power gate if not already done */
3464         err = tegra_xhci_host_elpg_entry(tegra);
3465         if (err) {
3466                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3467                                 __func__, err);
3468                 goto tegra_xhci_host_elpg_entry_failed;
3469         }
3470
3471         /* At this point,ensure ss/hs intr enables are always on */
3472         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3473         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3474
3475         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3476         if (fw_log_wait_empty_timeout(tegra, 100))
3477                 xhci_warn(xhci, "%s still has logs\n", __func__);
3478         tegra->log.dequeue = tegra->log.virt_addr;
3479         tegra->log.seq = 0;
3480
3481 done:
3482         /* pads are disabled only if usb2 root hub in xusb is idle */
3483         /* pads will actually be disabled only when all usb2 ports are idle */
3484         if (xhci->main_hcd == hcd) {
3485                 utmi_phy_pad_disable();
3486                 utmi_phy_iddq_override(true);
3487         }
3488         mutex_unlock(&tegra->sync_lock);
3489         return 0;
3490
3491 tegra_xhci_host_elpg_entry_failed:
3492
3493 xhci_suspend_failed:
3494         tegra->hc_in_elpg = false;
3495 xhci_bus_suspend_failed:
3496         if (xhci->shared_hcd == hcd)
3497                 tegra->usb3_rh_suspend = false;
3498         else if (xhci->main_hcd == hcd)
3499                 tegra->usb2_rh_suspend = false;
3500
3501         mutex_unlock(&tegra->sync_lock);
3502         return err;
3503 }
3504
3505 /* First, USB2HCD and then USB3HCD resume will be called */
3506 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3507 {
3508         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3509         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3510         int err = 0;
3511
3512         mutex_lock(&tegra->sync_lock);
3513
3514         tegra->host_resume_req = true;
3515
3516         if (xhci->shared_hcd == hcd)
3517                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3518         else if (xhci->main_hcd == hcd)
3519                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3520
3521         /* pads are disabled only if usb2 root hub in xusb is idle */
3522         /* pads will actually be disabled only when all usb2 ports are idle */
3523         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3524                 utmi_phy_pad_enable();
3525                 utmi_phy_iddq_override(false);
3526         }
3527         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3528                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3529                         tegra_xhci_host_partition_elpg_exit(tegra);
3530         }
3531
3532          /* handle remote wakeup before resuming bus */
3533         wait_remote_wakeup_ports(hcd);
3534
3535         err = xhci_bus_resume(hcd);
3536         if (err) {
3537                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3538                                 __func__, err);
3539                 goto xhci_bus_resume_failed;
3540         }
3541
3542         if (xhci->shared_hcd == hcd)
3543                 tegra->usb3_rh_suspend = false;
3544         else if (xhci->main_hcd == hcd)
3545                 tegra->usb2_rh_suspend = false;
3546
3547         mutex_unlock(&tegra->sync_lock);
3548         return 0;
3549
3550 xhci_bus_resume_failed:
3551         /* TODO: reverse elpg? */
3552         mutex_unlock(&tegra->sync_lock);
3553         return err;
3554 }
3555 #endif
3556
3557 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3558 {
3559         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3560         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3561         irqreturn_t iret = IRQ_HANDLED;
3562         u32 status;
3563
3564         spin_lock(&tegra->lock);
3565         if (tegra->hc_in_elpg) {
3566                 spin_lock(&xhci->lock);
3567                 if (HCD_HW_ACCESSIBLE(hcd)) {
3568                         status = xhci_readl(xhci, &xhci->op_regs->status);
3569                         status |= STS_EINT;
3570                         xhci_writel(xhci, status, &xhci->op_regs->status);
3571                 }
3572                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3573                                 __func__);
3574                 schedule_work(&tegra->host_elpg_exit_work);
3575                 spin_unlock(&xhci->lock);
3576         } else
3577                 iret = xhci_irq(hcd);
3578         spin_unlock(&tegra->lock);
3579
3580         wake_up_interruptible(&tegra->log.intr_wait);
3581
3582         return iret;
3583 }
3584
3585
3586 static const struct hc_driver tegra_plat_xhci_driver = {
3587         .description =          "tegra-xhci",
3588         .product_desc =         "Nvidia xHCI Host Controller",
3589         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3590
3591         /*
3592          * generic hardware linkage
3593          */
3594         .irq =                  tegra_xhci_irq,
3595         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3596
3597         /*
3598          * basic lifecycle operations
3599          */
3600         .reset =                xhci_plat_setup,
3601         .start =                xhci_run,
3602         .stop =                 xhci_stop,
3603         .shutdown =             xhci_shutdown,
3604
3605         /*
3606          * managing i/o requests and associated device resources
3607          */
3608         .urb_enqueue =          xhci_urb_enqueue,
3609         .urb_dequeue =          xhci_urb_dequeue,
3610         .alloc_dev =            xhci_alloc_dev,
3611         .free_dev =             xhci_free_dev,
3612         .alloc_streams =        xhci_alloc_streams,
3613         .free_streams =         xhci_free_streams,
3614         .add_endpoint =         xhci_add_endpoint,
3615         .drop_endpoint =        xhci_drop_endpoint,
3616         .endpoint_reset =       xhci_endpoint_reset,
3617         .check_bandwidth =      xhci_check_bandwidth,
3618         .reset_bandwidth =      xhci_reset_bandwidth,
3619         .address_device =       xhci_address_device,
3620         .update_hub_device =    xhci_update_hub_device,
3621         .reset_device =         xhci_discover_or_reset_device,
3622
3623         /*
3624          * scheduling support
3625          */
3626         .get_frame_number =     xhci_get_frame,
3627
3628         /* Root hub support */
3629         .hub_control =          xhci_hub_control,
3630         .hub_status_data =      xhci_hub_status_data,
3631
3632 #ifdef CONFIG_PM
3633         .bus_suspend =          tegra_xhci_bus_suspend,
3634         .bus_resume =           tegra_xhci_bus_resume,
3635 #endif
3636 };
3637
3638 #ifdef CONFIG_PM
3639 static int
3640 tegra_xhci_suspend(struct platform_device *pdev,
3641                                                 pm_message_t state)
3642 {
3643         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3644         struct xhci_hcd *xhci = tegra->xhci;
3645
3646         int ret = 0;
3647
3648         mutex_lock(&tegra->sync_lock);
3649         if (!tegra->init_done) {
3650                 xhci_warn(xhci, "%s: xhci probe not done\n",
3651                                 __func__);
3652                 mutex_unlock(&tegra->sync_lock);
3653                 return -EBUSY;
3654         }
3655         if (!tegra->hc_in_elpg) {
3656                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3657                                 __func__);
3658                 mutex_unlock(&tegra->sync_lock);
3659                 return -EBUSY;
3660         }
3661         mutex_unlock(&tegra->sync_lock);
3662
3663         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3664         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3665
3666         /* enable_irq_wake for ss ports */
3667         ret = enable_irq_wake(tegra->padctl_irq);
3668         if (ret < 0) {
3669                 xhci_err(xhci,
3670                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3671                 __func__, tegra->padctl_irq, ret);
3672         }
3673
3674         /* enable_irq_wake for utmip/uhisc wakes */
3675         ret = enable_irq_wake(tegra->usb3_irq);
3676         if (ret < 0) {
3677                 xhci_err(xhci,
3678                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3679                 __func__, tegra->usb3_irq, ret);
3680         }
3681
3682         /* enable_irq_wake for utmip/uhisc wakes */
3683         ret = enable_irq_wake(tegra->usb2_irq);
3684         if (ret < 0) {
3685                 xhci_err(xhci,
3686                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3687                 __func__, tegra->usb2_irq, ret);
3688         }
3689
3690         regulator_disable(tegra->xusb_s1p8v_reg);
3691         regulator_disable(tegra->xusb_s1p05v_reg);
3692         tegra_usb2_clocks_deinit(tegra);
3693
3694         return ret;
3695 }
3696
3697 static int
3698 tegra_xhci_resume(struct platform_device *pdev)
3699 {
3700         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3701         struct xhci_hcd *xhci = tegra->xhci;
3702
3703         dev_dbg(&pdev->dev, "%s\n", __func__);
3704
3705         mutex_lock(&tegra->sync_lock);
3706         if (!tegra->init_done) {
3707                 xhci_warn(xhci, "%s: xhci probe not done\n",
3708                                 __func__);
3709                 mutex_unlock(&tegra->sync_lock);
3710                 return -EBUSY;
3711         }
3712         mutex_unlock(&tegra->sync_lock);
3713
3714         tegra->last_jiffies = jiffies;
3715
3716         disable_irq_wake(tegra->padctl_irq);
3717         disable_irq_wake(tegra->usb3_irq);
3718         disable_irq_wake(tegra->usb2_irq);
3719         tegra->lp0_exit = true;
3720
3721         regulator_enable(tegra->xusb_s1p05v_reg);
3722         regulator_enable(tegra->xusb_s1p8v_reg);
3723         tegra_usb2_clocks_init(tegra);
3724
3725         return 0;
3726 }
3727 #endif
3728
3729
3730 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3731 {
3732         struct platform_device *pdev = tegra->pdev;
3733         void __iomem *fw_mmio_base;
3734         phys_addr_t fw_mem_phy_addr;
3735         size_t fw_size;
3736         dma_addr_t fw_dma;
3737 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3738         int ret;
3739         DEFINE_DMA_ATTRS(attrs);
3740 #endif
3741
3742         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3743         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3744
3745         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3746                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3747
3748         if (!fw_mmio_base) {
3749                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3750                                         (u32)fw_mem_phy_addr);
3751                         return -ENOMEM;
3752         }
3753
3754         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3755         devm_iounmap(&pdev->dev, fw_mmio_base);
3756
3757         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3758                         fw_mem_phy_addr, fw_size);
3759         if (!fw_mmio_base) {
3760                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3761                                         (u32)fw_mem_phy_addr);
3762                         return -ENOMEM;
3763         }
3764
3765         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3766                         (u32) fw_mem_phy_addr, fw_mmio_base, fw_size);
3767
3768 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3769         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3770         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3771                         DMA_TO_DEVICE, &attrs);
3772
3773         if (fw_dma == DMA_ERROR_CODE) {
3774                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3775                                 __func__);
3776                 ret = -ENOMEM;
3777                 goto error_iounmap;
3778         }
3779 #else
3780         fw_dma = fw_mem_phy_addr;
3781 #endif
3782         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3783                         (void *) fw_dma, fw_size);
3784
3785         /* all set and ready to go */
3786         tegra->firmware.data = fw_mmio_base;
3787         tegra->firmware.dma = fw_dma;
3788         tegra->firmware.size = fw_size;
3789
3790         return 0;
3791
3792 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3793 error_iounmap:
3794         devm_iounmap(&pdev->dev, fw_mmio_base);
3795         return ret;
3796 #endif
3797 }
3798
3799 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3800 {
3801         struct platform_device *pdev = tegra->pdev;
3802         void __iomem *fw_mmio_base = tegra->firmware.data;
3803
3804 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3805         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3806                         tegra->firmware.size, DMA_TO_DEVICE);
3807 #endif
3808         devm_iounmap(&pdev->dev, fw_mmio_base);
3809
3810         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3811 }
3812
3813 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3814 {
3815         struct platform_device *pdev = tegra->pdev;
3816         int ret;
3817
3818         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
3819                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
3820         if (ret < 0) {
3821                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
3822                 return ret;
3823         }
3824
3825         return ret;
3826 }
3827
3828 static void init_filesystem_firmware_done(const struct firmware *fw,
3829                                         void *context)
3830 {
3831         struct tegra_xhci_hcd *tegra = context;
3832         struct platform_device *pdev = tegra->pdev;
3833         struct cfgtbl *fw_cfgtbl;
3834         size_t fw_size;
3835         void *fw_data;
3836         dma_addr_t fw_dma;
3837         int ret;
3838
3839         mutex_lock(&tegra->sync_lock);
3840
3841         if (fw == NULL) {
3842                 dev_err(&pdev->dev,
3843                         "failed to init firmware from filesystem: %s\n",
3844                         firmware_file);
3845                 goto err_firmware_done;
3846         }
3847
3848         fw_cfgtbl = (struct cfgtbl *) fw->data;
3849         fw_size = fw_cfgtbl->fwimg_len;
3850         dev_info(&pdev->dev, "Firmware File: %s (%d Bytes)\n",
3851                         firmware_file, fw_size);
3852
3853         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
3854                         &fw_dma, GFP_KERNEL);
3855         if (!fw_data) {
3856                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
3857                         __func__);
3858                 goto err_firmware_done;
3859         }
3860
3861         memcpy(fw_data, fw->data, fw_size);
3862         dev_info(&pdev->dev,
3863                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%d Bytes)\n",
3864                 (void *) fw_dma, fw_data, fw_size);
3865
3866         /* all set and ready to go */
3867         tegra->firmware.data = fw_data;
3868         tegra->firmware.dma = fw_dma;
3869         tegra->firmware.size = fw_size;
3870
3871         ret = tegra_xhci_probe2(tegra);
3872         if (ret < 0) {
3873                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
3874                 goto err_firmware_done;
3875         }
3876
3877         release_firmware(fw);
3878         mutex_unlock(&tegra->sync_lock);
3879         return;
3880
3881 err_firmware_done:
3882         release_firmware(fw);
3883         mutex_unlock(&tegra->sync_lock);
3884         tegra_xhci_remove(pdev);
3885 }
3886
3887 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3888 {
3889         struct platform_device *pdev = tegra->pdev;
3890
3891         if (tegra->firmware.data) {
3892                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
3893                         tegra->firmware.data, tegra->firmware.dma);
3894         }
3895
3896         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3897 }
3898 static int init_firmware(struct tegra_xhci_hcd *tegra)
3899 {
3900         if (use_bootloader_firmware)
3901                 return init_bootloader_firmware(tegra);
3902         else
3903                 return init_filesystem_firmware(tegra);
3904 }
3905
3906 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3907 {
3908         if (use_bootloader_firmware)
3909                 return deinit_bootloader_firmware(tegra);
3910         else
3911                 return deinit_filesystem_firmware(tegra);
3912 }
3913
3914 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3915                 struct platform_device *pdev)
3916 {
3917         int err = 0;
3918         /* enable ss clock */
3919         err = clk_enable(tegra->host_clk);
3920         if (err) {
3921                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3922                 goto enable_host_clk_failed;
3923         }
3924
3925         err = clk_enable(tegra->ss_clk);
3926         if (err) {
3927                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3928                 goto eanble_ss_clk_failed;
3929         }
3930
3931         err = clk_enable(tegra->emc_clk);
3932         if (err) {
3933                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3934                 goto eanble_emc_clk_failed;
3935         }
3936
3937         return 0;
3938
3939 eanble_emc_clk_failed:
3940         clk_disable(tegra->ss_clk);
3941
3942 eanble_ss_clk_failed:
3943         clk_disable(tegra->host_clk);
3944
3945 enable_host_clk_failed:
3946         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3947                 clk_disable(tegra->pll_re_vco_clk);
3948         return err;
3949 }
3950
3951 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3952         .boot_media_0                   = 0x0,
3953         .usb2_pad_mux_0                 = 0x4,
3954         .usb2_port_cap_0                = 0x8,
3955         .snps_oc_map_0                  = 0xc,
3956         .usb2_oc_map_0                  = 0x10,
3957         .ss_port_map_0                  = 0x14,
3958         .oc_det_0                       = 0x18,
3959         .elpg_program_0                 = 0x1c,
3960         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3961         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3962         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3963         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3964         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3965         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3966         .usb2_bchrg_bias_pad_0          = 0x28,
3967         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3968         .iophy_pll_p0_ctl1_0            = 0x30,
3969         .iophy_pll_p0_ctl2_0            = 0x34,
3970         .iophy_pll_p0_ctl3_0            = 0x38,
3971         .iophy_pll_p0_ctl4_0            = 0x3c,
3972         .iophy_usb3_pad0_ctl1_0         = 0x40,
3973         .iophy_usb3_pad1_ctl1_0         = 0x44,
3974         .iophy_usb3_pad0_ctl2_0         = 0x48,
3975         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3976         .iophy_usb3_pad0_ctl3_0         = 0x50,
3977         .iophy_usb3_pad1_ctl3_0         = 0x54,
3978         .iophy_usb3_pad0_ctl4_0         = 0x58,
3979         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3980         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3981         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3982         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3983         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3984         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3985         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3986         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3987         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3988         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3989         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3990         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3991         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3992         .usb2_otg_pad0_ctl0_0           = 0x90,
3993         .usb2_otg_pad1_ctl0_0           = 0x94,
3994         .usb2_otg_pad2_ctl0_0           = 0xffff,
3995         .usb2_otg_pad0_ctl1_0           = 0x98,
3996         .usb2_otg_pad1_ctl1_0           = 0x9c,
3997         .usb2_otg_pad2_ctl1_0           = 0xffff,
3998         .usb2_bias_pad_ctl0_0           = 0xa0,
3999         .usb2_bias_pad_ctl1_0           = 0xa4,
4000         .usb2_hsic_pad0_ctl0_0          = 0xa8,
4001         .usb2_hsic_pad1_ctl0_0          = 0xac,
4002         .usb2_hsic_pad0_ctl1_0          = 0xb0,
4003         .usb2_hsic_pad1_ctl1_0          = 0xb4,
4004         .usb2_hsic_pad0_ctl2_0          = 0xb8,
4005         .usb2_hsic_pad1_ctl2_0          = 0xbc,
4006         .ulpi_link_trim_ctl0            = 0xc0,
4007         .ulpi_null_clk_trim_ctl0        = 0xc4,
4008         .hsic_strb_trim_ctl0            = 0xc8,
4009         .wake_ctl0                      = 0xcc,
4010         .pm_spare0                      = 0xd0,
4011         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
4012         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
4013         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
4014         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
4015         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
4016         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
4017         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
4018         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
4019         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
4020         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
4021         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
4022         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
4023         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
4024         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
4025         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
4026         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
4027         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
4028         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
4029         .usb3_pad_mux_0                 = 0xffff,
4030         .iophy_pll_s0_ctl1_0            = 0xffff,
4031         .iophy_pll_s0_ctl2_0            = 0xffff,
4032         .iophy_pll_s0_ctl3_0            = 0xffff,
4033         .iophy_pll_s0_ctl4_0            = 0xffff,
4034         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
4035         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
4036         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
4037         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
4038         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
4039         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
4040 };
4041
4042 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
4043         .boot_media_0                   = 0x0,
4044         .usb2_pad_mux_0                 = 0x4,
4045         .usb2_port_cap_0                = 0x8,
4046         .snps_oc_map_0                  = 0xc,
4047         .usb2_oc_map_0                  = 0x10,
4048         .ss_port_map_0                  = 0x14,
4049         .oc_det_0                       = 0x18,
4050         .elpg_program_0                 = 0x1c,
4051         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
4052         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
4053         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
4054         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
4055         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
4056         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
4057         .usb2_bchrg_bias_pad_0          = 0x38,
4058         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
4059         .iophy_pll_p0_ctl1_0            = 0x40,
4060         .iophy_pll_p0_ctl2_0            = 0x44,
4061         .iophy_pll_p0_ctl3_0            = 0x48,
4062         .iophy_pll_p0_ctl4_0            = 0x4c,
4063         .iophy_usb3_pad0_ctl1_0         = 0x50,
4064         .iophy_usb3_pad1_ctl1_0         = 0x54,
4065         .iophy_usb3_pad0_ctl2_0         = 0x58,
4066         .iophy_usb3_pad1_ctl2_0         = 0x5c,
4067         .iophy_usb3_pad0_ctl3_0         = 0x60,
4068         .iophy_usb3_pad1_ctl3_0         = 0x64,
4069         .iophy_usb3_pad0_ctl4_0         = 0x68,
4070         .iophy_usb3_pad1_ctl4_0         = 0x6c,
4071         .iophy_misc_pad_p0_ctl1_0       = 0x70,
4072         .iophy_misc_pad_p1_ctl1_0       = 0x74,
4073         .iophy_misc_pad_p0_ctl2_0       = 0x78,
4074         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
4075         .iophy_misc_pad_p0_ctl3_0       = 0x80,
4076         .iophy_misc_pad_p1_ctl3_0       = 0x84,
4077         .iophy_misc_pad_p0_ctl4_0       = 0x88,
4078         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
4079         .iophy_misc_pad_p0_ctl5_0       = 0x90,
4080         .iophy_misc_pad_p1_ctl5_0       = 0x94,
4081         .iophy_misc_pad_p0_ctl6_0       = 0x98,
4082         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
4083         .usb2_otg_pad0_ctl0_0           = 0xa0,
4084         .usb2_otg_pad1_ctl0_0           = 0xa4,
4085         .usb2_otg_pad2_ctl0_0           = 0xa8,
4086         .usb2_otg_pad0_ctl1_0           = 0xac,
4087         .usb2_otg_pad1_ctl1_0           = 0xb0,
4088         .usb2_otg_pad2_ctl1_0           = 0xb4,
4089         .usb2_bias_pad_ctl0_0           = 0xb8,
4090         .usb2_bias_pad_ctl1_0           = 0xbc,
4091         .usb2_hsic_pad0_ctl0_0          = 0xc0,
4092         .usb2_hsic_pad1_ctl0_0          = 0xc4,
4093         .usb2_hsic_pad0_ctl1_0          = 0xc8,
4094         .usb2_hsic_pad1_ctl1_0          = 0xcc,
4095         .usb2_hsic_pad0_ctl2_0          = 0xd0,
4096         .usb2_hsic_pad1_ctl2_0          = 0xd4,
4097         .ulpi_link_trim_ctl0            = 0xd8,
4098         .ulpi_null_clk_trim_ctl0        = 0xdc,
4099         .hsic_strb_trim_ctl0            = 0xe0,
4100         .wake_ctl0                      = 0xe4,
4101         .pm_spare0                      = 0xe8,
4102         .iophy_misc_pad_p2_ctl1_0       = 0xec,
4103         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
4104         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
4105         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
4106         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
4107         .iophy_misc_pad_p4_ctl2_0       = 0x100,
4108         .iophy_misc_pad_p2_ctl3_0       = 0x104,
4109         .iophy_misc_pad_p3_ctl3_0       = 0x108,
4110         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
4111         .iophy_misc_pad_p2_ctl4_0       = 0x110,
4112         .iophy_misc_pad_p3_ctl4_0       = 0x114,
4113         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4114         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4115         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4116         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4117         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4118         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4119         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4120         .usb3_pad_mux_0                 = 0x134,
4121         .iophy_pll_s0_ctl1_0            = 0x138,
4122         .iophy_pll_s0_ctl2_0            = 0x13c,
4123         .iophy_pll_s0_ctl3_0            = 0x140,
4124         .iophy_pll_s0_ctl4_0            = 0x144,
4125         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4126         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4127         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4128         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4129         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4130         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4131 };
4132
4133 /* FIXME: using notifier to transfer control to host from suspend
4134  * for otg port when xhci is in elpg. Find  better alternative
4135  */
4136 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4137                                    unsigned long event, void *unused)
4138 {
4139         struct tegra_xhci_hcd *tegra = container_of(nb,
4140                                         struct tegra_xhci_hcd, otgnb);
4141
4142         if ((event == USB_EVENT_ID))
4143                 if (tegra->hc_in_elpg) {
4144                         schedule_work(&tegra->host_elpg_exit_work);
4145                         tegra->host_resume_req = true;
4146         }
4147
4148         return NOTIFY_OK;
4149 }
4150
4151 static void tegra_xusb_read_board_data(struct tegra_xhci_hcd *tegra)
4152 {
4153         struct tegra_xusb_board_data *bdata = tegra->bdata;
4154         struct device_node *node = tegra->pdev->dev.of_node;
4155         int ret;
4156
4157         bdata->uses_external_pmic = of_property_read_bool(node,
4158                                         "nvidia,uses_external_pmic");
4159         bdata->gpio_controls_muxed_ss_lanes = of_property_read_bool(node,
4160                                         "nvidia,gpio_controls_muxed_ss_lanes");
4161         ret = of_property_read_u32(node, "nvidia,gpio_ss1_sata",
4162                                         &bdata->gpio_ss1_sata);
4163         ret = of_property_read_u32(node, "nvidia,portmap",
4164                                         &bdata->portmap);
4165         ret = of_property_read_u8(node, "nvidia,ss_portmap",
4166                                         &bdata->ss_portmap);
4167         ret = of_property_read_u8(node, "nvidia,lane_owner",
4168                                         &bdata->lane_owner);
4169         ret = of_property_read_u8(node, "nvidia,ulpicap",
4170                                         &bdata->ulpicap);
4171         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4172                                         0, &bdata->supply.utmi_vbuses[0]);
4173         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4174                                         1, &bdata->supply.utmi_vbuses[1]);
4175         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4176                                         2, &bdata->supply.utmi_vbuses[2]);
4177         ret = of_property_read_string(node, "nvidia,supply_s3p3v",
4178                                         &bdata->supply.s3p3v);
4179         ret = of_property_read_string(node, "nvidia,supply_s1p8v",
4180                                         &bdata->supply.s1p8v);
4181         ret = of_property_read_string(node, "nvidia,supply_vddio_hsic",
4182                                         &bdata->supply.vddio_hsic);
4183         ret = of_property_read_string(node, "nvidia,supply_s1p05v",
4184                                         &bdata->supply.s1p05v);
4185         /* TODO: add read for tegra_xusb_hsic_config
4186          * Add error conditions check
4187          */
4188 }
4189
4190 static void tegra_xusb_read_calib_data(struct tegra_xhci_hcd *tegra)
4191 {
4192         u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
4193         struct tegra_xusb_chip_calib *cdata = tegra->cdata;
4194
4195         pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
4196         /*
4197          * read from usb_calib0 and pass to driver
4198          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
4199          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
4200          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
4201          * set HS_IREF_CAP              = usb_calib0[14:13]
4202          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
4203          */
4204
4205         cdata->hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
4206         cdata->hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
4207         cdata->hs_squelch_level = (usb_calib0 >> 11) & 0x3;
4208         cdata->hs_iref_cap = (usb_calib0 >> 13) & 0x3;
4209         cdata->hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
4210         cdata->hs_curr_level_pad2 = (usb_calib0 >> 15) & 0x3f;
4211 }
4212
4213 static const struct tegra_xusb_soc_config tegra114_soc_config = {
4214         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4215                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 4),
4216         .quirks = TEGRA_XUSB_USE_HS_SRC_CLOCK2,
4217         .rx_wander = (0x3 << 4),
4218         .rx_eq = (0x3928 << 8),
4219         .cdr_cntl = (0x26 << 24),
4220         .dfe_cntl = 0x002008EE,
4221         .hs_slew = (0xE << 6),
4222         .ls_rslew_pad0 = (0x3 << 14),
4223         .ls_rslew_pad1 = (0x0 << 14),
4224         .hs_disc_lvl = (0x5 << 2),
4225         .spare_in = 0x0,
4226 };
4227
4228 static const struct tegra_xusb_soc_config tegra124_soc_config = {
4229         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4230                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
4231                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
4232         .rx_wander = (0xF << 4),
4233         .rx_eq = (0xF070 << 8),
4234         .cdr_cntl = (0x26 << 24),
4235         .dfe_cntl = 0x002008EE,
4236         .hs_slew = (0xE << 6),
4237         .ls_rslew_pad0 = (0x3 << 14),
4238         .ls_rslew_pad1 = (0x0 << 14),
4239         .ls_rslew_pad2 = (0x0 << 14),
4240         .hs_disc_lvl = (0x5 << 2),
4241         .spare_in = 0x1,
4242 };
4243
4244 static struct of_device_id tegra_xhci_of_match[] = {
4245         { .compatible = "nvidia,tegra114-xhci", .data = &tegra114_soc_config },
4246         { .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_config },
4247         { },
4248 };
4249
4250 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4251 static int tegra_xhci_probe(struct platform_device *pdev)
4252 {
4253         struct tegra_xhci_hcd *tegra;
4254         struct resource *res;
4255         unsigned pad;
4256         u32 val;
4257         int ret;
4258         int irq;
4259         const struct tegra_xusb_soc_config *soc_config;
4260         const struct of_device_id *match;
4261
4262         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4263
4264         if (usb_disabled())
4265                 return -ENODEV;
4266
4267         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4268         if (!tegra) {
4269                 dev_err(&pdev->dev, "memory alloc failed\n");
4270                 return -ENOMEM;
4271         }
4272         mutex_init(&tegra->sync_lock);
4273         spin_lock_init(&tegra->lock);
4274         mutex_init(&tegra->mbox_lock);
4275
4276         tegra->init_done = false;
4277
4278         tegra->bdata = devm_kzalloc(&pdev->dev, sizeof(
4279                                         struct tegra_xusb_board_data),
4280                                         GFP_KERNEL);
4281         if (!tegra->bdata) {
4282                 dev_err(&pdev->dev, "memory alloc failed\n");
4283                 return -ENOMEM;
4284         }
4285         tegra->cdata = devm_kzalloc(&pdev->dev, sizeof(
4286                                         struct tegra_xusb_chip_calib),
4287                                         GFP_KERNEL);
4288         if (!tegra->cdata) {
4289                 dev_err(&pdev->dev, "memory alloc failed\n");
4290                 return -ENOMEM;
4291         }
4292         match = of_match_device(tegra_xhci_of_match, &pdev->dev);
4293         if (!match) {
4294                 dev_err(&pdev->dev, "Error: No device match found\n");
4295                 return -ENODEV;
4296         }
4297         soc_config = match->data;
4298         /* Right now device-tree probed devices don't get dma_mask set.
4299          * Since shared usb code relies on it, set it here for now.
4300          * Once we have dma capability bindings this can go away.
4301          */
4302         tegra->tegra_xusb_dmamask = DMA_BIT_MASK(64);
4303         if (!pdev->dev.dma_mask)
4304                 pdev->dev.dma_mask = &tegra->tegra_xusb_dmamask;
4305
4306         tegra->pdev = pdev;
4307         tegra_xusb_read_calib_data(tegra);
4308         tegra_xusb_read_board_data(tegra);
4309         tegra->pdata = dev_get_platdata(&pdev->dev);
4310         tegra->bdata->portmap = tegra->pdata->portmap;
4311         if (tegra->bdata->portmap == NULL)
4312                 return -ENODEV;
4313         tegra->bdata->lane_owner = tegra->pdata->lane_owner;
4314         tegra->soc_config = soc_config;
4315         tegra->ss_pwr_gated = false;
4316         tegra->host_pwr_gated = false;
4317         tegra->hc_in_elpg = false;
4318         tegra->hs_wake_event = false;
4319         tegra->host_resume_req = false;
4320         tegra->lp0_exit = false;
4321
4322         /* request resource padctl base address */
4323         ret = tegra_xhci_request_mem_region(pdev, 3, &tegra->padctl_base);
4324         if (ret) {
4325                 dev_err(&pdev->dev, "failed to map padctl\n");
4326                 return ret;
4327         }
4328
4329         /* request resource fpci base address */
4330         ret = tegra_xhci_request_mem_region(pdev, 1, &tegra->fpci_base);
4331         if (ret) {
4332                 dev_err(&pdev->dev, "failed to map fpci\n");
4333                 return ret;
4334         }
4335
4336         /* request resource ipfs base address */
4337         ret = tegra_xhci_request_mem_region(pdev, 2, &tegra->ipfs_base);
4338         if (ret) {
4339                 dev_err(&pdev->dev, "failed to map ipfs\n");
4340                 return ret;
4341         }
4342
4343         ret = tegra_xusb_partitions_clk_init(tegra);
4344         if (ret) {
4345                 dev_err(&pdev->dev,
4346                         "failed to initialize xusb partitions clocks\n");
4347                 return ret;
4348         }
4349
4350         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4351                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4352                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4353                         dev_err(&pdev->dev, "failed to get usb phy\n");
4354                         tegra->transceiver = NULL;
4355                 }
4356         }
4357
4358         /* Enable power rails to the PAD,VBUS
4359          * and pull-up voltage.Initialize the regulators
4360          */
4361         ret = tegra_xusb_regulator_init(tegra, pdev);
4362         if (ret) {
4363                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4364                 goto err_deinit_xusb_partition_clk;
4365         }
4366
4367         /* Enable UTMIP, PLLU and PLLE */
4368         ret = tegra_usb2_clocks_init(tegra);
4369         if (ret) {
4370                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4371                 goto err_deinit_tegra_xusb_regulator;
4372         }
4373
4374         /* tegra_unpowergate_partition also does partition reset deassert */
4375         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4376         if (ret)
4377                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4378
4379         /* tegra_unpowergate_partition also does partition reset deassert */
4380         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4381         if (ret)
4382                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4383
4384         ret = tegra_enable_xusb_clk(tegra, pdev);
4385         if (ret)
4386                 dev_err(&pdev->dev, "could not enable partition clock\n");
4387
4388         /* reset the pointer back to NULL. driver uses it */
4389         /* platform_set_drvdata(pdev, NULL); */
4390
4391         /* request resource host base address */
4392         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4393         if (!res) {
4394                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4395                 ret = -ENODEV;
4396                 goto err_deinit_usb2_clocks;
4397         }
4398         tegra->host_phy_base = res->start;
4399         tegra->host_phy_size = resource_size(res);
4400
4401         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4402                                 res->start, resource_size(res));
4403         if (!tegra->host_phy_virt_base) {
4404                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4405                 ret = -ENOMEM;
4406                 goto err_deinit_usb2_clocks;
4407         }
4408
4409         /* Setup IPFS access and BAR0 space */
4410         tegra_xhci_cfg(tegra);
4411
4412         val = readl(tegra->fpci_base + XUSB_CFG_0);
4413         tegra->device_id = (val >> 16) & 0xffff;
4414
4415         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4416                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4417
4418         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4419                 tegra->padregs = &t114_padregs_offset;
4420         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4421                 tegra->padregs = &t124_padregs_offset;
4422         } else {
4423                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4424                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4425                 tegra->padregs = &t124_padregs_offset;
4426         }
4427
4428         /* calculate rctrl_val and tctrl_val once at boot time */
4429         /* Issue is only applicable for T114 */
4430         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4431                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4432
4433         for_each_enabled_hsic_pad(pad, tegra)
4434                 hsic_power_rail_enable(tegra);
4435
4436         /* Program the XUSB pads to take ownership of ports */
4437         tegra_xhci_padctl_portmap_and_caps(tegra);
4438
4439         /* Release XUSB wake logic state latching */
4440         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4441         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4442
4443         /* Deassert reset to XUSB host, ss, dev clocks */
4444         tegra_periph_reset_deassert(tegra->host_clk);
4445         tegra_periph_reset_deassert(tegra->ss_clk);
4446
4447         platform_set_drvdata(pdev, tegra);
4448         fw_log_init(tegra);
4449         ret = init_firmware(tegra);
4450         if (ret < 0) {
4451                 dev_err(&pdev->dev, "failed to init firmware\n");
4452                 ret = -ENODEV;
4453                 goto err_deinit_firmware_log;
4454         }
4455
4456         if (use_bootloader_firmware) {
4457                 ret = tegra_xhci_probe2(tegra);
4458                 if (ret < 0) {
4459                         ret = -ENODEV;
4460                         goto err_deinit_firmware;
4461                 }
4462         }
4463
4464         return 0;
4465
4466 err_deinit_firmware:
4467         deinit_firmware(tegra);
4468 err_deinit_firmware_log:
4469         fw_log_deinit(tegra);
4470 err_deinit_usb2_clocks:
4471         tegra_usb2_clocks_deinit(tegra);
4472 err_deinit_tegra_xusb_regulator:
4473         tegra_xusb_regulator_deinit(tegra);
4474 err_deinit_xusb_partition_clk:
4475         if (tegra->transceiver)
4476                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4477
4478         tegra_xusb_partitions_clk_deinit(tegra);
4479
4480         return ret;
4481 }
4482
4483 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
4484 {
4485         struct platform_device *pdev = tegra->pdev;
4486         const struct hc_driver *driver;
4487         int ret;
4488         struct resource *res;
4489         int irq;
4490         struct xhci_hcd *xhci;
4491         struct usb_hcd  *hcd;
4492         unsigned port;
4493
4494
4495         ret = load_firmware(tegra, true /* do reset ARU */);
4496         if (ret < 0) {
4497                 dev_err(&pdev->dev, "failed to load firmware\n");
4498                 return -ENODEV;
4499         }
4500         pmc_init(tegra);
4501
4502         device_init_wakeup(&pdev->dev, 1);
4503         driver = &tegra_plat_xhci_driver;
4504
4505         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4506         if (!hcd) {
4507                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4508                 return -ENOMEM;
4509         }
4510
4511         /* request resource host base address */
4512         ret = tegra_xhci_request_mem_region(pdev, 0, &hcd->regs);
4513         if (ret) {
4514                 dev_err(&pdev->dev, "failed to map host\n");
4515                 goto err_put_usb2_hcd;
4516         }
4517         hcd->rsrc_start = tegra->host_phy_base;
4518         hcd->rsrc_len = tegra->host_phy_size;
4519
4520         /* Register interrupt handler for HOST */
4521         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4522         if (!res) {
4523                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4524                 ret = -ENODEV;
4525                 goto err_put_usb2_hcd;
4526         }
4527
4528         irq = res->start;
4529         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4530         if (ret) {
4531                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4532                 goto err_put_usb2_hcd;
4533         }
4534
4535         /* USB 2.0 roothub is stored in the platform_device now. */
4536         hcd = dev_get_drvdata(&pdev->dev);
4537         xhci = hcd_to_xhci(hcd);
4538         tegra->xhci = xhci;
4539         platform_set_drvdata(pdev, tegra);
4540
4541         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4542                 if (!IS_ERR_OR_NULL(tegra->transceiver)) {
4543                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4544                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4545                         usb_register_notifier(tegra->transceiver,
4546                                 &tegra->otgnb);
4547                 }
4548         }
4549
4550         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4551                                                 dev_name(&pdev->dev), hcd);
4552         if (!xhci->shared_hcd) {
4553                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4554                 ret = -ENOMEM;
4555                 goto err_remove_usb2_hcd;
4556         }
4557
4558         /*
4559          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4560          * is called by usb_add_hcd().
4561          */
4562         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4563
4564         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4565         if (ret) {
4566                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4567                 goto err_put_usb3_hcd;
4568         }
4569
4570         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4571         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4572
4573         /* do mailbox related initializations */
4574         tegra->mbox_owner = 0xffff;
4575         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4576
4577         tegra_xhci_enable_fw_message(tegra);
4578
4579         /* do ss partition elpg exit related initialization */
4580         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4581
4582         /* do host partition elpg exit related initialization */
4583         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4584
4585         /* Register interrupt handler for SMI line to handle mailbox
4586          * interrupt from firmware
4587          */
4588
4589         ret = tegra_xhci_request_irq(pdev, 1, tegra_xhci_smi_irq,
4590                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4591         if (ret != 0)
4592                 goto err_remove_usb3_hcd;
4593
4594         /* Register interrupt handler for PADCTRL line to
4595          * handle wake on connect irqs interrupt from
4596          * firmware
4597          */
4598         ret = tegra_xhci_request_irq(pdev, 2, tegra_xhci_padctl_irq,
4599                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4600                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4601         if (ret != 0)
4602                 goto err_remove_usb3_hcd;
4603
4604         /* Register interrupt wake handler for USB2 */
4605         ret = tegra_xhci_request_irq(pdev, 4, pmc_usb_phy_wake_isr,
4606                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4607                 &tegra->usb2_irq);
4608         if (ret != 0)
4609                 goto err_remove_usb3_hcd;
4610
4611         /* Register interrupt wake handler for USB3 */
4612         ret = tegra_xhci_request_irq(pdev, 3, pmc_usb_phy_wake_isr,
4613                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4614                 &tegra->usb3_irq);
4615         if (ret != 0)
4616                 goto err_remove_usb3_hcd;
4617
4618         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4619                 tegra->ctle_ctx_saved[port] = false;
4620                 tegra->dfe_ctx_saved[port] = false;
4621         }
4622
4623         hsic_pad_pretend_connect(tegra);
4624
4625         tegra_xhci_debug_read_pads(tegra);
4626         utmi_phy_pad_enable();
4627         utmi_phy_iddq_override(false);
4628
4629         tegra_pd_add_device(&pdev->dev);
4630         pm_runtime_enable(&pdev->dev);
4631
4632         tegra->init_done = true;
4633
4634         return 0;
4635
4636 err_remove_usb3_hcd:
4637         usb_remove_hcd(xhci->shared_hcd);
4638 err_put_usb3_hcd:
4639         usb_put_hcd(xhci->shared_hcd);
4640 err_remove_usb2_hcd:
4641         kfree(tegra->xhci);
4642         usb_remove_hcd(hcd);
4643 err_put_usb2_hcd:
4644         usb_put_hcd(hcd);
4645
4646         return ret;
4647 }
4648
4649 static int tegra_xhci_remove(struct platform_device *pdev)
4650 {
4651         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4652         unsigned pad;
4653
4654         if (tegra == NULL)
4655                 return -EINVAL;
4656
4657         mutex_lock(&tegra->sync_lock);
4658
4659         for_each_enabled_hsic_pad(pad, tegra) {
4660                 hsic_pad_disable(tegra, pad);
4661                 hsic_power_rail_disable(tegra);
4662         }
4663
4664         if (tegra->init_done) {
4665                 struct xhci_hcd *xhci = NULL;
4666                 struct usb_hcd *hcd = NULL;
4667
4668                 xhci = tegra->xhci;
4669                 hcd = xhci_to_hcd(xhci);
4670
4671                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4672                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4673                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4674                 usb_remove_hcd(xhci->shared_hcd);
4675                 usb_put_hcd(xhci->shared_hcd);
4676                 usb_remove_hcd(hcd);
4677                 usb_put_hcd(hcd);
4678                 kfree(xhci);
4679         }
4680
4681         deinit_firmware(tegra);
4682         fw_log_deinit(tegra);
4683
4684         tegra_xusb_regulator_deinit(tegra);
4685
4686         if (tegra->transceiver)
4687                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4688
4689         tegra_usb2_clocks_deinit(tegra);
4690         if (!tegra->hc_in_elpg)
4691                 tegra_xusb_partitions_clk_deinit(tegra);
4692
4693         utmi_phy_pad_disable();
4694         utmi_phy_iddq_override(true);
4695
4696         tegra_pd_remove_device(&pdev->dev);
4697         platform_set_drvdata(pdev, NULL);
4698
4699         mutex_unlock(&tegra->sync_lock);
4700
4701         return 0;
4702 }
4703
4704 static void tegra_xhci_shutdown(struct platform_device *pdev)
4705 {
4706         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4707         struct xhci_hcd *xhci = NULL;
4708         struct usb_hcd *hcd = NULL;
4709
4710         if (tegra == NULL)
4711                 return;
4712
4713         if (tegra->hc_in_elpg) {
4714                 pmc_disable_bus_ctrl(tegra);
4715         } else {
4716                 xhci = tegra->xhci;
4717                 hcd = xhci_to_hcd(xhci);
4718                 xhci_shutdown(hcd);
4719         }
4720 }
4721
4722 static struct platform_driver tegra_xhci_driver = {
4723         .probe  = tegra_xhci_probe,
4724         .remove = tegra_xhci_remove,
4725         .shutdown = tegra_xhci_shutdown,
4726 #ifdef CONFIG_PM
4727         .suspend = tegra_xhci_suspend,
4728         .resume  = tegra_xhci_resume,
4729 #endif
4730         .driver = {
4731                 .name = "tegra-xhci",
4732                 .of_match_table = tegra_xhci_of_match,
4733         },
4734 };
4735 MODULE_ALIAS("platform:tegra-xhci");
4736
4737 int tegra_xhci_register_plat(void)
4738 {
4739         return platform_driver_register(&tegra_xhci_driver);
4740 }
4741
4742 void tegra_xhci_unregister_plat(void)
4743 {
4744         platform_driver_unregister(&tegra_xhci_driver);
4745 }