2 * drivers/usb/phy/tegra11x_usb_phy.c
4 * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/clk/tegra.h>
30 #include <linux/tegra-soc.h>
31 #include <linux/tegra-fuse.h>
32 #include <mach/tegra_usb_pmc.h>
33 #include <mach/tegra_usb_pad_ctrl.h>
35 #include "tegra_usb_phy.h"
36 #include "../../../arch/arm/mach-tegra/gpio-names.h"
38 /* HACK! This needs to come from DT */
39 #include "../../../arch/arm/mach-tegra/iomap.h"
41 #define USB_USBCMD 0x130
42 #define USB_USBCMD_RS (1 << 0)
43 #define USB_CMD_RESET (1<<1)
45 #define USB_USBSTS 0x134
46 #define USB_USBSTS_PCI (1 << 2)
47 #define USB_USBSTS_SRI (1 << 7)
48 #define USB_USBSTS_HCH (1 << 12)
50 #define USB_TXFILLTUNING 0x154
51 #define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
52 #define USB_FIFO_TXFILL_MASK 0x1f0000
54 #define USB_ASYNCLISTADDR 0x148
56 #define ICUSB_CTRL 0x15c
58 #define USB_USBMODE 0x1f8
59 #define USB_USBMODE_MASK (3 << 0)
60 #define USB_USBMODE_HOST (3 << 0)
61 #define USB_USBMODE_DEVICE (2 << 0)
63 #define USB_SUSP_CTRL 0x400
64 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
65 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
66 #define USB_SUSP_CLR (1 << 5)
67 #define USB_CLKEN (1 << 6)
68 #define USB_PHY_CLK_VALID (1 << 7)
69 #define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
70 #define USB_PHY_CLK_VALID_INT_STS (1 << 8)
71 #define UTMIP_RESET (1 << 11)
72 #define UTMIP_PHY_ENABLE (1 << 12)
73 #define UHSIC_RESET (1 << 14)
74 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
75 #define UHSIC_PHY_ENABLE (1 << 19)
77 #define USB_PHY_VBUS_WAKEUP_ID 0x408
78 #define DIV_DET_EN (1 << 31)
79 #define VDCD_DET_STS (1 << 26)
80 #define VDCD_DET_CHG_DET (1 << 25)
81 #define VOP_DIV2P7_DET (1 << 23)
82 #define VOP_DIV2P0_DET (1 << 22)
83 #define VON_DIV2P7_DET (1 << 15)
84 #define VON_DIV2P0_DET (1 << 14)
85 #define VDAT_DET_INT_EN (1 << 16)
86 #define VDAT_DET_CHG_DET (1 << 17)
87 #define VDAT_DET_STS (1 << 18)
88 #define USB_ID_STATUS (1 << 2)
89 #define USB_ID_SW_VALUE (1 << 4)
91 #define USB_IF_SPARE 0x498
92 #define USB_HS_RSM_EOP_EN (1 << 4)
93 #define USB_PORT_SUSPEND_EN (1 << 5)
95 #define USB_NEW_CONTROL 0x4c0
96 #define USB_COHRENCY_EN (1 << 0)
97 #define USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
99 #define UTMIP_XCVR_CFG0 0x808
100 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
101 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
102 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
103 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
104 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
105 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
106 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
107 #define UTMIP_XCVR_SETUP_MSB(x) (((x) & 0x7) << 22)
108 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
109 #define UTMIP_XCVR_HSSLEW_LSB(x) (((x) & 0x3) << 4)
110 #define UTMIP_XCVR_MAX_OFFSET 2
111 #define UTMIP_XCVR_SETUP_MAX_VALUE 0x7f
112 #define UTMIP_XCVR_SETUP_MIN_VALUE 0
113 #define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
115 #define UTMIP_HSRX_CFG0 0x810
116 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
117 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
119 #define UTMIP_HSRX_CFG1 0x814
120 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
122 #define UTMIP_TX_CFG0 0x820
123 #define UTMIP_FS_PREABMLE_J (1 << 19)
124 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
126 #define UTMIP_DEBOUNCE_CFG0 0x82c
127 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
129 #define UTMIP_BAT_CHRG_CFG0 0x830
130 #define UTMIP_PD_CHRG (1 << 0)
131 #define UTMIP_OP_SINK_EN (1 << 1)
132 #define UTMIP_ON_SINK_EN (1 << 2)
133 #define UTMIP_OP_SRC_EN (1 << 3)
134 #define UTMIP_ON_SRC_EN (1 << 4)
135 #define UTMIP_OP_I_SRC_EN (1 << 5)
137 #define UTMIP_XCVR_CFG1 0x838
138 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
139 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
140 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
141 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
142 #define UTMIP_XCVR_HS_IREF_CAP(x) (((x) & 0x3) << 24)
144 #define UTMIP_XCVR_CFG2 0x854
145 #define UTMIP_XCVR_VREG_MASK (0x7 << 9)
146 #define UTMIP_XCVR_VREG_LEV_1P5V (1 << 10)
147 #define UTMIP_XCVR_VREG_FIX18 (1 << 9)
149 #define UTMIP_MISC_CFG0 0x824
150 #define UTMIP_DPDM_OBSERVE (1 << 26)
151 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
152 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
153 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
154 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
155 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
156 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
157 #define DISABLE_PULLUP_DP (1 << 15)
158 #define DISABLE_PULLUP_DM (1 << 14)
159 #define DISABLE_PULLDN_DP (1 << 13)
160 #define DISABLE_PULLDN_DM (1 << 12)
161 #define FORCE_PULLUP_DP (1 << 11)
162 #define FORCE_PULLUP_DM (1 << 10)
163 #define FORCE_PULLDN_DP (1 << 9)
164 #define FORCE_PULLDN_DM (1 << 8)
165 #define COMB_TERMS (1 << 0)
166 #define ALWAYS_FREE_RUNNING_TERMS (1 << 1)
167 #define MASK_ALL_PULLUP_PULLDOWN (0xff << 8)
169 #define UTMIP_SPARE_CFG0 0x834
170 #define FUSE_SETUP_SEL (1 << 3)
171 #define FUSE_ATERM_SEL (1 << 4)
172 #define FUSE_SQUELCH_SEL (1 << 7)
174 #define UHSIC_PLL_CFG1 0xc04
175 #define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
176 #define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
178 #define UHSIC_HSRX_CFG0 0xc08
179 #define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
180 #define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
181 #define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
183 #define UHSIC_HSRX_CFG1 0xc0c
184 #define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
186 #define UHSIC_TX_CFG0 0xc10
187 #define UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9)
188 #define UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 6)
191 #define UHSIC_MISC_CFG0 0xc14
192 #define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7)
193 #define UHSIC_DETECT_SHORT_CONNECT (1 << 8)
194 #define UHSIC_FORCE_XCVR_MODE (1 << 15)
195 #define UHSIC_DISABLE_BUSRESET (1 << 20)
197 #define UHSIC_MISC_CFG1 0xc18
198 #define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
200 #define UHSIC_PADS_CFG0 0xc1c
201 #define UHSIC_TX_RTUNEN 0xf000
202 #define UHSIC_TX_RTUNEP 0xf00
203 #define UHSIC_TX_RTUNE_P(x) (((x) & 0xf) << 8)
204 #define UHSIC_TX_SLEWP (0xf << 16)
205 #define UHSIC_TX_SLEWN (0xf << 20)
207 #define UHSIC_PADS_CFG1 0xc20
208 #define UHSIC_AUTO_RTERM_EN (1 << 0)
209 #define UHSIC_PD_BG (1 << 2)
210 #define UHSIC_PD_TX (1 << 3)
211 #define UHSIC_PD_TRK (1 << 4)
212 #define UHSIC_PD_RX (1 << 5)
213 #define UHSIC_PD_ZI (1 << 6)
214 #define UHSIC_RX_SEL (1 << 7)
215 #define UHSIC_RPD_DATA (1 << 9)
216 #define UHSIC_RPD_STROBE (1 << 10)
217 #define UHSIC_RPU_DATA (1 << 11)
218 #define UHSIC_RPU_STROBE (1 << 12)
220 #define UHSIC_SPARE_CFG0 0xc2c
221 #define FORCE_BK_ON (1 << 12)
223 #define UHSIC_STAT_CFG0 0xc28
224 #define UHSIC_CONNECT_DETECT (1 << 0)
226 #define UHSIC_STATUS(inst) UHSIC_INST(inst, 0x214, 0x290)
227 #define UHSIC_WAKE_ALARM(inst) (1 << UHSIC_INST(inst, 19, 4))
228 #define UHSIC_WALK_PTR_VAL(inst) (0x3 << UHSIC_INST(inst, 6, 0))
229 #define UHSIC_DATA_VAL(inst) (1 << UHSIC_INST(inst, 15, 3))
230 #define UHSIC_STROBE_VAL(inst) (1 << UHSIC_INST(inst, 14, 2))
232 #define UHSIC_CMD_CFG0 0xc24
233 #define UHSIC_PRETEND_CONNECT_DETECT (1 << 5)
235 #define USB_USBINTR 0x138
237 #define UTMIP_STATUS 0x214
238 #define UTMIP_WALK_PTR_VAL(inst) (0x3 << ((inst)*2))
239 #define UTMIP_USBOP_VAL(inst) (1 << ((2*(inst)) + 8))
240 #define UTMIP_USBOP_VAL_P2 (1 << 12)
241 #define UTMIP_USBOP_VAL_P1 (1 << 10)
242 #define UTMIP_USBOP_VAL_P0 (1 << 8)
243 #define UTMIP_USBON_VAL(inst) (1 << ((2*(inst)) + 9))
244 #define UTMIP_USBON_VAL_P2 (1 << 13)
245 #define UTMIP_USBON_VAL_P1 (1 << 11)
246 #define UTMIP_USBON_VAL_P0 (1 << 9)
247 #define UTMIP_WAKE_ALARM(inst) (1 << ((inst) + 16))
248 #define UTMIP_WAKE_ALARM_P2 (1 << 18)
249 #define UTMIP_WAKE_ALARM_P1 (1 << 17)
250 #define UTMIP_WAKE_ALARM_P0 (1 << 16)
251 #define UTMIP_WALK_PTR(inst) (1 << ((inst)*2))
252 #define UTMIP_WALK_PTR_P2 (1 << 4)
253 #define UTMIP_WALK_PTR_P1 (1 << 2)
254 #define UTMIP_WALK_PTR_P0 (1 << 0)
256 #define USB1_PREFETCH_ID 6
257 #define USB2_PREFETCH_ID 18
258 #define USB3_PREFETCH_ID 17
260 #define FUSE_USB_CALIB_0 0x1F0
261 #define XCVR_SETUP_P0(x) (((x) & 0x7F) << 0)
262 #define XCVR_SETUP_P1(x) (((x) & (0x7F << 15)) >> 15)
263 #define XCVR_SETUP_P2(x) (((x) & (0x7F << 22)) >> 22)
264 #define XCVR_SETUP_LSB_MASK 0xF
265 #define XCVR_SETUP_MSB_MASK 0x70
266 #define XCVR_SETUP_LSB_MAX_VAL 0xF
268 #define APB_MISC_GP_OBSCTRL_0 0x818
269 #define APB_MISC_GP_OBSDATA_0 0x81c
271 #define PADCTL_SNPS_OC_MAP 0xC
272 #define CONTROLLER_OC(inst, x) (((x) & 0x7) << (3 * (inst)))
273 #define CONTROLLER_OC_P0(x) (((x) & 0x7) << 0)
274 #define CONTROLLER_OC_P1(x) (((x) & 0x7) << 3)
275 #define CONTROLLER_OC_P2(x) (((x) & 0x7) << 6)
277 #define PADCTL_OC_DET 0x18
278 #define ENABLE0_OC_MAP(x) (((x) & 0x7) << 10)
279 #define ENABLE1_OC_MAP(x) (((x) & 0x7) << 13)
281 #define TEGRA_STREAM_DISABLE 0x1f8
282 #define TEGRA_STREAM_DISABLE_OFFSET (1 << 4)
284 /* These values (in milli second) are taken from the battery charging spec */
285 #define TDP_SRC_ON_MS 100
286 #define TDPSRC_CON_MS 40
288 /* Maxim Debounce Timer */
289 #define MAXIM_DEBOUNCE_TIME 120
291 /* Force port resume wait time in micro second on remote resume */
292 #define FPR_WAIT_TIME_US 25000
294 /* define HSIC phy params */
295 #define HSIC_SYNC_START_DELAY 9
296 #define HSIC_IDLE_WAIT_DELAY 17
297 #define HSIC_ELASTIC_UNDERRUN_LIMIT 16
298 #define HSIC_ELASTIC_OVERRUN_LIMIT 16
300 struct tegra_usb_pmc_data pmc_data[3];
302 static struct tegra_xtal_freq utmip_freq_table[] = {
305 .enable_delay = 0x02,
306 .stable_count = 0x2F,
307 .active_delay = 0x04,
308 .xtal_freq_count = 0x76,
314 .enable_delay = 0x02,
315 .stable_count = 0x33,
316 .active_delay = 0x05,
317 .xtal_freq_count = 0x7F,
323 .enable_delay = 0x03,
324 .stable_count = 0x4B,
325 .active_delay = 0x06,
326 .xtal_freq_count = 0xBB,
332 .enable_delay = 0x04,
333 .stable_count = 0x66,
334 .active_delay = 0x09,
335 .xtal_freq_count = 0xFE,
341 .enable_delay = 0x00,
342 .stable_count = 0x00,
343 .active_delay = 0x18,
344 .xtal_freq_count = 0x177,
350 static struct tegra_xtal_freq uhsic_freq_table[] = {
353 .enable_delay = 0x02,
354 .stable_count = 0x2F,
356 .xtal_freq_count = 0x1CA,
360 .enable_delay = 0x02,
361 .stable_count = 0x33,
363 .xtal_freq_count = 0x1F0,
367 .enable_delay = 0x03,
368 .stable_count = 0x4B,
370 .xtal_freq_count = 0x2DD,
374 .enable_delay = 0x04,
375 .stable_count = 0x66,
377 .xtal_freq_count = 0x3E0,
381 .enable_delay = 0x00,
382 .stable_count = 0x00,
383 .active_delay = 0x18,
384 .xtal_freq_count = 0x177,
388 static void pmc_init(struct tegra_usb_phy *phy)
390 pmc_data[phy->inst].instance = phy->inst;
391 pmc_data[phy->inst].phy_type = phy->pdata->phy_intf;
392 pmc_data[phy->inst].controller_type = TEGRA_USB_2_0;
393 pmc_data[phy->inst].usb_base = phy->regs;
394 tegra_usb_pmc_init(&pmc_data[phy->inst]);
397 static int _usb_phy_init(struct tegra_usb_phy *phy)
400 void __iomem *base = phy->regs;
402 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
404 val = readl(base + HOSTPC1_DEVLC);
405 val &= ~HOSTPC1_DEVLC_STS;
406 writel(val, base + HOSTPC1_DEVLC);
408 val = readl(base + USB_IF_SPARE);
409 val |= USB_HS_RSM_EOP_EN;
410 val |= USB_PORT_SUSPEND_EN;
411 writel(val, base + USB_IF_SPARE);
413 if (phy->pdata->unaligned_dma_buf_supported == true) {
414 val = readl(base + USB_NEW_CONTROL);
415 val |= USB_COHRENCY_EN;
416 val |= USB_MEM_ALLIGNMENT_MUX_EN;
417 writel(val, base + USB_NEW_CONTROL);
419 val = readl(base + TEGRA_STREAM_DISABLE);
420 if (!tegra_platform_is_silicon())
421 val |= TEGRA_STREAM_DISABLE_OFFSET;
423 val &= ~TEGRA_STREAM_DISABLE_OFFSET;
424 writel(val , base + TEGRA_STREAM_DISABLE);
429 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
431 /* Fence read for coherency of AHB master intiated writes */
433 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
434 else if (phy->inst == 1)
435 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
436 else if (phy->inst == 2)
437 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
441 static int usb_phy_reset(struct tegra_usb_phy *phy)
444 void __iomem *base = phy->regs;
446 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
448 if (!tegra_platform_is_silicon()) {
449 val = readl(base + TEGRA_STREAM_DISABLE);
450 val |= TEGRA_STREAM_DISABLE_OFFSET;
451 writel(val , base + TEGRA_STREAM_DISABLE);
453 val = readl(base + USB_TXFILLTUNING);
454 if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
455 val = USB_FIFO_TXFILL_THRES(0x10);
456 writel(val, base + USB_TXFILLTUNING);
462 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
464 void __iomem *base = phy->regs;
465 unsigned int inst = phy->inst;
468 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
469 val = readl(base + UTMIP_PMC_WAKEUP0);
470 if (val & EVENT_INT_ENB) {
471 val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
472 if (UTMIP_WAKE_ALARM(inst) & val) {
473 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG,
474 UTMIP_WAKE_VAL(inst, 0xF),
475 UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE));
477 tegra_usb_pmc_reg_update(PMC_TRIGGERS, 0,
478 UTMIP_CLR_WAKE_ALARM(inst));
480 val = readl(base + UTMIP_PMC_WAKEUP0);
481 val &= ~EVENT_INT_ENB;
482 writel(val, base + UTMIP_PMC_WAKEUP0);
484 val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
485 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN)
486 phy->pmc_remote_wakeup = true;
488 phy->pmc_hotplug_wakeup = true;
490 DBG("%s: utmip PMC interrupt detected\n", __func__);
497 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
500 void __iomem *base = phy->regs;
502 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
503 PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
504 __LINE__, readl(base + USB_USBSTS), readl(base + USB_PORTSC),
507 /* Device is plugged in when system is in LP0 */
508 /* Bring up the controller from LP0*/
509 val = readl(base + USB_USBCMD);
510 val |= USB_CMD_RESET;
511 writel(val, base + USB_USBCMD);
513 if (usb_phy_reg_status_wait(base + USB_USBCMD,
514 USB_CMD_RESET, 0, 2500) < 0) {
515 pr_err("%s: timeout waiting for reset\n", __func__);
518 val = readl(base + USB_USBMODE);
519 val &= ~USB_USBMODE_MASK;
520 val |= USB_USBMODE_HOST;
521 writel(val, base + USB_USBMODE);
522 val = readl(base + HOSTPC1_DEVLC);
523 val &= ~HOSTPC1_DEVLC_PTS(~0);
525 if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
526 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
528 val |= HOSTPC1_DEVLC_STS;
529 writel(val, base + HOSTPC1_DEVLC);
531 /* Enable Port Power */
532 val = readl(base + USB_PORTSC);
533 val |= USB_PORTSC_PP;
534 writel(val, base + USB_PORTSC);
537 /* Check if the phy resume from LP0. When the phy resume from LP0
538 * USB register will be reset.to zero */
539 if (!readl(base + USB_ASYNCLISTADDR)) {
540 /* Program the field PTC based on the saved speed mode */
541 val = readl(base + USB_PORTSC);
542 val &= ~USB_PORTSC_PTC(~0);
543 if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) ||
544 (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC))
545 val |= USB_PORTSC_PTC(5);
546 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
547 val |= USB_PORTSC_PTC(6);
548 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
549 val |= USB_PORTSC_PTC(7);
550 writel(val, base + USB_PORTSC);
553 /* Disable test mode by setting PTC field to NORMAL_OP */
554 val = readl(base + USB_PORTSC);
555 val &= ~USB_PORTSC_PTC(~0);
556 writel(val, base + USB_PORTSC);
560 /* Poll until CCS is enabled */
561 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
562 USB_PORTSC_CCS, 2000)) {
563 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
566 /* Poll until PE is enabled */
567 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
568 USB_PORTSC_PE, 2000)) {
569 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
572 /* Clear the PCI status, to avoid an interrupt taken upon resume */
573 val = readl(base + USB_USBSTS);
574 val |= USB_USBSTS_PCI;
575 writel(val, base + USB_USBSTS);
577 phy->ctrlr_suspended = false;
578 if (!phy->pmc_remote_wakeup) {
579 /* Put controller in suspend mode by writing 1
580 * to SUSP bit of PORTSC */
581 val = readl(base + USB_PORTSC);
582 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
583 val |= USB_PORTSC_SUSP;
584 writel(val, base + USB_PORTSC);
585 phy->ctrlr_suspended = true;
586 /* Wait until port suspend completes */
587 if (usb_phy_reg_status_wait(base + USB_PORTSC,
588 USB_PORTSC_SUSP, USB_PORTSC_SUSP, 4000)) {
589 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
594 PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
595 __LINE__, readl(base + USB_USBSTS), readl(base + USB_PORTSC),
598 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
599 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
603 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
605 struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
608 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
610 if (cfg->xcvr_use_fuses) {
612 val = XCVR_SETUP_P0(tegra_fuse_readl(FUSE_USB_CALIB_0));
613 else if (phy->inst == 1)
614 val = XCVR_SETUP_P1(tegra_fuse_readl(FUSE_USB_CALIB_0));
616 val = XCVR_SETUP_P2(tegra_fuse_readl(FUSE_USB_CALIB_0));
618 if (cfg->xcvr_use_lsb) {
619 val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
620 + cfg->xcvr_setup_offset),
621 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
622 val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
624 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
625 val = val + cfg->xcvr_setup_offset;
627 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
628 val = UTMIP_XCVR_SETUP_MAX_VALUE;
629 pr_info("%s: reset XCVR_SETUP to max value\n",
631 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
632 val = UTMIP_XCVR_SETUP_MIN_VALUE;
633 pr_info("%s: reset XCVR_SETUP to min value\n",
638 val = cfg->xcvr_setup;
641 return (unsigned int) val;
644 static int utmi_phy_open(struct tegra_usb_phy *phy)
646 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
648 unsigned long parent_rate;
651 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
653 phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
654 if (IS_ERR(phy->utmi_pad_clk)) {
655 pr_err("%s: can't get utmip pad clock\n", __func__);
656 return PTR_ERR(phy->utmi_pad_clk);
660 phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
662 if (tegra_platform_is_silicon()) {
663 parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
664 for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
665 if (utmip_freq_table[i].freq == parent_rate) {
666 phy->freq = &utmip_freq_table[i];
671 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
676 /* Power-up the VBUS, ID detector for UTMIP PHY */
677 if (phy->pdata->id_det_type == TEGRA_USB_ID)
678 tegra_usb_pmc_reg_update(PMC_USB_AO,
679 PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0, 0);
681 tegra_usb_pmc_reg_update(PMC_USB_AO,
682 PMC_USB_AO_VBUS_WAKEUP_PD_P0, PMC_USB_AO_ID_PD_P0);
684 pmc->pmc_ops->powerup_pmc_wake_detect(pmc);
689 static void utmi_phy_close(struct tegra_usb_phy *phy)
692 void __iomem *base = phy->regs;
693 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
695 DBG("%s inst:[%d]\n", __func__, phy->inst);
697 /* Disable PHY clock valid interrupts while going into suspend*/
699 val = readl(base + USB_SUSP_CTRL);
700 val &= ~USB_PHY_CLK_VALID_INT_ENB;
701 writel(val, base + USB_SUSP_CTRL);
704 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
705 if (val & UTMIP_MASTER_ENABLE(phy->inst)) {
706 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
708 phy->pmc_remote_wakeup = false;
709 phy->pmc_hotplug_wakeup = false;
710 PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, phy->inst);
713 clk_put(phy->utmi_pad_clk);
716 static int utmi_phy_irq(struct tegra_usb_phy *phy)
718 void __iomem *base = phy->regs;
719 unsigned long val = 0;
720 bool remote_wakeup = false;
721 int irq_status = IRQ_HANDLED;
723 if (phy->phy_clk_on) {
724 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
725 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
726 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
727 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
728 readl(base + USB_USBMODE), readl(base + USB_USBCMD));
730 if (!phy->pdata->unaligned_dma_buf_supported)
731 usb_phy_fence_read(phy);
732 /* check if it is pmc wake event */
733 if (utmi_phy_remotewake_detected(phy))
734 remote_wakeup = phy->pmc_remote_wakeup;
737 val = readl(base + USB_SUSP_CTRL);
738 if ((val & USB_PHY_CLK_VALID_INT_STS) &&
739 (val & USB_PHY_CLK_VALID_INT_ENB)) {
740 val &= ~USB_PHY_CLK_VALID_INT_ENB |
741 USB_PHY_CLK_VALID_INT_STS;
742 writel(val , (base + USB_SUSP_CTRL));
744 /* In case of remote wakeup PHY clock will not up
745 * immediately, so should not access any controller
746 * register but normal plug-in/plug-out should be
749 if (!remote_wakeup) {
750 val = readl(base + USB_USBSTS);
751 if (!(val & USB_USBSTS_PCI)) {
752 irq_status = IRQ_NONE;
756 val = readl(base + USB_PORTSC);
757 if (val & USB_PORTSC_CCS)
758 val &= ~USB_PORTSC_WKCN;
760 val &= ~USB_PORTSC_WKDS;
761 val &= ~USB_PORTSC_RWC_BITS;
762 writel(val , (base + USB_PORTSC));
764 } else if (!phy->phy_clk_on) {
766 irq_status = IRQ_HANDLED;
768 irq_status = IRQ_NONE;
776 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
779 void __iomem *base = phy->regs;
781 /* (2LS WAR)is not required for LS and FS devices and is only for HS */
782 /* Force DP/DM pulldown active for Host mode */
783 val = readl(base + UTMIP_MISC_CFG0);
784 val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
785 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
786 writel(val, base + UTMIP_MISC_CFG0);
787 val = readl(base + UTMIP_MISC_CFG0);
788 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
789 if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
790 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
792 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
793 writel(val, base + UTMIP_MISC_CFG0);
796 val = readl(base + UTMIP_MISC_CFG0);
797 val |= UTMIP_DPDM_OBSERVE;
798 writel(val, base + UTMIP_MISC_CFG0);
800 DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
801 PHY_DBG("ENABLE_OBS_BUS\n");
804 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
806 void __iomem *base = phy->regs;
807 unsigned long val, port_speed;
809 /* check if OBS bus is already enabled */
810 val = readl(base + UTMIP_MISC_CFG0);
811 if (val & UTMIP_DPDM_OBSERVE) {
812 PHY_DBG("DISABLE_OBS_BUS\n");
814 /* disable ALL interrupts on current CPU */
815 local_irq_save(flags);
817 /* Change the UTMIP OBS bus to drive SE0 */
818 val = readl(base + UTMIP_MISC_CFG0);
819 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
820 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
821 writel(val, base + UTMIP_MISC_CFG0);
823 port_speed = (readl(base + USB_PORTSC) >> 26) &
824 USB_PORTSC_PSPD_MASK;
825 if (port_speed == USB_PHY_PORT_SPEED_FULL) {
826 val = readl(base + UTMIP_MISC_CFG0);
827 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
828 writel(val, base + UTMIP_MISC_CFG0);
831 /* Release UTMIP OBS bus */
832 val = readl(base + UTMIP_MISC_CFG0);
833 val &= ~UTMIP_DPDM_OBSERVE;
834 writel(val, base + UTMIP_MISC_CFG0);
836 /* Release DP/DM pulldown for Host mode */
837 val = readl(base + UTMIP_MISC_CFG0);
838 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
839 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
840 writel(val, base + UTMIP_MISC_CFG0);
842 val = readl(base + USB_USBCMD);
843 val |= USB_USBCMD_RS;
844 writel(val, base + USB_USBCMD);
845 /* restore ALL interrupts on current CPU */
846 local_irq_restore(flags);
848 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
849 USB_USBCMD_RS, 2000)) {
850 pr_err("%s: timeout waiting for USB_USBCMD_RS\n",
858 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
861 unsigned int inst = phy->inst;
862 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
864 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
865 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL) {
866 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
867 /* if PMC is not disabled by now then disable it */
868 if (val & UTMIP_MASTER_ENABLE(inst))
869 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
871 utmi_phy_disable_obs_bus(phy);
876 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
879 unsigned int inst = phy->inst;
880 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
882 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
883 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
884 if (val & UTMIP_MASTER_ENABLE(inst)) {
885 if (!remote_wakeup) {
886 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
887 phy->pmc_remote_wakeup = false;
888 phy->pmc_hotplug_wakeup = false;
889 PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
892 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
893 utmi_phy_enable_obs_bus(phy);
899 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
902 void __iomem *base = phy->regs;
903 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
905 PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
906 if (!phy->phy_clk_on) {
907 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
908 __func__, __LINE__, phy->inst);
912 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
913 pmc_data[phy->inst].is_xhci = phy->pdata->u_data.dev.is_xhci;
914 pmc->pmc_ops->powerdown_pmc_wake_detect(pmc);
915 val = readl(base + USB_SUSP_CTRL);
916 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
917 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
918 writel(val, base + USB_SUSP_CTRL);
920 val = readl(base + UTMIP_BAT_CHRG_CFG0);
921 val |= UTMIP_PD_CHRG;
922 writel(val, base + UTMIP_BAT_CHRG_CFG0);
924 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
925 HOSTPC1_DEVLC_PSPD_MASK;
927 /* Disable interrupts */
928 writel(0, base + USB_USBINTR);
930 /* Clear the run bit to stop SOFs when USB is suspended */
931 val = readl(base + USB_USBCMD);
932 val &= ~USB_USBCMD_RS;
933 writel(val, base + USB_USBCMD);
935 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
936 USB_USBSTS_HCH, 2000)) {
937 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n"
941 pmc_data[phy->inst].port_speed = (readl(base +
942 HOSTPC1_DEVLC) >> 25) &
943 HOSTPC1_DEVLC_PSPD_MASK;
945 if (pmc_data[phy->inst].port_speed <
946 USB_PMC_PORT_SPEED_UNKNOWN)
947 phy->pmc_remote_wakeup = false;
949 phy->pmc_hotplug_wakeup = false;
951 if (phy->pdata->port_otg) {
952 bool id_present = false;
953 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
954 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
955 id_present = (val & USB_ID_SW_VALUE) ? false : true;
957 id_present = (val & USB_ID_STATUS) ? false : true;
960 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
962 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
965 val = readl(base + UTMIP_PMC_WAKEUP0);
966 val |= EVENT_INT_ENB;
967 writel(val, base + UTMIP_PMC_WAKEUP0);
968 PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, phy->inst);
970 val = readl(base + USB_SUSP_CTRL);
971 val &= ~USB_WAKE_ON_CNNT_EN_DEV;
972 writel(val, base + USB_SUSP_CTRL);
975 if (!phy->hot_plug) {
976 val = readl(base + UTMIP_XCVR_CFG0);
977 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
978 UTMIP_FORCE_PDZI_POWERDOWN);
979 writel(val, base + UTMIP_XCVR_CFG0);
982 val = readl(base + UTMIP_XCVR_CFG1);
983 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
984 UTMIP_FORCE_PDDR_POWERDOWN;
985 writel(val, base + UTMIP_XCVR_CFG1);
987 val = readl(base + UTMIP_BIAS_CFG1);
988 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
989 writel(val, base + UTMIP_BIAS_CFG1);
992 bool enable_hotplug = true;
993 /* if it is OTG port then make sure to enable hot-plug feature
994 only if host adaptor is connected, i.e id is low */
995 if (phy->pdata->port_otg) {
996 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
997 enable_hotplug = (val & USB_ID_STATUS) ? false : true;
999 if (enable_hotplug) {
1000 /* Enable wakeup event of device plug-in/plug-out */
1001 val = readl(base + USB_PORTSC);
1002 if (val & USB_PORTSC_CCS)
1003 val |= USB_PORTSC_WKDS;
1005 val |= USB_PORTSC_WKCN;
1006 writel(val, base + USB_PORTSC);
1008 if (val & USB_PORTSC_CCS) {
1009 val = readl(base + USB_SUSP_CTRL);
1010 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1012 val = readl(base + USB_SUSP_CTRL);
1013 val |= USB_PHY_CLK_VALID_INT_ENB;
1015 writel(val, base + USB_SUSP_CTRL);
1017 /* Disable PHY clock valid interrupts while going into suspend*/
1018 val = readl(base + USB_SUSP_CTRL);
1019 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1020 writel(val, base + USB_SUSP_CTRL);
1024 /* Disable PHY clock */
1025 val = readl(base + HOSTPC1_DEVLC);
1026 val |= HOSTPC1_DEVLC_PHCD;
1027 writel(val, base + HOSTPC1_DEVLC);
1029 if (!phy->hot_plug) {
1030 val = readl(base + USB_SUSP_CTRL);
1032 writel(val, base + USB_SUSP_CTRL);
1035 utmi_phy_pad_disable();
1036 utmi_phy_iddq_override(true);
1038 phy->phy_clk_on = false;
1039 phy->hw_accessible = false;
1041 PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1047 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1050 void __iomem *base = phy->regs;
1051 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1052 void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1054 struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1055 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1057 PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1058 if (phy->phy_clk_on) {
1059 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1060 __func__, __LINE__, phy->inst);
1063 val = readl(base + USB_SUSP_CTRL);
1065 writel(val, base + USB_SUSP_CTRL);
1067 val = readl(base + UTMIP_TX_CFG0);
1068 val |= UTMIP_FS_PREABMLE_J;
1069 writel(val, base + UTMIP_TX_CFG0);
1071 val = readl(base + USB_USBMODE);
1072 val &= ~USB_USBMODE_MASK;
1073 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1074 val |= USB_USBMODE_HOST;
1076 val |= USB_USBMODE_DEVICE;
1077 writel(val, base + USB_USBMODE);
1079 val = readl(base + UTMIP_HSRX_CFG0);
1080 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1081 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1082 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1083 writel(val, base + UTMIP_HSRX_CFG0);
1085 val = readl(base + UTMIP_HSRX_CFG1);
1086 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1087 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1088 writel(val, base + UTMIP_HSRX_CFG1);
1090 if (tegra_platform_is_silicon()) {
1091 val = readl(base + UTMIP_DEBOUNCE_CFG0);
1092 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1093 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1094 writel(val, base + UTMIP_DEBOUNCE_CFG0);
1097 val = readl(base + UTMIP_MISC_CFG0);
1098 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1099 writel(val, base + UTMIP_MISC_CFG0);
1101 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1102 val = readl(base + USB_SUSP_CTRL);
1103 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1104 writel(val, base + USB_SUSP_CTRL);
1106 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1107 val &= ~UTMIP_PD_CHRG;
1108 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1110 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1111 val |= UTMIP_PD_CHRG;
1112 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1115 utmi_phy_pad_enable();
1117 val = readl(base + UTMIP_XCVR_CFG0);
1118 val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1119 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1120 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1121 UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0) |
1122 UTMIP_XCVR_SETUP_MSB(~0));
1123 val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1124 val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1125 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1126 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1127 if (!config->xcvr_use_lsb) {
1128 if (!config->xcvr_hsslew_msb)
1129 val |= UTMIP_XCVR_HSSLEW_MSB(3);
1131 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew_msb);
1133 if (config->xcvr_hsslew_lsb)
1134 val |= UTMIP_XCVR_HSSLEW_LSB(config->xcvr_hsslew_lsb);
1135 writel(val, base + UTMIP_XCVR_CFG0);
1137 val = readl(base + UTMIP_XCVR_CFG1);
1138 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1139 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1140 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1141 writel(val, base + UTMIP_XCVR_CFG1);
1143 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1144 val = readl(base + UTMIP_BIAS_CFG0);
1145 val &= ~UTMIP_HSSQUELCH_LEVEL(~0);
1146 val |= UTMIP_HSSQUELCH_LEVEL(2);
1147 writel(val, base + UTMIP_BIAS_CFG0);
1149 val = readl(base + UTMIP_BIAS_CFG2);
1150 val &= ~UTMIP_HSSQUELCH_LEVEL_NEW(~0);
1151 val |= UTMIP_HSSQUELCH_LEVEL_NEW(2);
1152 writel(val, base + UTMIP_BIAS_CFG2);
1154 /* 20soc process is not tolerant to 3.3v
1155 * activate protection circuits for usb2 pads
1157 val = readl(base + UTMIP_XCVR_CFG2);
1158 val &= ~UTMIP_XCVR_VREG_MASK;
1159 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1160 val |= UTMIP_XCVR_VREG_LEV_1P5V; /* sink cur */
1162 val |= UTMIP_XCVR_VREG_FIX18; /* source cur */
1163 writel(val, base + UTMIP_XCVR_CFG2);
1165 if (tegra_platform_is_silicon()) {
1166 val = readl(base + UTMIP_BIAS_CFG1);
1167 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1168 val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1169 writel(val, base + UTMIP_BIAS_CFG1);
1172 val = readl(base + UTMIP_SPARE_CFG0);
1173 val &= ~FUSE_SETUP_SEL;
1174 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1175 val &= ~FUSE_SQUELCH_SEL;
1176 val &= ~FUSE_ATERM_SEL;
1178 val |= FUSE_ATERM_SEL;
1180 writel(val, base + UTMIP_SPARE_CFG0);
1182 val = readl(base + USB_SUSP_CTRL);
1183 val |= UTMIP_PHY_ENABLE;
1184 writel(val, base + USB_SUSP_CTRL);
1186 val = readl(base + USB_SUSP_CTRL);
1187 val &= ~UTMIP_RESET;
1188 writel(val, base + USB_SUSP_CTRL);
1190 /* Bring UTMIPLL out of IDDQ mode while exiting from reset/suspend */
1191 utmi_phy_iddq_override(false);
1193 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1194 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2600))
1195 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1197 val = readl(base + HOSTPC1_DEVLC);
1198 val &= ~HOSTPC1_DEVLC_PHCD;
1199 writel(val, base + HOSTPC1_DEVLC);
1201 utmi_phy_set_snps_trking_data();
1204 writel(0, base + ICUSB_CTRL);
1206 val = readl(base + USB_USBMODE);
1207 val &= ~USB_USBMODE_MASK;
1208 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1209 val |= USB_USBMODE_HOST;
1211 val |= USB_USBMODE_DEVICE;
1212 writel(val, base + USB_USBMODE);
1214 val = readl(base + HOSTPC1_DEVLC);
1215 val &= ~HOSTPC1_DEVLC_PTS(~0);
1216 val |= HOSTPC1_DEVLC_STS;
1217 writel(val, base + HOSTPC1_DEVLC);
1219 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1220 pmc_data[phy->inst].is_xhci = phy->pdata->u_data.dev.is_xhci;
1221 pmc->pmc_ops->powerup_pmc_wake_detect(pmc);
1224 if (!readl(base + USB_ASYNCLISTADDR))
1226 val = readl(base + USB_TXFILLTUNING);
1227 if ((val & USB_FIFO_TXFILL_MASK) !=
1228 USB_FIFO_TXFILL_THRES(0x10)) {
1229 val = USB_FIFO_TXFILL_THRES(0x10);
1230 writel(val, base + USB_TXFILLTUNING);
1233 phy->phy_clk_on = true;
1234 phy->hw_accessible = true;
1236 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1237 val = readl(padctl_base + PADCTL_SNPS_OC_MAP);
1238 val |= CONTROLLER_OC(phy->inst, 0x4);
1239 writel(val, padctl_base + PADCTL_SNPS_OC_MAP);
1241 val = readl(padctl_base + PADCTL_OC_DET);
1243 val |= ENABLE0_OC_MAP(config->vbus_oc_map);
1245 val |= ENABLE1_OC_MAP(config->vbus_oc_map);
1246 writel(val, padctl_base + PADCTL_OC_DET);
1249 PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1253 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1256 int inst = phy->inst;
1257 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1259 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1260 val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
1261 /* Check whether we wake up from the remote resume.
1262 For lp1 case, pmc is not responsible for waking the
1263 system, it's the flow controller and hence
1264 UTMIP_WALK_PTR_VAL(inst) will return 0.
1265 Also, for lp1 case phy->pmc_remote_wakeup will already be set
1266 to true by utmi_phy_irq() when the remote wakeup happens.
1267 Hence change the logic in the else part to enter only
1268 if phy->pmc_remote_wakeup is not set to true by the
1270 if (UTMIP_WALK_PTR_VAL(inst) & val) {
1271 phy->pmc_remote_wakeup = true;
1272 } else if (!phy->pmc_remote_wakeup) {
1273 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
1274 if (val & UTMIP_MASTER_ENABLE(inst))
1275 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1277 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1278 utmi_phy_enable_obs_bus(phy);
1282 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1284 unsigned long val, flags = 0;
1285 void __iomem *base = phy->regs;
1286 int wait_time_us = 25000; /* FPR should be set by this time */
1287 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1289 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1290 /* check whether we wake up from the remote resume */
1291 if (phy->pmc_remote_wakeup) {
1292 /* wait until SUSPEND and RESUME bit
1293 * is cleared on remote resume */
1295 val = readl(base + USB_PORTSC);
1297 if (wait_time_us == 0) {
1298 PHY_DBG("%s PMC FPR" \
1299 "timeout val = 0x%x instance = %d\n", \
1300 __func__, (u32)val, phy->inst);
1301 if (phy->port_speed ==
1302 USB_PHY_PORT_SPEED_FULL) {
1303 val = readl(base + UTMIP_PMC_WAKEUP0);
1304 val &= ~EVENT_INT_ENB;
1305 writel(val, base + UTMIP_PMC_WAKEUP0);
1307 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1308 phy->pmc_remote_wakeup = false;
1309 phy->pmc_hotplug_wakeup = false;
1311 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1312 utmi_phy_post_resume(phy);
1316 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1318 /* Add delay sothat resume will be driven for more than 20 ms */
1319 if (phy->port_speed != USB_PHY_PORT_SPEED_FULL) {
1320 usleep_range(10000, 11000);
1321 local_irq_save(flags);
1322 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 1);
1323 phy->pmc_remote_wakeup = false;
1324 phy->pmc_hotplug_wakeup = false;
1325 local_irq_restore(flags);
1326 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1327 USB_USBCMD_RS, USB_USBCMD_RS, 2000))
1329 "%s: timeout waiting for USB_USBCMD_RS\n",
1332 usleep_range(25000, 26000);
1333 local_irq_save(flags);
1334 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1335 phy->pmc_remote_wakeup = false;
1336 phy->pmc_hotplug_wakeup = false;
1337 local_irq_restore(flags);
1340 PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, phy->inst);
1342 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1343 val = readl(base + USB_USBSTS);
1344 writel(val, base + USB_USBSTS);
1345 /* wait to avoid SOF if there is any */
1346 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1347 USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1348 pr_err("%s: timeout waiting for SOF\n", __func__);
1351 if (phy->port_speed != USB_PHY_PORT_SPEED_FULL) {
1352 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1353 phy->pmc_remote_wakeup = false;
1354 phy->pmc_hotplug_wakeup = false;
1355 PHY_DBG("%s DISABLE_PMC inst = %d\n",
1356 __func__, phy->inst);
1359 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1360 utmi_phy_post_resume(phy);
1363 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1367 int port_connected = 0;
1369 void __iomem *base = phy->regs;
1370 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1372 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1373 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1374 if (readl(base + USB_ASYNCLISTADDR) &&
1375 !phy->pdata->u_data.host.power_off_on_suspend)
1378 val = readl(base + USB_PORTSC);
1379 port_connected = val & USB_PORTSC_CCS;
1380 is_lp0 = !(readl(base + USB_ASYNCLISTADDR));
1382 if ((phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) &&
1383 (port_connected ^ is_lp0)) {
1384 utmi_phy_restore_start(phy);
1385 usb_phy_bringup_host_controller(phy);
1386 utmi_phy_restore_end(phy);
1388 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1389 phy->pmc_remote_wakeup = false;
1390 phy->pmc_hotplug_wakeup = false;
1392 /* bring up the controller from suspend*/
1393 val = readl(base + USB_USBCMD);
1394 val |= USB_CMD_RESET;
1395 writel(val, base + USB_USBCMD);
1397 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1398 USB_CMD_RESET, 0, 2500) < 0) {
1399 pr_err("%s: timeout waiting for reset\n", __func__);
1402 val = readl(base + USB_USBMODE);
1403 val &= ~USB_USBMODE_MASK;
1404 val |= USB_USBMODE_HOST;
1405 writel(val, base + USB_USBMODE);
1407 val = readl(base + HOSTPC1_DEVLC);
1408 val &= ~HOSTPC1_DEVLC_PTS(~0);
1409 val |= HOSTPC1_DEVLC_STS;
1410 writel(val, base + HOSTPC1_DEVLC);
1412 writel(USB_USBCMD_RS, base + USB_USBCMD);
1414 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1415 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1416 pr_err("%s: timeout waiting for run bit\n", __func__);
1419 /* Enable Port Power */
1420 val = readl(base + USB_PORTSC);
1421 val |= USB_PORTSC_PP;
1422 writel(val, base + USB_PORTSC);
1425 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1426 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1428 val = readl(base + USB_TXFILLTUNING);
1429 if ((val & USB_FIFO_TXFILL_MASK) !=
1430 USB_FIFO_TXFILL_THRES(0x10)) {
1431 val = USB_FIFO_TXFILL_THRES(0x10);
1432 writel(val, base + USB_TXFILLTUNING);
1439 static unsigned long utmi_phy_set_dp_dm_pull_up_down(struct tegra_usb_phy *phy,
1440 unsigned long pull_up_down_flags)
1444 void __iomem *base = phy->regs;
1446 org = readl(base + UTMIP_MISC_CFG0);
1448 val = org & ~MASK_ALL_PULLUP_PULLDOWN;
1449 val |= pull_up_down_flags;
1451 writel(val, base + UTMIP_MISC_CFG0);
1453 usleep_range(500, 2000);
1457 unsigned long utmi_phy_get_dp_dm_status(struct tegra_usb_phy *phy,
1458 unsigned long pull_up_down_flags)
1460 void __iomem *base = phy->regs;
1461 unsigned long org_flags;
1464 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy, pull_up_down_flags);
1465 ret = USB_PORTSC_LINE_STATE(readl(base + USB_PORTSC));
1466 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1470 static void disable_charger_detection(void __iomem *base)
1474 /* Disable charger detection logic */
1475 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1476 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1477 val &= ~(UTMIP_ON_SRC_EN | UTMIP_OP_SINK_EN);
1478 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1480 /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1481 msleep(TDPSRC_CON_MS);
1485 * Per Battery Charging Specification 1.2 section 3.2.3:
1486 * We check Data Contact Detect (DCD) before we check the USB cable type.
1488 static bool utmi_phy_dcd_detect(struct tegra_usb_phy *phy)
1490 void __iomem *base = phy->regs;
1492 unsigned long org_flags;
1495 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1496 /* inject IDP_SRC */
1497 val |= UTMIP_OP_I_SRC_EN;
1498 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1499 /* enable pull down resistor RDM_DWN on D- */
1500 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1501 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1502 DISABLE_PULLDN_DP | FORCE_PULLDN_DM);
1503 usleep_range(20000, 30000);
1506 if (0 == USB_PORTSC_LINE_STATE(readl(base + USB_PORTSC))) {
1507 /* minimum debounce time is 10mS per TDCD_DBNC */
1508 usleep_range(10000, 12000);
1509 if (0 == USB_PORTSC_LINE_STATE(readl(base + USB_PORTSC)))
1513 val &= ~UTMIP_OP_I_SRC_EN;
1514 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1515 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1519 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1522 void __iomem *base = phy->regs;
1526 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1527 if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1528 /* Charger detection is not there for ULPI
1529 * return Charger not available */
1533 /* ensure we start from an initial state */
1534 writel(0, base + UTMIP_BAT_CHRG_CFG0);
1535 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1537 /* log initial values */
1538 DBG("%s(%d) inst:[%d], UTMIP_BAT_CHRG_CFG0 = %08X\n",
1540 phy->inst, readl(base + UTMIP_BAT_CHRG_CFG0));
1541 DBG("%s(%d) inst:[%d], UTMIP_MISC_CFG0 = %08X\n",
1543 phy->inst, readl(base + UTMIP_MISC_CFG0));
1545 /* DCD timeout max value is 900mS */
1547 while (dcd_timeout_ms < 900) {
1548 /* standard DCD detect for SDP/DCP/CDP */
1549 if (utmi_phy_dcd_detect(phy))
1551 /* for NV-charger, we wait D+/D- both set */
1552 if ((USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET) ==
1553 utmi_phy_get_dp_dm_status(phy,
1554 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1555 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM))
1557 usleep_range(20000, 22000);
1558 dcd_timeout_ms += 22;
1561 /* Enable charger detection logic */
1562 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1563 val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1564 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1566 /* Source should be on for 100 ms as per USB charging spec */
1567 msleep(TDP_SRC_ON_MS);
1569 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1570 /* If charger is not connected disable the interrupt */
1571 val &= ~VDAT_DET_INT_EN;
1572 val |= VDAT_DET_CHG_DET;
1573 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1575 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1576 if (val & VDAT_DET_STS)
1580 disable_charger_detection(base);
1582 DBG("%s(%d) inst:[%d], UTMIP_BAT_CHRG_CFG0 = %08X\n",
1584 phy->inst, readl(base + UTMIP_BAT_CHRG_CFG0));
1585 DBG("%s(%d) inst:[%d], UTMIP_MISC_CFG0 = %08X\n",
1587 phy->inst, readl(base + UTMIP_MISC_CFG0));
1589 DBG("%s(%d) inst:[%d] DONE Status = %d\n",
1590 __func__, __LINE__, phy->inst, status);
1595 static bool cdp_charger_detection(struct tegra_usb_phy *phy)
1599 void __iomem *base = phy->regs;
1602 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1603 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1604 val |= UTMIP_ON_SRC_EN | UTMIP_OP_SINK_EN;
1605 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1607 DBG("%s(%d) UTMIP_BAT_CHRG_CFG0 = %08x\n",
1609 readl(base + UTMIP_BAT_CHRG_CFG0));
1613 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1614 if (val & VDAT_DET_STS) {
1616 DBG("%s: DCP detected\n", __func__);
1619 disable_charger_detection(base);
1620 DBG("%s: No voltage from D- to D+ found\n", __func__);
1626 static bool maxim_charger_detection(struct tegra_usb_phy *phy)
1628 void __iomem *base = phy->regs;
1630 unsigned long org_flags;
1634 * Enable charger detection logic
1635 * 3.3V on D+, Sink D- (high speed usb)
1636 * Maxim charger will remove short !! -- DCP will not
1638 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1639 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1640 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1641 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1642 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1643 val &= ~(UTMIP_ON_SRC_EN | UTMIP_OP_SINK_EN);
1644 val |= UTMIP_ON_SINK_EN;
1645 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1647 /* Source should be on at least 120 ms per Maxim spec */
1648 msleep(MAXIM_DEBOUNCE_TIME);
1650 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1651 if (val & VDAT_DET_STS) {
1653 DBG("%s: Maxim charger not found\n", __func__);
1654 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1657 DBG("%s: Maxim Charger detected\n", __func__);
1660 disable_charger_detection(base);
1664 static bool utmi_phy_qc2_charger_detect(struct tegra_usb_phy *phy,
1668 void __iomem *base = phy->regs;
1672 unsigned long org_flags;
1673 #ifdef QC_MEASURE_VOLTAGES
1677 DBG("%s(%d) inst:[%d] max_voltage = %d\n",
1678 __func__, __LINE__, phy->inst, max_voltage);
1681 /* no need to detect qc2 if operating at 5V */
1682 switch (max_voltage) {
1683 case TEGRA_USB_QC2_5V:
1684 case TEGRA_USB_QC2_9V:
1685 case TEGRA_USB_QC2_12V:
1686 case TEGRA_USB_QC2_20V:
1689 disable_charger_detection(base);
1693 /* Ensure we start from an initial state */
1694 writel(0, base + UTMIP_BAT_CHRG_CFG0);
1695 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1698 * The QC2 charger can be inserted when the system is
1699 * powered down. In this case it will act as a DCP unless
1700 * it is forced to negotiate voltage. This is because
1701 * the QC2 charger will not see D+/D- voltage signaling
1702 * with in its negotiation timer window.
1703 * We try to detect this condition. We know that if
1704 * we enter suspend then system must be active before
1705 * the QC2 charger was seen.
1706 * In this case no reset of the charger is needed, otherwise
1707 * we force the D+ and D- Pull Up down which will reset a
1708 * QC2 charger but have no effect on a normal DCP.
1710 if (!phy->qc2_no_reset) {
1711 phy->qc2_no_reset = true;
1712 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1713 FORCE_PULLDN_DP | FORCE_PULLDN_DM);
1716 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1719 /* Enable charger detection logic */
1720 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1721 val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1722 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1724 /* Source should be on for 100 ms as per USB charging spec */
1725 msleep(TDP_SRC_ON_MS);
1727 /* if vbus drops we are connected to quick charge 2 */
1729 while (qc2_timeout_ms < 1500) {
1730 usleep_range(1000, 1200);
1731 qc2_timeout_ms += 1;
1732 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1733 if (!(val & VDAT_DET_STS)) {
1739 if (vbus_stat && qc2_timeout_ms > 100) {
1742 DBG("%s(%d) inst:[%d], QC2 DETECTED !!!",
1743 __func__, __LINE__, phy->inst);
1745 /* Wall charger needs time before setting D+/D- */
1746 usleep_range(25000, 26000);
1748 switch (max_voltage) {
1749 case TEGRA_USB_QC2_9V:
1750 /* Set the input voltage to 9V */
1751 /* D+ 3.3v -- D- 0.6v */
1752 DBG("%s(%d) inst:[%d], QC 9V D+ 3.3v D- 0.6v",
1753 __func__, __LINE__, phy->inst);
1754 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1755 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1756 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1757 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1758 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1759 val |= UTMIP_ON_SRC_EN;
1760 val &= ~UTMIP_OP_SRC_EN;
1761 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1764 case TEGRA_USB_QC2_12V:
1765 /* 0.6v v on D+ and D- */
1766 DBG("%s(%d) inst:[%d], QC 12V D+ 0.6v D- 0.6v",
1767 __func__, __LINE__, phy->inst);
1768 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1769 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1770 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1771 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1772 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1773 val |= (UTMIP_OP_SRC_EN | UTMIP_ON_SRC_EN);
1774 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1777 case TEGRA_USB_QC2_20V:
1778 /* 3.3 v on D+ and D- */
1779 DBG("%s(%d) inst:[%d], QC 20V D+ 3.3v D- 3.3v",
1780 __func__, __LINE__, phy->inst);
1781 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1782 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1783 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1784 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1785 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1786 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SRC_EN);
1787 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1790 case TEGRA_USB_QC2_5V:
1792 DBG("%s(%d) inst:[%d], QC 5V D+ 0.6v D- GND",
1793 __func__, __LINE__, phy->inst);
1794 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1795 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1796 DISABLE_PULLDN_DP | FORCE_PULLDN_DM);
1797 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1798 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1799 val |= UTMIP_OP_SRC_EN;
1800 val &= ~UTMIP_ON_SRC_EN;
1801 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1805 #ifdef QC_MEASURE_VOLTAGES
1807 DBG("%s(%d) MEASURE VOLTAGES -- you have %d seconds",
1808 __func__, __LINE__, timeout);
1809 while (timeout-- > 0) {
1810 DBG("%s(%d) COUNT = %d",
1811 __func__, __LINE__, timeout);
1818 * If QC2 charger detected do not disable the charger
1819 * detection voltage on D- and D+. Doing this will
1820 * cause it to move to 5V
1823 disable_charger_detection(base);
1825 DBG("%s(%d) inst:[%d] DONE Status = %d\n",
1826 __func__, __LINE__, phy->inst, status);
1830 static bool utmi_phy_is_non_std_charger(struct tegra_usb_phy *phy)
1833 * non std charger has D+/D- line float, we can apply pull up/down on
1834 * each line and verify if line status change.
1836 /* pull up DP only */
1837 if (USB_PORTSC_LINE_DP_SET != utmi_phy_get_dp_dm_status(phy,
1838 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1839 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM))
1840 goto NOT_NON_STD_CHARGER;
1842 /* pull down DP only */
1843 if (0x0 != utmi_phy_get_dp_dm_status(phy,
1844 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1845 FORCE_PULLDN_DP | DISABLE_PULLDN_DM))
1846 goto NOT_NON_STD_CHARGER;
1848 /* pull up DM only */
1849 if (USB_PORTSC_LINE_DM_SET != utmi_phy_get_dp_dm_status(phy,
1850 DISABLE_PULLUP_DP | FORCE_PULLUP_DM |
1851 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM))
1852 goto NOT_NON_STD_CHARGER;
1854 /* pull down DM only */
1855 if (0x0 != utmi_phy_get_dp_dm_status(phy,
1856 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1857 DISABLE_PULLDN_DP | FORCE_PULLDN_DM))
1858 goto NOT_NON_STD_CHARGER;
1860 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1863 NOT_NON_STD_CHARGER:
1864 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1869 static void utmi_phy_pmc_disable(struct tegra_usb_phy *phy)
1871 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1872 if (phy->pdata->u_data.host.turn_off_vbus_on_lp0 &&
1873 phy->pdata->port_otg) {
1874 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1875 pmc->pmc_ops->powerdown_pmc_wake_detect(pmc);
1878 static bool utmi_phy_nv_charger_detect(struct tegra_usb_phy *phy)
1885 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1887 if (utmi_phy_is_non_std_charger(phy))
1891 /* Turn off all terminations except DP pulldown */
1892 status1 = utmi_phy_get_dp_dm_status(phy,
1893 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1894 FORCE_PULLDN_DP | DISABLE_PULLDN_DM);
1896 /* Turn off all terminations except for DP pullup */
1897 status2 = utmi_phy_get_dp_dm_status(phy,
1898 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1899 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1901 /* Check for NV charger DISABLE all terminations */
1902 status3 = utmi_phy_get_dp_dm_status(phy,
1903 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1904 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1906 if ((status1 == (USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET)) &&
1907 (status2 == (USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET)) &&
1908 (status3 == (USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET)))
1911 /* Restore standard termination by hardware. */
1912 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1916 static bool utmi_phy_apple_charger_1000ma_detect(struct tegra_usb_phy *phy)
1920 void __iomem *base = phy->regs;
1921 unsigned long org_flags;
1923 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1926 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1927 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1928 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1929 usleep_range(20000, 30000);
1930 utmi_phy_set_dp_dm_pull_up_down(phy,
1931 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1932 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1934 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1936 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1938 usleep_range(10000, 20000);
1940 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1942 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1944 if ((val & VOP_DIV2P0_DET) && (val & VON_DIV2P7_DET))
1947 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1952 static bool utmi_phy_apple_charger_2000ma_detect(struct tegra_usb_phy *phy)
1956 void __iomem *base = phy->regs;
1957 unsigned long org_flags;
1959 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1962 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1963 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1964 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1965 usleep_range(20000, 30000);
1966 utmi_phy_set_dp_dm_pull_up_down(phy,
1967 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1968 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1970 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1972 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1974 usleep_range(10000, 20000);
1976 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1978 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1980 if ((val & VOP_DIV2P7_DET) && (val & VON_DIV2P0_DET))
1983 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1988 static bool utmi_phy_apple_charger_500ma_detect(struct tegra_usb_phy *phy)
1992 void __iomem *base = phy->regs;
1993 unsigned long org_flags;
1995 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1998 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1999 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
2000 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
2001 usleep_range(20000, 30000);
2002 utmi_phy_set_dp_dm_pull_up_down(phy,
2003 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
2004 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
2006 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
2008 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
2010 usleep_range(10000, 20000);
2012 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
2014 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
2016 if ((val & VOP_DIV2P0_DET) && (val & VON_DIV2P0_DET))
2019 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
2024 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
2026 void __iomem *base = phy->regs;
2028 unsigned int inst = phy->inst;
2030 val = readl(base + UHSIC_PMC_WAKEUP0);
2031 if (!(val & EVENT_INT_ENB))
2033 val = tegra_usb_pmc_reg_read(UHSIC_STATUS(inst));
2034 if (!(UHSIC_WAKE_ALARM(inst) & val))
2036 tegra_usb_pmc_reg_update(PMC_UHSIC_SLEEP_CFG(inst),
2037 UHSIC_WAKE_VAL(inst, WAKE_VAL_ANY),
2038 UHSIC_WAKE_VAL(inst, WAKE_VAL_NONE));
2040 tegra_usb_pmc_reg_update(PMC_UHSIC_TRIGGERS(inst),
2041 0, UHSIC_CLR_WAKE_ALARM(inst));
2043 val = readl(base + UHSIC_PMC_WAKEUP0);
2044 val &= ~EVENT_INT_ENB;
2045 writel(val, base + UHSIC_PMC_WAKEUP0);
2046 phy->pmc_remote_wakeup = true;
2047 DBG("%s:PMC interrupt detected for HSIC\n", __func__);
2051 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2054 void __iomem *base = phy->regs;
2056 if (remote_wakeup) {
2058 val = readl(base + USB_USBCMD);
2059 val |= USB_USBCMD_RS;
2060 writel(val, base + USB_USBCMD);
2063 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2068 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2071 void __iomem *base = phy->regs;
2072 unsigned int inst = phy->inst;
2073 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2075 val = tegra_usb_pmc_reg_read(UHSIC_STATUS(inst));
2077 /* check whether we wake up from the remote resume */
2078 if (UHSIC_WALK_PTR_VAL(inst) & val) {
2079 phy->pmc_remote_wakeup = true;
2080 DBG("%s: uhsic remote wakeup detected\n", __func__);
2082 if (!((UHSIC_STROBE_VAL(inst) | UHSIC_DATA_VAL(inst)) & val)) {
2085 * If pmc wakeup is detected after putting controller
2086 * in suspend in usb_phy_bringup_host_cotroller,
2087 * restart bringing up host controller as
2088 * in case of only pmc wakeup.
2090 if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2091 usb_phy_bringup_host_controller(phy);
2092 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2093 (USB_PORTSC_RESUME | USB_PORTSC_SUSP),
2094 0, FPR_WAIT_TIME_US) < 0)
2095 pr_err("%s: timeout waiting" \
2096 "for SUSPEND to clear\n",
2098 phy->ctrlr_suspended = false;
2101 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
2102 phy->pmc_remote_wakeup = false;
2104 DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2105 val = readl(base + UHSIC_CMD_CFG0);
2106 val |= UHSIC_PRETEND_CONNECT_DETECT;
2107 writel(val, base + UHSIC_CMD_CFG0);
2112 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2115 unsigned long val, flags = 0;
2116 void __iomem *base = phy->regs;
2117 int wait_time_us = FPR_WAIT_TIME_US; /* FPR should be set by this time */
2118 bool irq_disabled = false;
2119 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2120 bool remote_wakeup_detected;
2122 DBG("%s(%d)\n", __func__, __LINE__);
2124 remote_wakeup_detected = phy->pmc_remote_wakeup;
2126 * check whether we wake up from the remote wake detected before putting
2127 * controller in suspend in usb_phy_bringup_host_controller.
2129 if (!phy->ctrlr_suspended) {
2130 /* wait until FPR bit is set automatically on remote resume */
2132 val = readl(base + USB_PORTSC);
2134 if (wait_time_us == 0) {
2136 * If pmc wakeup is detected after putting controller
2137 * in suspend in usb_phy_bringup_host_cotroller,
2138 * restart bringing up host controller as
2139 * in case of only pmc wakeup.
2141 if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2142 usb_phy_bringup_host_controller(phy);
2143 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2144 (USB_PORTSC_RESUME | USB_PORTSC_SUSP),
2145 0, FPR_WAIT_TIME_US) < 0)
2146 pr_err("%s: timeout waiting" \
2147 " for SUSPEND to clear\n",
2149 phy->ctrlr_suspended = false;
2152 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
2153 phy->pmc_remote_wakeup = false;
2157 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
2158 /* In case of remote wakeup, disable local irq to prevent
2159 * context switch b/t disable PMC and set RUN bit ops */
2160 local_irq_save(flags);
2161 irq_disabled = true;
2165 * If pmc wakeup is detected after putting controller in suspend
2166 * in usb_phy_bringup_host_cotroller, restart bringing up host
2167 * controller as in case of only pmc wakeup.
2169 if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2170 usb_phy_bringup_host_controller(phy);
2171 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2172 (USB_PORTSC_RESUME | USB_PORTSC_SUSP), 0,
2173 FPR_WAIT_TIME_US) < 0)
2174 pr_err("%s: timeout waiting for SUSPEND to clear\n",
2176 phy->ctrlr_suspended = false;
2179 val = tegra_usb_pmc_reg_read(PMC_UHSIC_SLEEP_CFG(phy->inst));
2180 if (val & UHSIC_MASTER_ENABLE(phy->inst)) {
2181 val = readl(base + UHSIC_PADS_CFG1);
2182 val &= ~(UHSIC_PD_TX);
2183 writel(val, base + UHSIC_PADS_CFG1);
2187 local_irq_restore(flags);
2188 usleep_range(25000, 26000);
2189 local_irq_save(flags);
2191 usleep_range(10000, 11000);
2193 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 1);
2194 phy->pmc_remote_wakeup = false;
2196 /* Restore local irq if disabled before */
2198 local_irq_restore(flags);
2199 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2200 USB_USBCMD_RS, 2000)) {
2201 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2204 if (remote_wakeup_detected && phy->pdata->ops &&
2205 phy->pdata->ops->post_remote_wakeup)
2206 phy->pdata->ops->post_remote_wakeup();
2209 static int uhsic_rail_enable(struct tegra_usb_phy *phy)
2213 if (phy->hsic_reg == NULL) {
2214 phy->hsic_reg = regulator_get(&phy->pdev->dev, "vddio_hsic");
2215 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2216 pr_err("UHSIC: Could not get regulator vddio_hsic\n");
2217 ret = PTR_ERR(phy->hsic_reg);
2218 phy->hsic_reg = NULL;
2223 ret = regulator_enable(phy->hsic_reg);
2225 pr_err("%s vddio_hsic could not be enabled\n", __func__);
2232 static int uhsic_rail_disable(struct tegra_usb_phy *phy)
2236 if (phy->hsic_reg == NULL) {
2237 pr_warn("%s: unbalanced disable\n", __func__);
2241 ret = regulator_disable(phy->hsic_reg);
2243 pr_err("HSIC regulator vddio_hsic cannot be disabled\n");
2246 regulator_put(phy->hsic_reg);
2247 phy->hsic_reg = NULL;
2251 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2253 unsigned long parent_rate;
2256 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2258 phy->hsic_reg = NULL;
2259 ret = uhsic_rail_enable(phy);
2261 pr_err("%s vddio_hsic could not be enabled\n", __func__);
2265 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2266 parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2267 for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2268 if (uhsic_freq_table[i].freq == parent_rate) {
2269 phy->freq = &uhsic_freq_table[i];
2274 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2277 /* reset controller for reenumerating hsic device */
2278 tegra_periph_reset_assert(phy->ctrlr_clk);
2280 tegra_periph_reset_deassert(phy->ctrlr_clk);
2283 uhsic_phy_set_snps_trking_data();
2286 pmc->pmc_ops->powerup_pmc_wake_detect(pmc);
2291 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2294 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2296 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2297 pmc->pmc_ops->powerdown_pmc_wake_detect(pmc);
2299 ret = uhsic_rail_disable(phy);
2301 pr_err("%s vddio_hsic could not be disabled\n", __func__);
2304 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2307 void __iomem *base = phy->regs;
2308 int irq_status = IRQ_HANDLED;
2310 /* check if there is any remote wake event */
2311 if (!phy->pdata->unaligned_dma_buf_supported)
2312 usb_phy_fence_read(phy);
2313 if (uhsic_phy_remotewake_detected(phy))
2314 DBG("%s: uhsic remote wake detected\n", __func__);
2316 val = readl(base + USB_SUSP_CTRL);
2317 if ((val & USB_PHY_CLK_VALID_INT_STS) &&
2318 (val & USB_PHY_CLK_VALID_INT_ENB)) {
2319 val &= ~USB_PHY_CLK_VALID_INT_ENB |
2320 USB_PHY_CLK_VALID_INT_STS;
2321 writel(val , (base + USB_SUSP_CTRL));
2323 val = readl(base + USB_USBSTS);
2324 if (!(val & USB_USBSTS_PCI)) {
2325 irq_status = IRQ_NONE;
2329 val = readl(base + USB_PORTSC);
2330 if (val & USB_PORTSC_CCS)
2331 val &= ~USB_PORTSC_WKCN;
2332 val &= ~USB_PORTSC_RWC_BITS;
2333 writel(val , (base + USB_PORTSC));
2334 irq_status = IRQ_HANDLED;
2340 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2343 void __iomem *base = phy->regs;
2344 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2345 void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
2348 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2350 if (phy->phy_clk_on) {
2351 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2352 __func__, __LINE__, phy->inst);
2356 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2357 val = readl(padctl_base + PADCTL_SNPS_OC_MAP);
2358 val |= CONTROLLER_OC(phy->inst, 0x7);
2359 writel(val, padctl_base + PADCTL_SNPS_OC_MAP);
2362 val = readl(base + UHSIC_PADS_CFG1);
2363 val &= ~(UHSIC_PD_BG | UHSIC_PD_RX |
2364 UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2365 writel(val, base + UHSIC_PADS_CFG1);
2367 val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2368 val |= UHSIC_AUTO_RTERM_EN;
2369 writel(val, base + UHSIC_PADS_CFG1);
2371 val = readl(base + USB_SUSP_CTRL);
2373 writel(val, base + USB_SUSP_CTRL);
2376 val = readl(base + USB_SUSP_CTRL);
2377 val |= UHSIC_PHY_ENABLE;
2378 writel(val, base + USB_SUSP_CTRL);
2380 val = readl(base + UHSIC_HSRX_CFG0);
2381 val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
2382 val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
2383 val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
2384 writel(val, base + UHSIC_HSRX_CFG0);
2386 val = readl(base + UHSIC_HSRX_CFG1);
2387 val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
2388 writel(val, base + UHSIC_HSRX_CFG1);
2391 val = readl(base + UHSIC_TX_CFG0);
2392 val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2393 writel(val, base + UHSIC_TX_CFG0);
2395 val = readl(base + UHSIC_MISC_CFG0);
2396 val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2397 writel(val, base + UHSIC_MISC_CFG0);
2399 val = readl(base + UHSIC_MISC_CFG1);
2400 val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2401 writel(val, base + UHSIC_MISC_CFG1);
2403 val = readl(base + UHSIC_PLL_CFG1);
2404 val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2405 val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2406 writel(val, base + UHSIC_PLL_CFG1);
2408 val = readl(base + USB_SUSP_CTRL);
2409 val &= ~(UHSIC_RESET);
2410 writel(val, base + USB_SUSP_CTRL);
2413 val = tegra_usb_pmc_reg_read(PMC_UHSIC_SLEEP_CFG(phy->inst));
2414 if (!(val & UHSIC_MASTER_ENABLE(phy->inst))) {
2415 val = readl(base + UHSIC_PADS_CFG1);
2416 val &= ~(UHSIC_PD_TX);
2417 writel(val, base + UHSIC_PADS_CFG1);
2420 /* HSIC pad tracking circuit power down sequence */
2421 val = readl(base + UHSIC_PADS_CFG1);
2422 val &= ~(UHSIC_PD_TRK);
2423 writel(val, base + UHSIC_PADS_CFG1);
2424 /* Wait for 25usec */
2426 val |= UHSIC_PD_TRK;
2427 writel(val, base + UHSIC_PADS_CFG1);
2429 /* Enable bus keepers always */
2430 val = readl(base + UHSIC_SPARE_CFG0);
2432 writel(val, base + UHSIC_SPARE_CFG0);
2434 /*SUSP_CTRL has to be toggled to enable host PHY clock */
2435 val = readl(base + USB_SUSP_CTRL);
2436 val |= USB_SUSP_CLR;
2437 writel(val, base + USB_SUSP_CTRL);
2439 val = readl(base + USB_SUSP_CTRL);
2440 val &= ~USB_SUSP_CLR;
2441 writel(val, base + USB_SUSP_CTRL);
2443 val = readl(base + USB_USBMODE);
2444 val |= USB_USBMODE_HOST;
2445 writel(val, base + USB_USBMODE);
2447 /* Change the USB controller PHY type to HSIC */
2448 val = readl(base + HOSTPC1_DEVLC);
2449 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2450 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2451 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2452 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2453 val &= ~HOSTPC1_DEVLC_STS;
2454 writel(val, base + HOSTPC1_DEVLC);
2456 val = readl(base + USB_PORTSC);
2457 val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS);
2458 writel(val, base + USB_PORTSC);
2460 val = readl(base + UHSIC_TX_CFG0);
2461 val |= UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE;
2462 writel(val, base + UHSIC_TX_CFG0);
2464 val = readl(base + UHSIC_PADS_CFG0);
2465 /* Clear RTUNEP, SLEWP & SLEWN bit fields */
2466 val &= ~(UHSIC_TX_RTUNEP | UHSIC_TX_SLEWP | UHSIC_TX_SLEWN);
2467 /* set Rtune impedance to 50 ohm */
2468 #if defined(CONFIG_ARCH_TEGRA_13x_SOC)
2469 val |= UHSIC_TX_RTUNE_P(0x8);
2470 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2471 val |= UHSIC_TX_RTUNE_P(0xA);
2473 val |= UHSIC_TX_RTUNE_P(0xC);
2475 writel(val, base + UHSIC_PADS_CFG0);
2477 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2478 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2479 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2483 phy->phy_clk_on = true;
2484 phy->hw_accessible = true;
2486 if (!readl(base + USB_ASYNCLISTADDR))
2489 if (phy->pmc_sleepwalk) {
2490 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2492 uhsic_phy_restore_start(phy);
2493 usb_phy_bringup_host_controller(phy);
2494 uhsic_phy_restore_end(phy);
2495 phy->pmc_sleepwalk = false;
2498 val = readl(base + USB_TXFILLTUNING);
2499 if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2500 val = USB_FIFO_TXFILL_THRES(0x10);
2501 writel(val, base + USB_TXFILLTUNING);
2507 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2510 void __iomem *base = phy->regs;
2511 bool port_connected;
2512 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2514 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2515 if (!phy->phy_clk_on) {
2516 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2517 __func__, __LINE__, phy->inst);
2521 /* Disable interrupts */
2522 writel(0, base + USB_USBINTR);
2524 /* check for port connect status */
2525 val = readl(base + USB_PORTSC);
2526 port_connected = val & USB_PORTSC_CCS;
2528 if (phy->pmc_sleepwalk == false && port_connected) {
2529 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
2531 phy->pmc_remote_wakeup = false;
2532 phy->pmc_sleepwalk = true;
2534 val = readl(base + UHSIC_PMC_WAKEUP0);
2535 val |= EVENT_INT_ENB;
2536 writel(val, base + UHSIC_PMC_WAKEUP0);
2538 val = readl(base + USB_SUSP_CTRL);
2539 val &= ~USB_WAKE_ON_CNNT_EN_DEV;
2540 writel(val, base + USB_SUSP_CTRL);
2542 phy->pmc_sleepwalk = true;
2545 val = readl(base + HOSTPC1_DEVLC);
2546 val |= HOSTPC1_DEVLC_PHCD;
2547 writel(val, base + HOSTPC1_DEVLC);
2549 /* Remove power downs for HSIC from PADS CFG1 register */
2550 val = readl(base + UHSIC_PADS_CFG1);
2551 val |= (UHSIC_PD_BG | UHSIC_PD_TRK |
2552 UHSIC_PD_ZI | UHSIC_PD_TX);
2553 writel(val, base + UHSIC_PADS_CFG1);
2555 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2556 USB_PHY_CLK_VALID, 0, 2500))
2557 pr_warn("%s: timeout waiting for phy to disable\n", __func__);
2559 DBG("%s(%d) inst:[%d] End\n", __func__, __LINE__, phy->inst);
2561 phy->phy_clk_on = false;
2562 phy->hw_accessible = false;
2567 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2570 void __iomem *base = phy->regs;
2572 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2574 val = readl(base + USB_USBMODE);
2575 val |= USB_USBMODE_HOST;
2576 writel(val, base + USB_USBMODE);
2578 /* Change the USB controller PHY type to HSIC */
2579 val = readl(base + HOSTPC1_DEVLC);
2580 val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2581 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2582 val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2583 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2584 writel(val, base + HOSTPC1_DEVLC);
2586 val = readl(base + UHSIC_MISC_CFG0);
2587 val |= UHSIC_DETECT_SHORT_CONNECT;
2588 writel(val, base + UHSIC_MISC_CFG0);
2590 if (phy->pdata->ops && phy->pdata->ops->port_power)
2591 phy->pdata->ops->port_power();
2596 static struct tegra_usb_phy_ops utmi_phy_ops = {
2597 .init = _usb_phy_init,
2598 .reset = usb_phy_reset,
2599 .open = utmi_phy_open,
2600 .close = utmi_phy_close,
2601 .irq = utmi_phy_irq,
2602 .power_on = utmi_phy_power_on,
2603 .power_off = utmi_phy_power_off,
2604 .pre_resume = utmi_phy_pre_resume,
2605 .resume = utmi_phy_resume,
2606 .post_resume = utmi_phy_post_resume,
2607 .charger_detect = utmi_phy_charger_detect,
2608 .qc2_charger_detect = utmi_phy_qc2_charger_detect,
2609 .cdp_charger_detect = cdp_charger_detection,
2610 .nv_charger_detect = utmi_phy_nv_charger_detect,
2611 .maxim_charger_14675 = maxim_charger_detection,
2612 .apple_charger_1000ma_detect = utmi_phy_apple_charger_1000ma_detect,
2613 .apple_charger_2000ma_detect = utmi_phy_apple_charger_2000ma_detect,
2614 .apple_charger_500ma_detect = utmi_phy_apple_charger_500ma_detect,
2615 .pmc_disable = utmi_phy_pmc_disable,
2618 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2619 .init = _usb_phy_init,
2620 .reset = usb_phy_reset,
2621 .open = uhsic_phy_open,
2622 .close = uhsic_phy_close,
2623 .irq = uhsic_phy_irq,
2624 .power_on = uhsic_phy_power_on,
2625 .power_off = uhsic_phy_power_off,
2626 .pre_resume = uhsic_phy_pre_resume,
2627 .port_power = uhsic_phy_bus_port_power,
2630 static struct tegra_usb_phy_ops *phy_ops[] = {
2631 [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2632 [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2635 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
2637 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2639 phy->ops = phy_ops[phy->pdata->phy_intf];
2641 /* FIXME: uncommenting below line to make USB host mode fail*/
2642 /* pmc->pmc_ops->power_down_pmc(pmc); */