arch/arm/mach-tegra/board-ardbeg.c

   1 /*
   2  * arch/arm/mach-tegra/board-ardbeg.c
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/ctype.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/i2c-hid.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/delay.h>
  31 #include <linux/i2c-tegra.h>
  32 #include <linux/gpio.h>
  33 #include <linux/input.h>
  34 #include <linux/platform_data/tegra_usb.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/rm31080a_ts.h>
  37 #include <linux/maxim_sti.h>
  38 #include <linux/memblock.h>
  39 #include <linux/spi/spi-tegra.h>
  40 #include <linux/nfc/pn544.h>
  41 #include <linux/rfkill-gpio.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/ti_wilink_st.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/smb349-charger.h>
  46 #include <linux/max17048_battery.h>
  47 #include <linux/leds.h>
  48 #include <linux/i2c/at24.h>
  49 #include <linux/of_platform.h>
  50 #include <linux/i2c.h>
  51 #include <linux/i2c-tegra.h>
  52 #include <linux/platform_data/serial-tegra.h>
  53 #include <linux/edp.h>
  54 #include <linux/usb/tegra_usb_phy.h>
  55 #include <linux/mfd/palmas.h>
  56 #include <linux/clk/tegra.h>
  57 #include <linux/clocksource.h>
  58 #include <linux/irqchip.h>
  59 #include <linux/irqchip/tegra.h>
  60 #include <linux/tegra-soc.h>
  61 #include <linux/tegra_fiq_debugger.h>
  62 #include <linux/platform_data/tegra_usb_modem_power.h>
  63 #include <linux/platform_data/tegra_ahci.h>
  64 #include <linux/irqchip/tegra.h>
  65 #include <sound/max98090.h>
  66 #include <linux/pinctrl/pinctrl.h>
  67 #include <linux/pinctrl/consumer.h>
  68 #include <linux/pinctrl/pinconf-tegra.h>
  69
  70 #include <mach/irqs.h>
  71 #include <mach/io_dpd.h>
  72 #include <mach/i2s.h>
  73 #include <mach/isomgr.h>
  74 #include <mach/tegra_asoc_pdata.h>
  75 #include <mach/dc.h>
  76 #include <mach/tegra_usb_pad_ctrl.h>
  77
  78 #include <asm/mach-types.h>
  79 #include <asm/mach/arch.h>
  80 #include <mach/xusb.h>
  81
  82 #include "board.h"
  83 #include "board-ardbeg.h"
  84 #include "board-common.h"
  85 #include "board-panel.h"
  86 #include "board-touch-raydium.h"
  87 #include "board-touch-maxim_sti.h"
  88 #include "clock.h"
  89 #include "common.h"
  90 #include "devices.h"
  91 #include "gpio-names.h"
  92 #include "iomap.h"
  93 #include "pm.h"
  94 #include "tegra-board-id.h"
  95 #include "tegra-of-dev-auxdata.h"
  96
  97 static struct board_info board_info, display_board_info;
  98 #ifndef CONFIG_USE_OF
  99 static struct resource ardbeg_bluedroid_pm_resources[] = {
 100         [0] = {
 101                 .name   = "shutdown_gpio",
 102                 .start  = TEGRA_GPIO_PR1,
 103                 .end    = TEGRA_GPIO_PR1,
 104                 .flags  = IORESOURCE_IO,
 105         },
 106         [1] = {
 107                 .name = "host_wake",
 108                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 109         },
 110         [2] = {
 111                 .name = "gpio_ext_wake",
 112                 .start  = TEGRA_GPIO_PEE1,
 113                 .end    = TEGRA_GPIO_PEE1,
 114                 .flags  = IORESOURCE_IO,
 115         },
 116         [3] = {
 117                 .name = "gpio_host_wake",
 118                 .start  = TEGRA_GPIO_PU6,
 119                 .end    = TEGRA_GPIO_PU6,
 120                 .flags  = IORESOURCE_IO,
 121         },
 122         [4] = {
 123                 .name = "reset_gpio",
 124                 .start  = TEGRA_GPIO_PX1,
 125                 .end    = TEGRA_GPIO_PX1,
 126                 .flags  = IORESOURCE_IO,
 127         },
 128 };
 129
 130 static struct platform_device ardbeg_bluedroid_pm_device = {
 131         .name = "bluedroid_pm",
 132         .id             = 0,
 133         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
 134         .resource       = ardbeg_bluedroid_pm_resources,
 135 };
 136
 137 static noinline void __init ardbeg_setup_bluedroid_pm(void)
 138 {
 139         struct board_info board_info;
 140
 141         tegra_get_board_info(&board_info);
 142         if (board_info.board_id == BOARD_E2141)
 143                 ardbeg_bluedroid_pm_resources[0].name = "";
 144
 145         ardbeg_bluedroid_pm_resources[1].start =
 146                 ardbeg_bluedroid_pm_resources[1].end =
 147                                 gpio_to_irq(TEGRA_GPIO_PU6);
 148         platform_device_register(&ardbeg_bluedroid_pm_device);
 149 }
 150 #endif
 151 static struct i2c_board_info __initdata rt5639_board_info = {
 152         I2C_BOARD_INFO("rt5639", 0x1c),
 153 };
 154
 155 static struct max98090_eq_cfg max98090_eq_cfg[] = {
 156 };
 157
 158 static struct max98090_pdata norrin_max98090_pdata = {
 159         /* Equalizer Configuration */
 160         .eq_cfg = max98090_eq_cfg,
 161         .eq_cfgcnt = ARRAY_SIZE(max98090_eq_cfg),
 162
 163         /* Microphone Configuration */
 164         .digmic_left_mode = 1,
 165         .digmic_right_mode = 1,
 166 };
 167
 168 static struct i2c_board_info __initdata max98090_board_info = {
 169         I2C_BOARD_INFO("max98090", 0x10),
 170         .platform_data  = &norrin_max98090_pdata,
 171 };
 172
 173 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
 174         /* name         parent          rate            enabled */
 175         { "pll_m",      NULL,           0,              false},
 176         { "hda",        "pll_p",        108000000,      false},
 177         { "hda2codec_2x", "pll_p",      48000000,       false},
 178         { "pwm",        "pll_p",        48000000,       false},
 179         { "i2s1",       "pll_a_out0",   0,              false},
 180         { "i2s3",       "pll_a_out0",   0,              false},
 181         { "i2s4",       "pll_a_out0",   0,              false},
 182         { "spdif_out",  "pll_a_out0",   0,              false},
 183         { "d_audio",    "pll_a_out0",   12288000,       false},
 184         { "dam0",       "clk_m",        12000000,       false},
 185         { "dam1",       "clk_m",        12000000,       false},
 186         { "dam2",       "clk_m",        12000000,       false},
 187         { "audio1",     "i2s1_sync",    0,              false},
 188         { "audio3",     "i2s3_sync",    0,              false},
 189         { "vi_sensor",  "pll_p",        150000000,      false},
 190         { "vi_sensor2", "pll_p",        150000000,      false},
 191         { "cilab",      "pll_p",        150000000,      false},
 192         { "cilcd",      "pll_p",        150000000,      false},
 193         { "cile",       "pll_p",        150000000,      false},
 194         { "i2c1",       "pll_p",        3200000,        false},
 195         { "i2c2",       "pll_p",        3200000,        false},
 196         { "i2c3",       "pll_p",        3200000,        false},
 197         { "i2c4",       "pll_p",        3200000,        false},
 198         { "i2c5",       "pll_p",        3200000,        false},
 199         { "sbc1",       "pll_p",        25000000,       false},
 200         { "sbc2",       "pll_p",        25000000,       false},
 201         { "sbc3",       "pll_p",        25000000,       false},
 202         { "sbc4",       "pll_p",        25000000,       false},
 203         { "sbc5",       "pll_p",        25000000,       false},
 204         { "sbc6",       "pll_p",        25000000,       false},
 205         { "uarta",      "pll_p",        408000000,      false},
 206         { "uartb",      "pll_p",        408000000,      false},
 207         { "uartc",      "pll_p",        408000000,      false},
 208         { "uartd",      "pll_p",        408000000,      false},
 209         { NULL,         NULL,           0,              0},
 210 };
 211
 212 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
 213         .hid_descriptor_address = 0x0,
 214 };
 215
 216 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
 217         I2C_BOARD_INFO("hid", 0x3B),
 218         .platform_data  = &i2c_keyboard_pdata,
 219 };
 220
 221 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
 222         .hid_descriptor_address = 0x20,
 223 };
 224
 225 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
 226         I2C_BOARD_INFO("hid", 0x2C),
 227         .platform_data  = &i2c_touchpad_pdata,
 228 };
 229
 230 static void ardbeg_i2c_init(void)
 231 {
 232         struct board_info board_info;
 233         tegra_get_board_info(&board_info);
 234
 235         if (board_info.board_id == BOARD_PM374) {
 236                 i2c_register_board_info(0, &max98090_board_info, 1);
 237         } else if (board_info.board_id != BOARD_PM359)
 238                 i2c_register_board_info(0, &rt5639_board_info, 1);
 239
 240         if (board_info.board_id == BOARD_PM359 ||
 241                 board_info.board_id == BOARD_PM358 ||
 242                 board_info.board_id == BOARD_PM363 ||
 243                 board_info.board_id == BOARD_PM374) {
 244                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
 245                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
 246
 247                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
 248                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
 249         }
 250 }
 251
 252 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
 253         .gpio_hp_det = TEGRA_GPIO_HP_DET,
 254         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
 255         .gpio_spkr_en = -1,
 256         .gpio_int_mic_en = -1,
 257         .gpio_ext_mic_en = -1,
 258         .gpio_hp_mute = -1,
 259         .gpio_codec1 = -1,
 260         .gpio_codec2 = -1,
 261         .gpio_codec3 = -1,
 262         .i2s_param[HIFI_CODEC]       = {
 263                 .audio_port_id = 1,
 264                 .is_i2s_master = 1,
 265                 .i2s_mode = TEGRA_DAIFMT_I2S,
 266                 .sample_size    = 16,
 267                 .channels       = 2,
 268                 .bit_clk        = 1536000,
 269         },
 270         .i2s_param[BT_SCO] = {
 271                 .audio_port_id = 3,
 272                 .is_i2s_master = 1,
 273                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
 274         },
 275         .i2s_param[BASEBAND]    = {
 276                 .audio_port_id  = 0,
 277                 .is_i2s_master  = 1,
 278                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 279                 .sample_size    = 16,
 280                 .rate           = 16000,
 281                 .channels       = 2,
 282                 .bit_clk        = 1024000,
 283         },
 284 };
 285
 286 static struct tegra_asoc_platform_data norrin_audio_pdata_max98090 = {
 287         .gpio_hp_det            = NORRIN_GPIO_HP_DET,
 288         .gpio_ext_mic_en        = TEGRA_GPIO_HP_DET,
 289         .gpio_hp_mute           = -1,
 290         .edp_support            = true,
 291         .edp_states             = {1080, 842, 0},
 292         .i2s_param[HIFI_CODEC]  = {
 293                 .audio_port_id  = 1,
 294                 .is_i2s_master  = 1,
 295                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 296                 .sample_size    = 16,
 297                 .channels       = 2,
 298                 .bit_clk        = 1536000,
 299         },
 300         .i2s_param[BT_SCO]      = {
 301                 .audio_port_id  = 3,
 302                 .is_i2s_master  = 1,
 303                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 304                 .sample_size    = 16,
 305                 .channels       = 1,
 306                 .bit_clk        = 512000,
 307         },
 308 };
 309
 310 static void ardbeg_audio_init(void)
 311 {
 312         struct board_info board_info;
 313         tegra_get_board_info(&board_info);
 314         if (board_info.board_id == BOARD_PM359 ||
 315                         board_info.board_id == BOARD_PM358 ||
 316                         board_info.board_id == BOARD_PM370 ||
 317                         board_info.board_id == BOARD_PM374 ||
 318                         board_info.board_id == BOARD_PM375 ||
 319                         board_info.board_id == BOARD_PM363) {
 320                 /*Laguna*/
 321                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_HP_DET;
 322                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 1;
 323                 if (board_info.board_id != BOARD_PM363)
 324                         ardbeg_audio_pdata_rt5639.gpio_ldo1_en = -1;
 325         } else {
 326                 /*Ardbeg*/
 327
 328                 if (board_info.board_id == BOARD_E1762 ||
 329                         board_info.board_id == BOARD_P1761 ||
 330                         board_info.board_id == BOARD_E1922) {
 331                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 332                                 TEGRA_GPIO_CDC_IRQ;
 333                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 334                 } else {
 335                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 336                                 TEGRA_GPIO_HP_DET;
 337                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = false;
 338                 }
 339                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 340                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 341         }
 342
 343         if (board_info.board_id == BOARD_E1971) {
 344                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_CDC_IRQ;
 345                 ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 346                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 347                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 348         }
 349
 350         if (board_info.board_id == BOARD_E2141) {
 351                 ardbeg_audio_pdata_rt5639.i2s_param[HIFI_CODEC].audio_port_id
 352                                 = 0;
 353                 ardbeg_audio_pdata_rt5639.i2s_param[BT_SCO].audio_port_id = 1;
 354         }
 355         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
 356         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
 357
 358         norrin_audio_pdata_max98090.codec_name = "max98090.0-0010";
 359         norrin_audio_pdata_max98090.codec_dai_name = "HiFi";
 360 }
 361
 362 static struct platform_device ardbeg_audio_device_rt5639 = {
 363         .name = "tegra-snd-rt5639",
 364         .id = 0,
 365         .dev = {
 366                 .platform_data = &ardbeg_audio_pdata_rt5639,
 367         },
 368 };
 369
 370 static struct platform_device norrin_audio_device_max98090 = {
 371         .name   = "tegra-snd-max98090",
 372         .id     = 0,
 373         .dev    = {
 374                 .platform_data = &norrin_audio_pdata_max98090,
 375         },
 376 };
 377
 378 static struct platform_device *ardbeg_devices[] __initdata = {
 379         &tegra_rtc_device,
 380 #if !defined(CONFIG_ARM64)
 381         &tegra_udc_device,
 382 #endif
 383 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
 384         &tegra12_se_device,
 385 #endif
 386         &tegra_ahub_device,
 387         &tegra_dam_device0,
 388         &tegra_dam_device1,
 389         &tegra_dam_device2,
 390         &tegra_i2s_device0,
 391         &tegra_i2s_device1,
 392         &tegra_i2s_device3,
 393         &tegra_i2s_device4,
 394         &tegra_spdif_device,
 395         &spdif_dit_device,
 396         &bluetooth_dit_device,
 397         &baseband_dit_device,
 398         &tegra_offload_device,
 399         &tegra30_avp_audio_device,
 400 };
 401
 402 static struct tegra_usb_platform_data tegra_udc_pdata = {
 403         .port_otg = true,
 404         .has_hostpc = true,
 405         .unaligned_dma_buf_supported = false,
 406         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 407         .op_mode = TEGRA_USB_OPMODE_DEVICE,
 408         .u_data.dev = {
 409                 .vbus_pmu_irq = 0,
 410                 .charging_supported = true,
 411                 .remote_wakeup_supported = false,
 412         },
 413         .u_cfg.utmi = {
 414                 .hssync_start_delay = 0,
 415                 .elastic_limit = 16,
 416                 .idle_wait_delay = 17,
 417                 .term_range_adj = 6,
 418                 .xcvr_setup = 8,
 419                 .xcvr_lsfslew = 2,
 420                 .xcvr_lsrslew = 2,
 421                 .xcvr_setup_offset = 0,
 422                 .xcvr_use_fuses = 1,
 423         },
 424 };
 425
 426 #if !defined(CONFIG_ARM64)
 427 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
 428         .port_otg = true,
 429         .has_hostpc = true,
 430         .unaligned_dma_buf_supported = true,
 431         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 432         .op_mode = TEGRA_USB_OPMODE_HOST,
 433         .u_data.host = {
 434                 .hot_plug = false,
 435                 .remote_wakeup_supported = true,
 436                 .power_off_on_suspend = true,
 437         },
 438         .u_cfg.utmi = {
 439                 .hssync_start_delay = 0,
 440                 .elastic_limit = 16,
 441                 .idle_wait_delay = 17,
 442                 .term_range_adj = 6,
 443                 .xcvr_setup = 15,
 444                 .xcvr_lsfslew = 0,
 445                 .xcvr_lsrslew = 3,
 446                 .xcvr_setup_offset = 0,
 447                 .xcvr_use_fuses = 1,
 448                 .vbus_oc_map = 0x4,
 449                 .xcvr_hsslew_lsb = 2,
 450         },
 451 };
 452
 453 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
 454         .port_otg = false,
 455         .has_hostpc = true,
 456         .unaligned_dma_buf_supported = true,
 457         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 458         .op_mode = TEGRA_USB_OPMODE_HOST,
 459         .u_data.host = {
 460                 .hot_plug = false,
 461                 .remote_wakeup_supported = true,
 462                 .power_off_on_suspend = true,
 463         },
 464         .u_cfg.utmi = {
 465                 .hssync_start_delay = 0,
 466                 .elastic_limit = 16,
 467                 .idle_wait_delay = 17,
 468                 .term_range_adj = 6,
 469                 .xcvr_setup = 8,
 470                 .xcvr_lsfslew = 2,
 471                 .xcvr_lsrslew = 2,
 472                 .xcvr_setup_offset = 0,
 473                 .xcvr_use_fuses = 1,
 474                 .vbus_oc_map = 0x5,
 475         },
 476 };
 477
 478 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
 479         .port_otg = false,
 480         .has_hostpc = true,
 481         .unaligned_dma_buf_supported = true,
 482         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 483         .op_mode = TEGRA_USB_OPMODE_HOST,
 484         .u_data.host = {
 485                 .hot_plug = false,
 486                 .remote_wakeup_supported = true,
 487                 .power_off_on_suspend = true,
 488         },
 489         .u_cfg.utmi = {
 490         .hssync_start_delay = 0,
 491                 .elastic_limit = 16,
 492                 .idle_wait_delay = 17,
 493                 .term_range_adj = 6,
 494                 .xcvr_setup = 8,
 495                 .xcvr_lsfslew = 2,
 496                 .xcvr_lsrslew = 2,
 497                 .xcvr_setup_offset = 0,
 498                 .xcvr_use_fuses = 1,
 499                 .vbus_oc_map = 0x5,
 500         },
 501 };
 502
 503 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
 504         .port_otg = false,
 505         .has_hostpc = true,
 506         .unaligned_dma_buf_supported = true,
 507         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 508         .op_mode        = TEGRA_USB_OPMODE_HOST,
 509         .u_data.host = {
 510                 .hot_plug = false,
 511                 .remote_wakeup_supported = true,
 512                 .power_off_on_suspend = true,
 513         },
 514 };
 515
 516 static struct tegra_usb_otg_data tegra_otg_pdata = {
 517         .ehci_device = &tegra_ehci1_device,
 518         .ehci_pdata = &tegra_ehci1_utmi_pdata,
 519 };
 520
 521 #else
 522 static struct tegra_usb_otg_data tegra_otg_pdata;
 523 #endif
 524
 525 static void ardbeg_usb_init(void)
 526 {
 527 #if !defined(CONFIG_ARM64)
 528         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 529         int modem_id = tegra_get_modem_id();
 530 #endif
 531         struct board_info bi;
 532         tegra_get_pmu_board_info(&bi);
 533
 534 #if !defined(CONFIG_ARM64)
 535         if (board_info.sku == 1100 || board_info.board_id == BOARD_P1761 ||
 536                                         board_info.board_id == BOARD_E1784)
 537                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
 538
 539         if (board_info.board_id == BOARD_PM359 ||
 540                         board_info.board_id == BOARD_PM358 ||
 541                         board_info.board_id == BOARD_PM370 ||
 542                         board_info.board_id == BOARD_PM374 ||
 543                         board_info.board_id == BOARD_PM375 ||
 544                         board_info.board_id == BOARD_PM363) {
 545                 /* Laguna */
 546                 /* Host cable is detected through AMS PMU Interrupt */
 547                 if (board_info.major_revision >= 'A' &&
 548                         board_info.major_revision <= 'D' &&
 549                         board_info.board_id == BOARD_PM375) {
 550                         tegra_udc_pdata.id_det_type = TEGRA_USB_VIRTUAL_ID;
 551                         tegra_ehci1_utmi_pdata.id_det_type =
 552                                                 TEGRA_USB_VIRTUAL_ID;
 553                 } else {
 554                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 555                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 556                 }
 557                 tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
 558         } else {
 559                 /* Ardbeg and TN8 */
 560
 561                 /*
 562                  * TN8 supports vbus changing and it can handle
 563                  * vbus voltages larger then 5V.  Enable this.
 564                  */
 565                 if (board_info.board_id == BOARD_P1761 ||
 566                         board_info.board_id == BOARD_E1784 ||
 567                         board_info.board_id == BOARD_E1780) {
 568
 569                         /*
 570                          * Set the maximum voltage that can be supplied
 571                          * over USB vbus that the board supports if we use
 572                          * a quick charge 2 wall charger.
 573                          */
 574                         tegra_udc_pdata.qc2_voltage = TEGRA_USB_QC2_9V;
 575                         tegra_udc_pdata.u_data.dev.qc2_current_limit_ma = 1200;
 576
 577                         /* charger needs to be set to 2A - h/w will do 1.8A */
 578                         tegra_udc_pdata.u_data.dev.dcp_current_limit_ma = 2000;
 579                 }
 580
 581                 switch (bi.board_id) {
 582                 case BOARD_E1733:
 583                         /* Host cable is detected through PMU Interrupt */
 584                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 585                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 586                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 587                                                          "as3722-extcon";
 588                         break;
 589                 case BOARD_E1736:
 590                 case BOARD_E1769:
 591                 case BOARD_E1735:
 592                 case BOARD_E1936:
 593                 case BOARD_P1761:
 594                         /* Device cable is detected through PMU Interrupt */
 595                         tegra_udc_pdata.support_pmu_vbus = true;
 596                         tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
 597                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
 598                         tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
 599                                                          "palmas-extcon";
 600                         /* Host cable is detected through PMU Interrupt */
 601                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 602                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 603                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 604                                                          "palmas-extcon";
 605                 }
 606
 607                 /* Enable Y-Cable support */
 608                 if (bi.board_id == BOARD_P1761)
 609                         tegra_ehci1_utmi_pdata.u_data.host.support_y_cable =
 610                                                         true;
 611         }
 612
 613         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
 614                 tegra_otg_pdata.is_xhci = false;
 615                 tegra_udc_pdata.u_data.dev.is_xhci = false;
 616         } else {
 617                 tegra_otg_pdata.is_xhci = true;
 618                 tegra_udc_pdata.u_data.dev.is_xhci = true;
 619         }
 620
 621         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
 622         platform_device_register(&tegra_otg_device);
 623 #endif
 624
 625         /* Setup the udc platform data */
 626         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
 627 #if !defined(CONFIG_ARM64)
 628         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 629                 if (!modem_id) {
 630                         if ((bi.board_id != BOARD_P1761) &&
 631                             (bi.board_id != BOARD_E1922) &&
 632                             (bi.board_id != BOARD_E1784)) {
 633                                 tegra_ehci2_device.dev.platform_data =
 634                                         &tegra_ehci2_utmi_pdata;
 635                                 platform_device_register(&tegra_ehci2_device);
 636                         }
 637                 }
 638         }
 639
 640         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 641                 if ((bi.board_id != BOARD_P1761) &&
 642                     (bi.board_id != BOARD_E1922) &&
 643                     (bi.board_id != BOARD_E1784)) {
 644                         tegra_ehci3_device.dev.platform_data =
 645                                 &tegra_ehci3_utmi_pdata;
 646                         platform_device_register(&tegra_ehci3_device);
 647                 }
 648         }
 649 #endif
 650 }
 651
 652 static struct tegra_xusb_platform_data xusb_pdata = {
 653         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
 654                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
 655 };
 656
 657 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
 658 static void ardbeg_xusb_init(void)
 659 {
 660         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 661
 662         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
 663
 664         if (board_info.board_id == BOARD_PM358 ||
 665                         board_info.board_id == BOARD_PM374 ||
 666                         board_info.board_id == BOARD_PM370 ||
 667                         board_info.board_id == BOARD_PM363) {
 668                 if (board_info.board_id == BOARD_PM374 ||
 669                         board_info.board_id == BOARD_PM370)
 670                         pr_info("Norrin. 0x%x\n", board_info.board_id);
 671                 else
 672                         pr_info("Laguna. 0x%x\n", board_info.board_id);
 673
 674                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 675                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 676                                 TEGRA_XUSB_SS_P0);
 677
 678                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 679                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 680                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
 681
 682                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 683         } else if (board_info.board_id == BOARD_PM359) {
 684                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 685                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 686                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 687                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
 688                                 TEGRA_XUSB_SS_P0 | TEGRA_XUSB_SS_P1 |
 689                                 TEGRA_XUSB_USB2_P1);
 690         } else if (board_info.board_id == BOARD_PM375) {
 691                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 692                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 693                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 694                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
 695                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0);
 696                 xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);
 697         } else {
 698                 /* Ardbeg */
 699                 if (board_info.board_id == BOARD_E1781) {
 700                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
 701                         /* Shield ERS-S */
 702                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 703                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 704
 705                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 706                                 xusb_pdata.portmap &= ~(
 707                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
 708                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 709                 } else {
 710                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
 711                         /* Shield ERS */
 712                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 713                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 714                                         TEGRA_XUSB_SS_P0);
 715
 716                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 717                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 718                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 719                 }
 720                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 721         }
 722
 723         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
 724                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
 725
 726         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
 727                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
 728 }
 729 #endif
 730
 731 static void ardbeg_modem_init(void)
 732 {
 733 #if !defined(CONFIG_ARM64)
 734         int modem_id = tegra_get_modem_id();
 735         struct board_info board_info;
 736         struct board_info pmu_board_info;
 737         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 738
 739         tegra_get_board_info(&board_info);
 740         tegra_get_pmu_board_info(&pmu_board_info);
 741         pr_info("%s: modem_id = %d\n", __func__, modem_id);
 742
 743         switch (modem_id) {
 744         case TEGRA_BB_BRUCE:
 745                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 746                         /* Set specific USB wake source for Ardbeg */
 747                         if (board_info.board_id == BOARD_E1780)
 748                                 tegra_set_wake_source(42, INT_USB2);
 749                 }
 750                 break;
 751         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
 752                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 753                         tegra_ehci2_device.dev.platform_data =
 754                                 &tegra_ehci2_hsic_smsc_hub_pdata;
 755                         /* Set specific USB wake source for Ardbeg */
 756                         if (board_info.board_id == BOARD_E1780)
 757                                 tegra_set_wake_source(42, INT_USB2);
 758                         platform_device_register(&tegra_ehci2_device);
 759                 } else
 760                         xusb_pdata.pretend_connect_0 = true;
 761                 break;
 762         default:
 763                 return;
 764         }
 765 #endif
 766 }
 767
 768 #ifdef CONFIG_USE_OF
 769 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
 770         T124_SPI_OF_DEV_AUXDATA,
 771         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
 772                                 NULL),
 773         OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
 774         OF_DEV_AUXDATA("nvidia,tegra132-dtv", 0x7000c300, "dtv", NULL),
 775         OF_DEV_AUXDATA("nvidia,tegra124-dtv", 0x7000c300, "dtv", NULL),
 776 #if defined(CONFIG_ARM64)
 777         OF_DEV_AUXDATA("nvidia,tegra132-udc", 0x7d000000, "tegra-udc.0",
 778                         &tegra_udc_pdata.u_data.dev),
 779         OF_DEV_AUXDATA("nvidia,tegra132-otg", 0x7d000000, "tegra-otg",
 780                         &tegra_otg_pdata),
 781         OF_DEV_AUXDATA("nvidia,tegra132-ehci", 0x7d004000, "tegra-ehci.1",
 782                         NULL),
 783         OF_DEV_AUXDATA("nvidia,tegra132-ehci", 0x7d008000, "tegra-ehci.2",
 784                         NULL),
 785 #endif
 786         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
 787                 NULL),
 788         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
 789                 "gk20a.0", NULL),
 790 #ifdef CONFIG_ARCH_TEGRA_VIC
 791         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
 792 #endif
 793         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
 794                 NULL),
 795 #ifdef CONFIG_VI_ONE_DEVICE
 796         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
 797 #else
 798         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
 799 #endif
 800         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
 801         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
 802         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
 803         T124_UART_OF_DEV_AUXDATA,
 804         T124_I2C_OF_DEV_AUXDATA,
 805         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
 806                                 &xusb_pdata),
 807         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
 808                 NULL),
 809         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
 810                 NULL),
 811         OF_DEV_AUXDATA("nvidia,tegra124-nvavp", 0x60001000, "nvavp",
 812                                 NULL),
 813         OF_DEV_AUXDATA("nvidia,tegra124-pwm", 0x7000a000, "tegra-pwm", NULL),
 814         OF_DEV_AUXDATA("nvidia,tegra124-dfll", 0x70110000, "tegra_cl_dvfs",
 815                 NULL),
 816         OF_DEV_AUXDATA("nvidia,tegra132-dfll", 0x70040084, "tegra_cl_dvfs",
 817                 NULL),
 818         OF_DEV_AUXDATA("nvidia,tegra124-efuse", TEGRA_FUSE_BASE, "tegra-fuse",
 819                 NULL),
 820         OF_DEV_AUXDATA("nvidia,tegra124-camera", 0, "pcl-generic",
 821                                 NULL),
 822         OF_DEV_AUXDATA("nvidia,tegra124-ahci-sata", 0x70027000, "tegra-sata.0",
 823                 NULL),
 824         OF_DEV_AUXDATA("nvidia,tegra-bluedroid_pm", 0, "bluedroid_pm",
 825                 NULL),
 826         OF_DEV_AUXDATA("pwm-backlight", 0, "pwm-backlight", NULL),
 827 #ifdef CONFIG_TEGRA_CEC_SUPPORT
 828         OF_DEV_AUXDATA("nvidia,tegra124-cec", 0x70015000, "tegra_cec", NULL),
 829 #endif
 830         OF_DEV_AUXDATA("nvidia,icera-i500", 0, "tegra_usb_modem_power", NULL),
 831         OF_DEV_AUXDATA("nvidia,ptm", 0x7081c000, "ptm", NULL),
 832         OF_DEV_AUXDATA("nvidia,tegra30-hda", 0x70030000, "tegra30-hda", NULL),
 833         {}
 834 };
 835 #endif
 836
 837 struct maxim_sti_pdata maxim_sti_pdata = {
 838         .touch_fusion         = "/vendor/bin/touch_fusion",
 839         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 840         .fw_name              = "maxim_fp35.bin",
 841         .nl_family            = TF_FAMILY_NAME,
 842         .nl_mc_groups         = 5,
 843         .chip_access_method   = 2,
 844         .default_reset_state  = 0,
 845         .tx_buf_size          = 4100,
 846         .rx_buf_size          = 4100,
 847         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 848         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 849 };
 850
 851 struct maxim_sti_pdata maxim_sti_pdata_rd = {
 852         .touch_fusion         = "/vendor/bin/touch_fusion_rd",
 853         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 854         .fw_name              = "maxim_fp35.bin",
 855         .nl_family            = TF_FAMILY_NAME,
 856         .nl_mc_groups         = 5,
 857         .chip_access_method   = 2,
 858         .default_reset_state  = 0,
 859         .tx_buf_size          = 4100,
 860         .rx_buf_size          = 4100,
 861         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 862         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 863 };
 864
 865 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
 866         .rx_clk_tap_delay = 0,
 867         .is_hw_based_cs = true,
 868         .tx_clk_tap_delay = 0,
 869 };
 870
 871 struct spi_board_info maxim_sti_spi_board = {
 872         .modalias = MAXIM_STI_NAME,
 873         .bus_num = TOUCH_SPI_ID,
 874         .chip_select = TOUCH_SPI_CS,
 875         .max_speed_hz = 12 * 1000 * 1000,
 876         .mode = SPI_MODE_0,
 877         .platform_data = &maxim_sti_pdata,
 878         .controller_data = &maxim_dev_cdata,
 879 };
 880
 881 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
 882         /* name         parent          rate            enabled */
 883         { "extern2",    "pll_p",        41000000,       false},
 884         { "clk_out_2",  "extern2",      40800000,       false},
 885         { NULL,         NULL,           0,              0},
 886 };
 887
 888 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
 889         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 890         .config = 0,
 891         .platform_id = RM_PLATFORM_A010,
 892         .name_of_clock = "clk_out_2",
 893         .name_of_clock_con = "extern2",
 894 };
 895
 896 static struct rm_spi_ts_platform_data rm31080ts_tn8_data = {
 897         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 898         .config = 0,
 899         .platform_id = RM_PLATFORM_T008,
 900         .name_of_clock = "clk_out_2",
 901         .name_of_clock_con = "extern2",
 902 };
 903
 904 static struct rm_spi_ts_platform_data rm31080ts_tn8_p1765_data = {
 905         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 906         .config = 0,
 907         .platform_id = RM_PLATFORM_T008_2,
 908         .name_of_clock = "clk_out_2",
 909         .name_of_clock_con = "extern2",
 910 };
 911
 912 static struct rm_spi_ts_platform_data rm31080ts_norrin_data = {
 913         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 914         .config = 0,
 915         .platform_id = RM_PLATFORM_P140,
 916         .name_of_clock = "clk_out_2",
 917         .name_of_clock_con = "extern2",
 918 };
 919
 920 struct rm_spi_ts_platform_data rm31080ts_t132loki_data = {
 921         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 922         .config = 0,
 923         .platform_id = RM_PLATFORM_L005,
 924         .name_of_clock = "clk_out_2",
 925         .name_of_clock_con = "extern2",
 926 };
 927
 928 struct rm_spi_ts_platform_data rm31080ts_t132loki_data_jdi_5 = {
 929         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 930         .config = 0,
 931         .platform_id = RM_PLATFORM_L005,
 932         .name_of_clock = "clk_out_2",
 933         .name_of_clock_con = "extern2",
 934         .gpio_sensor_select0 = false,
 935         .gpio_sensor_select1 = true,
 936 };
 937
 938 static struct rm_spi_ts_platform_data rm31080ts_e2141_data = {
 939         .gpio_reset = E2141_TOUCH_GPIO_RST_RAYDIUM_SPI,
 940         .config = 0,
 941         .platform_id = RM_PLATFORM_T008,
 942         .name_of_clock = "clk_out_2",
 943         .name_of_clock_con = "extern2",
 944 };
 945
 946 static struct tegra_spi_device_controller_data dev_cdata = {
 947         .rx_clk_tap_delay = 0,
 948         .tx_clk_tap_delay = 16,
 949 };
 950
 951 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
 952         {
 953                 .modalias = "rm_ts_spidev",
 954                 .bus_num = TOUCH_SPI_ID,
 955                 .chip_select = TOUCH_SPI_CS,
 956                 .max_speed_hz = 12 * 1000 * 1000,
 957                 .mode = SPI_MODE_0,
 958                 .controller_data = &dev_cdata,
 959                 .platform_data = &rm31080ts_ardbeg_data,
 960         },
 961 };
 962
 963 static struct spi_board_info rm31080a_tn8_spi_board[1] = {
 964         {
 965                 .modalias = "rm_ts_spidev",
 966                 .bus_num = TOUCH_SPI_ID,
 967                 .chip_select = TOUCH_SPI_CS,
 968                 .max_speed_hz = 18 * 1000 * 1000,
 969                 .mode = SPI_MODE_0,
 970                 .controller_data = &dev_cdata,
 971                 .platform_data = &rm31080ts_tn8_data,
 972         },
 973 };
 974
 975 static struct spi_board_info rm31080a_tn8_p1765_spi_board[1] = {
 976         {
 977                 .modalias = "rm_ts_spidev",
 978                 .bus_num = TOUCH_SPI_ID,
 979                 .chip_select = TOUCH_SPI_CS,
 980                 .max_speed_hz = 18 * 1000 * 1000,
 981                 .mode = SPI_MODE_0,
 982                 .controller_data = &dev_cdata,
 983                 .platform_data = &rm31080ts_tn8_p1765_data,
 984         },
 985 };
 986
 987 static struct spi_board_info rm31080a_norrin_spi_board[1] = {
 988         {
 989                 .modalias = "rm_ts_spidev",
 990                 .bus_num = NORRIN_TOUCH_SPI_ID,
 991                 .chip_select = NORRIN_TOUCH_SPI_CS,
 992                 .max_speed_hz = 12 * 1000 * 1000,
 993                 .mode = SPI_MODE_0,
 994                 .controller_data = &dev_cdata,
 995                 .platform_data = &rm31080ts_norrin_data,
 996         },
 997 };
 998
 999 static struct spi_board_info rm31080a_e2141_spi_board[1] = {
1000         {
1001                 .modalias = "rm_ts_spidev",
1002                 .bus_num = E2141_TOUCH_SPI_ID,
1003                 .chip_select = TOUCH_SPI_CS,
1004                 .max_speed_hz = 12 * 1000 * 1000,
1005                 .mode = SPI_MODE_0,
1006                 .controller_data = &dev_cdata,
1007                 .platform_data = &rm31080ts_e2141_data,
1008         },
1009 };
1010
1011 static int __init ardbeg_touch_init(void)
1012 {
1013         tegra_get_board_info(&board_info);
1014
1015         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1016                 pr_info("%s init maxim touch\n", __func__);
1017 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1018         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1019                 if (tegra_get_touch_panel_id() == TOUCHPANEL_TN7)
1020                         maxim_sti_spi_board.platform_data = &maxim_sti_pdata_rd;
1021                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1022 #endif
1023         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1024                 pr_info("%s init raydium touch\n", __func__);
1025                 tegra_clk_init_from_table(touch_clk_init_table);
1026                 if (board_info.board_id == BOARD_PM374) {
1027                         rm31080a_norrin_spi_board[0].irq =
1028                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1029                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1030                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1031                                         &rm31080ts_norrin_data,
1032                                         &rm31080a_norrin_spi_board[0],
1033                                         ARRAY_SIZE(rm31080a_norrin_spi_board));
1034                 } else if ((board_info.board_id == BOARD_P2530) ||
1035                         (board_info.board_id == BOARD_E2548)) {
1036                         if (board_info.sku == BOARD_SKU_FOSTER)
1037                                 return 0;
1038                         if (tegra_get_touch_panel_id() == TOUCHPANEL_LOKI_JDI5)
1039                                 rm31080a_ardbeg_spi_board[0].platform_data =
1040                                         &rm31080ts_t132loki_data_jdi_5;
1041                         else
1042                                 rm31080a_ardbeg_spi_board[0].platform_data =
1043                                         &rm31080ts_t132loki_data;
1044                         if (board_info.fab >= 0xa3) {
1045                                 rm31080ts_t132loki_data.name_of_clock = NULL;
1046                                 rm31080ts_t132loki_data.name_of_clock_con = NULL;
1047                         } else
1048                                 tegra_clk_init_from_table(touch_clk_init_table);
1049                                 rm31080a_ardbeg_spi_board[0].irq =
1050                                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1051                                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1052                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1053                                         &rm31080ts_t132loki_data,
1054                                         &rm31080a_ardbeg_spi_board[0],
1055                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1056                 } else if (board_info.board_id == BOARD_P1761) {
1057                         rm31080a_tn8_spi_board[0].irq =
1058                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1059                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1060                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1061                                 &rm31080ts_tn8_data,
1062                                 &rm31080a_tn8_spi_board[0],
1063                                 ARRAY_SIZE(rm31080a_tn8_spi_board));
1064                 } else if (board_info.board_id == BOARD_P1765) {
1065                         rm31080a_tn8_p1765_spi_board[0].irq =
1066                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1067                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1068                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1069                                 &rm31080ts_tn8_p1765_data,
1070                                 &rm31080a_tn8_p1765_spi_board[0],
1071                                 ARRAY_SIZE(rm31080a_tn8_p1765_spi_board));
1072                 } else if (board_info.board_id == BOARD_E2141) {
1073                         rm31080a_e2141_spi_board[0].irq =
1074                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1075                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1076                                 E2141_TOUCH_GPIO_RST_RAYDIUM_SPI,
1077                                 &rm31080ts_e2141_data,
1078                                 &rm31080a_e2141_spi_board[0],
1079                                 ARRAY_SIZE(rm31080a_e2141_spi_board));
1080                 } else {
1081                         rm31080a_ardbeg_spi_board[0].irq =
1082                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1083                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1084                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1085                                         &rm31080ts_ardbeg_data,
1086                                         &rm31080a_ardbeg_spi_board[0],
1087                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1088                 }
1089         }
1090         return 0;
1091 }
1092
1093 static void __init ardbeg_sysedp_init(void)
1094 {
1095         struct board_info bi;
1096
1097         tegra_get_board_info(&bi);
1098
1099         switch (bi.board_id) {
1100         case BOARD_E1780:
1101                 if (bi.sku == 1100) {
1102                         tn8_new_sysedp_init();
1103                 }
1104                 else
1105                         shield_new_sysedp_init();
1106                 break;
1107         case BOARD_E1971:
1108         case BOARD_E1922:
1109         case BOARD_E1784:
1110         case BOARD_P1761:
1111         case BOARD_P1765:
1112                 tn8_new_sysedp_init();
1113                 break;
1114         case BOARD_PM358:
1115         case BOARD_PM359:
1116         case BOARD_PM375:
1117         default:
1118                 break;
1119         }
1120 }
1121
1122 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1123 {
1124         struct board_info bi;
1125
1126         tegra_get_board_info(&bi);
1127
1128         switch (bi.board_id) {
1129         case BOARD_E1780:
1130                 if (bi.sku == 1100)
1131                         tn8_sysedp_dynamic_capping_init();
1132                 else
1133                         shield_sysedp_dynamic_capping_init();
1134                 break;
1135         case BOARD_E1971:
1136         case BOARD_E1922:
1137         case BOARD_E1784:
1138         case BOARD_P1761:
1139         case BOARD_P1765:
1140                 tn8_sysedp_dynamic_capping_init();
1141                 break;
1142         case BOARD_PM358:
1143         case BOARD_PM359:
1144         case BOARD_PM375:
1145         default:
1146                 break;
1147         }
1148 }
1149
1150 static void __init ardbeg_sysedp_batmon_init(void)
1151 {
1152         struct board_info bi;
1153
1154         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1155                 return;
1156
1157         tegra_get_board_info(&bi);
1158
1159         switch (bi.board_id) {
1160         case BOARD_E1780:
1161                 if (bi.sku != 1100)
1162                         shield_sysedp_batmon_init();
1163                 break;
1164         case BOARD_PM358:
1165         case BOARD_PM359:
1166         case BOARD_PM375:
1167         default:
1168                 break;
1169         }
1170 }
1171
1172
1173
1174 static void __init edp_init(void)
1175 {
1176         struct board_info bi;
1177
1178         tegra_get_board_info(&bi);
1179
1180         switch (bi.board_id) {
1181         case BOARD_E1780:
1182                 if (bi.sku == 1100)
1183                         tn8_edp_init();
1184                 else
1185                         ardbeg_edp_init();
1186                 break;
1187         case BOARD_P1761:
1188                         tn8_edp_init();
1189                         break;
1190         case BOARD_PM358:
1191         case BOARD_PM359:
1192         case BOARD_PM375:
1193                         laguna_edp_init();
1194                         break;
1195         case BOARD_P2530:
1196         case BOARD_E2548:
1197                         loki_edp_init();
1198                         break;
1199         default:
1200                         ardbeg_edp_init();
1201                         break;
1202         }
1203 }
1204
1205 static void __init tegra_ardbeg_early_init(void)
1206 {
1207         ardbeg_sysedp_init();
1208         tegra_clk_init_from_table(ardbeg_clk_init_table);
1209         tegra_clk_verify_parents();
1210         if (of_machine_is_compatible("nvidia,jetson-tk1"))
1211                 tegra_soc_device_init("jetson-tk1");
1212         else if (of_machine_is_compatible("nvidia,laguna"))
1213                 tegra_soc_device_init("laguna");
1214         else if (of_machine_is_compatible("nvidia,tn8"))
1215                 tegra_soc_device_init("tn8");
1216         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1217                 tegra_soc_device_init("ardbeg_sata");
1218         else if (of_machine_is_compatible("nvidia,norrin"))
1219                 tegra_soc_device_init("norrin");
1220         else if (of_machine_is_compatible("nvidia,bowmore"))
1221                 tegra_soc_device_init("bowmore");
1222         else if (of_machine_is_compatible("nvidia,t132loki"))
1223                 tegra_soc_device_init("t132loki");
1224         else if (of_machine_is_compatible("nvidia,e2141"))
1225                 tegra_soc_device_init("e2141");
1226         else
1227                 tegra_soc_device_init("ardbeg");
1228 }
1229
1230 static struct tegra_io_dpd pexbias_io = {
1231         .name                   = "PEX_BIAS",
1232         .io_dpd_reg_index       = 0,
1233         .io_dpd_bit             = 4,
1234 };
1235 static struct tegra_io_dpd pexclk1_io = {
1236         .name                   = "PEX_CLK1",
1237         .io_dpd_reg_index       = 0,
1238         .io_dpd_bit             = 5,
1239 };
1240 static struct tegra_io_dpd pexclk2_io = {
1241         .name                   = "PEX_CLK2",
1242         .io_dpd_reg_index       = 0,
1243         .io_dpd_bit             = 6,
1244 };
1245
1246 static void __init tegra_ardbeg_late_init(void)
1247 {
1248         struct board_info board_info;
1249         tegra_get_board_info(&board_info);
1250         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1251                 board_info.board_id, board_info.sku,
1252                 board_info.fab, board_info.major_revision,
1253                 board_info.minor_revision);
1254
1255 #ifndef CONFIG_MACH_EXUMA
1256         ardbeg_display_init();
1257 #endif
1258         ardbeg_usb_init();
1259         ardbeg_modem_init();
1260 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
1261         ardbeg_xusb_init();
1262 #endif
1263         ardbeg_i2c_init();
1264         ardbeg_audio_init();
1265         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1266         if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
1267                 platform_device_register(&norrin_audio_device_max98090);
1268         else if (board_info.board_id != BOARD_PM359)
1269                 platform_device_register(&ardbeg_audio_device_rt5639);
1270         tegra_io_dpd_init();
1271         if (board_info.board_id == BOARD_E2548 ||
1272                         board_info.board_id == BOARD_P2530)
1273                 loki_sdhci_init();
1274         else
1275                 ardbeg_sdhci_init();
1276         if (board_info.board_id == BOARD_PM359 ||
1277                         board_info.board_id == BOARD_PM358 ||
1278                         board_info.board_id == BOARD_PM370 ||
1279                         board_info.board_id == BOARD_PM375 ||
1280                         board_info.board_id == BOARD_PM363)
1281                 laguna_regulator_init();
1282         else if (board_info.board_id == BOARD_PM374)
1283                 norrin_regulator_init();
1284         else if (board_info.board_id == BOARD_E2548 ||
1285                         board_info.board_id == BOARD_P2530)
1286                 loki_regulator_init();
1287         else if (of_machine_is_compatible("nvidia,e2141"))
1288                 ; /* T210_interposer use DT for power tree*/
1289         else
1290                 ardbeg_regulator_init();
1291         ardbeg_suspend_init();
1292
1293         if ((board_info.board_id == BOARD_PM374) ||
1294                 (board_info.board_id == BOARD_E1971) ||
1295                 (board_info.board_id == BOARD_E1973))
1296                 norrin_emc_init();
1297         else if (board_info.board_id == BOARD_E2548 ||
1298                         board_info.board_id == BOARD_P2530)
1299                 loki_emc_init();
1300         else
1301                 ardbeg_emc_init();
1302
1303         edp_init();
1304         isomgr_init();
1305         ardbeg_touch_init();
1306         if (board_info.board_id == BOARD_E2548 ||
1307                         board_info.board_id == BOARD_P2530)
1308                 loki_panel_init();
1309         else
1310                 ardbeg_panel_init();
1311
1312                 /* put PEX pads into DPD mode to save additional power */
1313                 tegra_io_dpd_enable(&pexbias_io);
1314                 tegra_io_dpd_enable(&pexclk1_io);
1315                 tegra_io_dpd_enable(&pexclk2_io);
1316
1317         if (board_info.board_id == BOARD_E2548 ||
1318                         board_info.board_id == BOARD_P2530)
1319                 loki_kbc_init();
1320
1321         if (board_info.board_id == BOARD_PM374 ||
1322                 board_info.board_id == BOARD_PM359 ||
1323                 board_info.board_id == BOARD_PM358 ||
1324                 board_info.board_id == BOARD_PM370 ||
1325                 board_info.board_id == BOARD_PM375 ||
1326                 board_info.board_id == BOARD_PM363) {
1327                 ardbeg_sensors_init();
1328                 norrin_soctherm_init();
1329         }       else if (board_info.board_id == BOARD_E2548 ||
1330                         board_info.board_id == BOARD_P2530) {
1331                 loki_sensors_init();
1332                 loki_soctherm_init();
1333         }       else {
1334                 ardbeg_sensors_init();
1335                 ardbeg_soctherm_init();
1336         }
1337 #ifndef CONFIG_USE_OF
1338         ardbeg_setup_bluedroid_pm();
1339 #endif
1340         ardbeg_sysedp_dynamic_capping_init();
1341         ardbeg_sysedp_batmon_init();
1342 }
1343
1344 static void __init tegra_ardbeg_init_early(void)
1345 {
1346         tegra_get_board_info(&board_info);
1347         if (board_info.board_id == BOARD_E2548 ||
1348                         board_info.board_id == BOARD_P2530)
1349                 loki_rail_alignment_init();
1350         else
1351                 ardbeg_rail_alignment_init();
1352         tegra12x_init_early();
1353 }
1354
1355 static int tegra_ardbeg_notifier_call(struct notifier_block *nb,
1356                                     unsigned long event, void *data)
1357 {
1358 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
1359         struct device *dev = data;
1360 #endif
1361         switch (event) {
1362         case BUS_NOTIFY_BIND_DRIVER:
1363 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
1364                 if (dev->of_node) {
1365                         if (of_device_is_compatible(dev->of_node,
1366                                 "pwm-backlight")) {
1367                                 tegra_pwm_bl_ops_register(dev);
1368                         }
1369                 }
1370 #endif
1371                 break;
1372         default:
1373                 break;
1374         }
1375         return NOTIFY_DONE;
1376 }
1377
1378 static struct notifier_block platform_nb = {
1379         .notifier_call = tegra_ardbeg_notifier_call,
1380 };
1381
1382 static void __init tegra_ardbeg_dt_init(void)
1383 {
1384         tegra_get_board_info(&board_info);
1385         tegra_get_display_board_info(&display_board_info);
1386
1387 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
1388         /* In Ardbeg, zero display_board_id is considered to
1389          * Panasonic wuxga panel one */
1390         tegra_set_fixed_panel_ops(true, &dsi_p_wuxga_10_1_ops,
1391                 "p,wuxga-10-1");
1392         tegra_set_fixed_pwm_bl_ops(dsi_p_wuxga_10_1_ops.pwm_bl_ops);
1393 #endif
1394         bus_register_notifier(&platform_bus_type, &platform_nb);
1395
1396         tegra_ardbeg_early_init();
1397 #ifdef CONFIG_USE_OF
1398         ardbeg_camera_auxdata(ardbeg_auxdata_lookup);
1399         of_platform_populate(NULL,
1400                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1401                 &platform_bus);
1402 #endif
1403
1404         tegra_ardbeg_late_init();
1405 }
1406
1407 static void __init tegra_ardbeg_reserve(void)
1408 {
1409 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1410         ulong tmp;
1411 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1412
1413 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1414                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1415         ulong carveout_size = 0;
1416         ulong fb2_size = SZ_16M;
1417 #else
1418         ulong carveout_size = SZ_1G;
1419         ulong fb2_size = SZ_4M;
1420 #endif
1421         ulong fb1_size = SZ_16M + SZ_2M;
1422         ulong vpr_size = 186 * SZ_1M;
1423
1424 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
1425         /* support FBcon on 4K monitors */
1426         fb2_size = SZ_64M + SZ_8M;      /* 4096*2160*4*2 = 70778880 bytes */
1427 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
1428
1429 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1430         tmp = fb1_size;
1431         fb1_size = fb2_size;
1432         fb2_size = tmp;
1433 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1434
1435         tegra_reserve4(carveout_size, fb1_size, fb2_size, vpr_size);
1436 }
1437
1438 static const char * const ardbeg_dt_board_compat[] = {
1439         "nvidia,ardbeg",
1440         NULL
1441 };
1442
1443 static const char * const laguna_dt_board_compat[] = {
1444         "nvidia,laguna",
1445         NULL
1446 };
1447
1448 static const char * const tn8_dt_board_compat[] = {
1449         "nvidia,tn8",
1450         NULL
1451 };
1452
1453 static const char * const ardbeg_sata_dt_board_compat[] = {
1454         "nvidia,ardbeg_sata",
1455         NULL
1456 };
1457
1458 static const char * const norrin_dt_board_compat[] = {
1459         "nvidia,norrin",
1460         NULL
1461 };
1462
1463 static const char * const bowmore_dt_board_compat[] = {
1464         "nvidia,bowmore",
1465         NULL
1466 };
1467
1468 static const char * const loki_dt_board_compat[] = {
1469         "nvidia,t132loki",
1470         NULL
1471 };
1472
1473 static const char * const jetson_dt_board_compat[] = {
1474         "nvidia,jetson-tk1",
1475         NULL
1476 };
1477
1478 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1479 DT_MACHINE_START(LOKI, "t132loki")
1480         .atag_offset    = 0x100,
1481         .smp            = smp_ops(tegra_smp_ops),
1482         .map_io         = tegra_map_common_io,
1483         .reserve        = tegra_ardbeg_reserve,
1484         .init_early     = tegra_ardbeg_init_early,
1485         .init_irq       = irqchip_init,
1486         .init_time      = clocksource_of_init,
1487         .init_machine   = tegra_ardbeg_dt_init,
1488         .restart        = tegra_assert_system_reset,
1489         .dt_compat      = loki_dt_board_compat,
1490         .init_late      = tegra_init_late
1491 MACHINE_END
1492 #endif
1493
1494 DT_MACHINE_START(LAGUNA, "laguna")
1495         .atag_offset    = 0x100,
1496         .smp            = smp_ops(tegra_smp_ops),
1497         .map_io         = tegra_map_common_io,
1498         .reserve        = tegra_ardbeg_reserve,
1499         .init_early     = tegra_ardbeg_init_early,
1500         .init_irq       = irqchip_init,
1501         .init_time      = clocksource_of_init,
1502         .init_machine   = tegra_ardbeg_dt_init,
1503         .restart        = tegra_assert_system_reset,
1504         .dt_compat      = laguna_dt_board_compat,
1505         .init_late      = tegra_init_late
1506 MACHINE_END
1507
1508 DT_MACHINE_START(TN8, "tn8")
1509         .atag_offset    = 0x100,
1510         .smp            = smp_ops(tegra_smp_ops),
1511         .map_io         = tegra_map_common_io,
1512         .reserve        = tegra_ardbeg_reserve,
1513         .init_early     = tegra_ardbeg_init_early,
1514         .init_irq       = irqchip_init,
1515         .init_time      = clocksource_of_init,
1516         .init_machine   = tegra_ardbeg_dt_init,
1517         .restart        = tegra_assert_system_reset,
1518         .dt_compat      = tn8_dt_board_compat,
1519         .init_late      = tegra_init_late
1520 MACHINE_END
1521
1522 DT_MACHINE_START(NORRIN, "norrin")
1523         .atag_offset    = 0x100,
1524         .smp            = smp_ops(tegra_smp_ops),
1525         .map_io         = tegra_map_common_io,
1526         .reserve        = tegra_ardbeg_reserve,
1527         .init_early     = tegra_ardbeg_init_early,
1528         .init_irq       = irqchip_init,
1529         .init_time      = clocksource_of_init,
1530         .init_machine   = tegra_ardbeg_dt_init,
1531         .restart        = tegra_assert_system_reset,
1532         .dt_compat      = norrin_dt_board_compat,
1533         .init_late      = tegra_init_late
1534 MACHINE_END
1535
1536 DT_MACHINE_START(BOWMORE, "bowmore")
1537         .atag_offset    = 0x100,
1538         .smp            = smp_ops(tegra_smp_ops),
1539         .map_io         = tegra_map_common_io,
1540         .reserve        = tegra_ardbeg_reserve,
1541         .init_early     = tegra_ardbeg_init_early,
1542         .init_irq       = irqchip_init,
1543         .init_time      = clocksource_of_init,
1544         .init_machine   = tegra_ardbeg_dt_init,
1545         .restart        = tegra_assert_system_reset,
1546         .dt_compat      = bowmore_dt_board_compat,
1547         .init_late      = tegra_init_late
1548 MACHINE_END
1549
1550 DT_MACHINE_START(ARDBEG, "ardbeg")
1551         .atag_offset    = 0x100,
1552         .smp            = smp_ops(tegra_smp_ops),
1553         .map_io         = tegra_map_common_io,
1554         .reserve        = tegra_ardbeg_reserve,
1555         .init_early     = tegra_ardbeg_init_early,
1556         .init_irq       = irqchip_init,
1557         .init_time      = clocksource_of_init,
1558         .init_machine   = tegra_ardbeg_dt_init,
1559         .restart        = tegra_assert_system_reset,
1560         .dt_compat      = ardbeg_dt_board_compat,
1561         .init_late      = tegra_init_late
1562 MACHINE_END
1563
1564 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1565         .atag_offset    = 0x100,
1566         .smp            = smp_ops(tegra_smp_ops),
1567         .map_io         = tegra_map_common_io,
1568         .reserve        = tegra_ardbeg_reserve,
1569         .init_early     = tegra_ardbeg_init_early,
1570         .init_irq       = irqchip_init,
1571         .init_time      = clocksource_of_init,
1572         .init_machine   = tegra_ardbeg_dt_init,
1573         .restart        = tegra_assert_system_reset,
1574         .dt_compat      = ardbeg_sata_dt_board_compat,
1575         .init_late      = tegra_init_late
1576
1577 MACHINE_END
1578
1579 DT_MACHINE_START(JETSON_TK1, "jetson-tk1")
1580         .atag_offset    = 0x100,
1581         .smp            = smp_ops(tegra_smp_ops),
1582         .map_io         = tegra_map_common_io,
1583         .reserve        = tegra_ardbeg_reserve,
1584         .init_early     = tegra_ardbeg_init_early,
1585         .init_irq       = irqchip_init,
1586         .init_time      = clocksource_of_init,
1587         .init_machine   = tegra_ardbeg_dt_init,
1588         .restart        = tegra_assert_system_reset,
1589         .dt_compat      = jetson_dt_board_compat,
1590         .init_late      = tegra_init_late
1591 MACHINE_END