drivers/platform/tegra/tegra_usb_pad_ctrl.c

   1 /*
   2  * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  16  * 02111-1307, USA
  17  */
  18
  19
  20 #include <linux/export.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/delay.h>
  24 #include <linux/tegra-fuse.h>
  25 #include <linux/clk/tegra.h>
  26 #include <linux/tegra-powergate.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/tegra_pm_domains.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/slab.h>
  31 #include <linux/of_device.h>
  32
  33 #include <mach/tegra_usb_pad_ctrl.h>
  34
  35 #include "../../../arch/arm/mach-tegra/iomap.h"
  36
  37 static DEFINE_SPINLOCK(utmip_pad_lock);
  38 static DEFINE_SPINLOCK(xusb_padctl_lock);
  39 static DEFINE_SPINLOCK(xusb_padctl_reg_lock);
  40 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
  41 static DEFINE_SPINLOCK(pcie_pad_lock);
  42 static DEFINE_SPINLOCK(sata_pad_lock);
  43 static DEFINE_SPINLOCK(hsic_pad_lock);
  44 static int hsic_pad_count;
  45 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
  46 static struct of_device_id tegra_xusbb_pd[] = {
  47         { .compatible = "nvidia, tegra210-xusbb-pd", },
  48         { .compatible = "nvidia, tegra132-xusbb-pd", },
  49         { .compatible = "nvidia, tegra124-xusbb-pd", },
  50         {},
  51 };
  52 static struct of_device_id tegra_xusbc_pd[] = {
  53         { .compatible = "nvidia, tegra210-xusbc-pd", },
  54         { .compatible = "nvidia, tegra132-xusbc-pd", },
  55         { .compatible = "nvidia, tegra124-xusbc-pd", },
  56         {},
  57 };
  58 #endif
  59 #endif
  60 static int utmip_pad_count;
  61 static struct clk *utmi_pad_clk;
  62
  63 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
  64 static u32 usb_lanes;
  65 #endif
  66
  67 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
  68 struct tegra_padctl_soc_data {
  69         char    * const *regulator_name;
  70         int     num_regulator;
  71 };
  72
  73 struct tegra_padctl {
  74         struct platform_device *pdev;
  75
  76         const struct tegra_padctl_soc_data *soc_data;
  77
  78         struct regulator_bulk_data *regulator;
  79
  80         struct clk *plle_clk;
  81         struct clk *plle_hw_clk;
  82
  83         u32 lane_owner; /* used for XUSB lanes */
  84         u32 lane_map; /* used for PCIE lanes */
  85         bool enable_sata_port; /* used for SATA lane */
  86 };
  87 static struct tegra_padctl *padctl;
  88 #endif
  89
  90 void tegra_xhci_release_otg_port(bool release)
  91 {
  92         void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
  93         u32 reg;
  94         unsigned long flags;
  95
  96         if (tegra_platform_is_fpga())
  97                 return;
  98
  99         spin_lock_irqsave(&xusb_padctl_lock, flags);
 100         reg = readl(padctl_base + XUSB_PADCTL_USB2_PAD_MUX_0);
 101
 102         reg &= ~PAD_PORT_MASK(0);
 103         if (release)
 104                 reg |= PAD_PORT_SNPS(0);
 105         else
 106                 reg |= PAD_PORT_XUSB(0);
 107
 108         writel(reg, padctl_base + XUSB_PADCTL_USB2_PAD_MUX_0);
 109         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 110 }
 111 EXPORT_SYMBOL_GPL(tegra_xhci_release_otg_port);
 112
 113 void tegra_xhci_release_dev_port(bool release)
 114 {
 115         void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 116         u32 reg;
 117         unsigned long flags;
 118
 119         spin_lock_irqsave(&xusb_padctl_lock, flags);
 120         reg = readl(padctl_base + XUSB_PADCTL_USB2_PAD_MUX_0);
 121
 122         reg &= ~USB2_OTG_PORT_CAP(0, ~0);
 123         if (release)
 124                 reg |= USB2_OTG_PORT_CAP(0, XUSB_DEVICE_MODE);
 125         else
 126                 reg |= USB2_OTG_PORT_CAP(0, XUSB_HOST_MODE);
 127
 128         writel(reg, padctl_base + XUSB_PADCTL_USB2_PAD_MUX_0);
 129         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 130 }
 131 EXPORT_SYMBOL_GPL(tegra_xhci_release_dev_port);
 132
 133 static int tegra_padctl_hs_xmiter(int pad, bool force_disabled)
 134 {
 135 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 136         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 137         u32 reg;
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&xusb_padctl_lock, flags);
 141
 142         if (force_disabled) {
 143                 /* assert PD2 */
 144                 reg = readl(pad_base + XUSB_PADCTL_USB2_OTG_PAD_CTL_0(pad));
 145                 reg |= (USB2_OTG_PD2 | USB2_PD2_OVRD_EN);
 146                 writel(reg, pad_base + XUSB_PADCTL_USB2_OTG_PAD_CTL_0(pad));
 147         } else {
 148                 /* remove pd2_ovrd_en, leave it under HW control */
 149                 reg = readl(pad_base + XUSB_PADCTL_USB2_OTG_PAD_CTL_0(pad));
 150                 reg &= ~(USB2_PD2_OVRD_EN);
 151                 writel(reg, pad_base + XUSB_PADCTL_USB2_OTG_PAD_CTL_0(pad));
 152         }
 153         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 154 #endif
 155         return 0;
 156 }
 157
 158 int tegra_pd2_asserted(int pad)
 159 {
 160         return tegra_padctl_hs_xmiter(pad, true);
 161 }
 162 EXPORT_SYMBOL_GPL(tegra_pd2_asserted);
 163
 164 int tegra_pd2_deasserted(int pad)
 165 {
 166         return tegra_padctl_hs_xmiter(pad, false);
 167 }
 168 EXPORT_SYMBOL_GPL(tegra_pd2_deasserted);
 169
 170 void tegra_xhci_ss_wake_on_interrupts(u32 enabled_port, bool enable)
 171 {
 172         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 173         u32 elpg_program0;
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&xusb_padctl_lock, flags);
 177         /* clear any event */
 178         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 179         if (enabled_port & TEGRA_XUSB_SS_P0)
 180                 elpg_program0 |= SS_PORT0_WAKEUP_EVENT;
 181         if (enabled_port & TEGRA_XUSB_SS_P1)
 182                 elpg_program0 |= SS_PORT1_WAKEUP_EVENT;
 183         if (enabled_port & TEGRA_XUSB_SS_P2)
 184                 elpg_program0 |= SS_PORT2_WAKEUP_EVENT;
 185         if (enabled_port & TEGRA_XUSB_SS_P3)
 186                 elpg_program0 |= SS_PORT3_WAKEUP_EVENT;
 187
 188         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 189
 190         /* enable ss wake interrupts */
 191         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 192         if (enable) {
 193                 /* enable interrupts */
 194                 if (enabled_port & TEGRA_XUSB_SS_P0)
 195                         elpg_program0 |= SS_PORT0_WAKE_INTERRUPT_ENABLE;
 196                 if (enabled_port & TEGRA_XUSB_SS_P1)
 197                         elpg_program0 |= SS_PORT1_WAKE_INTERRUPT_ENABLE;
 198                 if (enabled_port & TEGRA_XUSB_SS_P2)
 199                         elpg_program0 |= SS_PORT2_WAKE_INTERRUPT_ENABLE;
 200                 if (enabled_port & TEGRA_XUSB_SS_P3)
 201                         elpg_program0 |= SS_PORT3_WAKE_INTERRUPT_ENABLE;
 202         } else {
 203                 /* disable interrupts */
 204                 if (enabled_port & TEGRA_XUSB_SS_P0)
 205                         elpg_program0 &= ~SS_PORT0_WAKE_INTERRUPT_ENABLE;
 206                 if (enabled_port & TEGRA_XUSB_SS_P1)
 207                         elpg_program0 &= ~SS_PORT1_WAKE_INTERRUPT_ENABLE;
 208                 if (enabled_port & TEGRA_XUSB_SS_P2)
 209                         elpg_program0 &= ~SS_PORT2_WAKE_INTERRUPT_ENABLE;
 210                 if (enabled_port & TEGRA_XUSB_SS_P3)
 211                         elpg_program0 &= ~SS_PORT3_WAKE_INTERRUPT_ENABLE;
 212         }
 213         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 214         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 215 }
 216 EXPORT_SYMBOL_GPL(tegra_xhci_ss_wake_on_interrupts);
 217
 218 void tegra_xhci_hs_wake_on_interrupts(u32 portmap, bool enable)
 219 {
 220         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 221         u32 elpg_program0;
 222         unsigned long flags;
 223
 224         spin_lock_irqsave(&xusb_padctl_lock, flags);
 225         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 226         if (portmap & TEGRA_XUSB_USB2_P0)
 227                 elpg_program0 |= USB2_PORT0_WAKEUP_EVENT;
 228         if (portmap & TEGRA_XUSB_USB2_P1)
 229                 elpg_program0 |= USB2_PORT1_WAKEUP_EVENT;
 230         if (portmap & TEGRA_XUSB_USB2_P2)
 231                 elpg_program0 |= USB2_PORT2_WAKEUP_EVENT;
 232         if (portmap & TEGRA_XUSB_USB2_P3)
 233                 elpg_program0 |= USB2_PORT3_WAKEUP_EVENT;
 234         if (portmap & TEGRA_XUSB_HSIC_P0)
 235                 elpg_program0 |= USB2_HSIC_PORT0_WAKEUP_EVENT;
 236         if (portmap & TEGRA_XUSB_HSIC_P1)
 237                 elpg_program0 |= USB2_HSIC_PORT1_WAKEUP_EVENT;
 238
 239         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 240
 241         /* Enable the wake interrupts */
 242         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 243         if (enable) {
 244                 /* enable interrupts */
 245                 if (portmap & TEGRA_XUSB_USB2_P0)
 246                         elpg_program0 |= USB2_PORT0_WAKE_INTERRUPT_ENABLE;
 247                 if (portmap & TEGRA_XUSB_USB2_P1)
 248                         elpg_program0 |= USB2_PORT1_WAKE_INTERRUPT_ENABLE;
 249                 if (portmap & TEGRA_XUSB_USB2_P2)
 250                         elpg_program0 |= USB2_PORT2_WAKE_INTERRUPT_ENABLE;
 251                 if (portmap & TEGRA_XUSB_USB2_P3)
 252                         elpg_program0 |= USB2_PORT3_WAKE_INTERRUPT_ENABLE;
 253                 if (portmap & TEGRA_XUSB_HSIC_P0)
 254                         elpg_program0 |= USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE;
 255                 if (portmap & TEGRA_XUSB_HSIC_P1)
 256                         elpg_program0 |= USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE;
 257         } else {
 258                 if (portmap & TEGRA_XUSB_USB2_P0)
 259                         elpg_program0 &= ~USB2_PORT0_WAKE_INTERRUPT_ENABLE;
 260                 if (portmap & TEGRA_XUSB_USB2_P1)
 261                         elpg_program0 &= ~USB2_PORT1_WAKE_INTERRUPT_ENABLE;
 262                 if (portmap & TEGRA_XUSB_USB2_P2)
 263                         elpg_program0 &= ~USB2_PORT2_WAKE_INTERRUPT_ENABLE;
 264                 if (portmap & TEGRA_XUSB_USB2_P3)
 265                         elpg_program0 &= ~USB2_PORT3_WAKE_INTERRUPT_ENABLE;
 266                 if (portmap & TEGRA_XUSB_HSIC_P0)
 267                         elpg_program0 &= ~USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE;
 268                 if (portmap & TEGRA_XUSB_HSIC_P1)
 269                         elpg_program0 &= ~USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE;
 270         }
 271         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 272         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 273 }
 274 EXPORT_SYMBOL_GPL(tegra_xhci_hs_wake_on_interrupts);
 275
 276 void tegra_xhci_ss_wake_signal(u32 enabled_port, bool enable)
 277 {
 278         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 279         u32 elpg_program0;
 280         unsigned long flags;
 281
 282         /* DO NOT COMBINE BELOW 2 WRITES */
 283
 284         spin_lock_irqsave(&xusb_padctl_lock, flags);
 285         /* Assert/Deassert clamp_en_early signals to SSP0/1 */
 286 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 287         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
 288 #else
 289         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 290 #endif
 291         if (enable) {
 292                 if (enabled_port & TEGRA_XUSB_SS_P0)
 293                         elpg_program0 |= SSP0_ELPG_CLAMP_EN_EARLY;
 294                 if (enabled_port & TEGRA_XUSB_SS_P1)
 295                         elpg_program0 |= SSP1_ELPG_CLAMP_EN_EARLY;
 296                 if (enabled_port & TEGRA_XUSB_SS_P2)
 297                         elpg_program0 |= SSP2_ELPG_CLAMP_EN_EARLY;
 298                 if (enabled_port & TEGRA_XUSB_SS_P3)
 299                         elpg_program0 |= SSP3_ELPG_CLAMP_EN_EARLY;
 300         } else {
 301                 if (enabled_port & TEGRA_XUSB_SS_P0)
 302                         elpg_program0 &= ~SSP0_ELPG_CLAMP_EN_EARLY;
 303                 if (enabled_port & TEGRA_XUSB_SS_P1)
 304                         elpg_program0 &= ~SSP1_ELPG_CLAMP_EN_EARLY;
 305                 if (enabled_port & TEGRA_XUSB_SS_P2)
 306                         elpg_program0 &= ~SSP2_ELPG_CLAMP_EN_EARLY;
 307                 if (enabled_port & TEGRA_XUSB_SS_P3)
 308                         elpg_program0 &= ~SSP3_ELPG_CLAMP_EN_EARLY;
 309         }
 310 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 311         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
 312 #else
 313         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 314 #endif
 315         /*
 316          * Check the LP0 figure and leave gap bw writes to
 317          * clamp_en_early and clamp_en
 318          */
 319         udelay(100);
 320
 321         /* Assert/Deassert clam_en signal */
 322 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 323         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
 324 #else
 325         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 326 #endif
 327
 328         if (enable) {
 329                 if (enabled_port & TEGRA_XUSB_SS_P0)
 330                         elpg_program0 |= SSP0_ELPG_CLAMP_EN;
 331                 if (enabled_port & TEGRA_XUSB_SS_P1)
 332                         elpg_program0 |= SSP1_ELPG_CLAMP_EN;
 333                 if (enabled_port & TEGRA_XUSB_SS_P2)
 334                         elpg_program0 |= SSP2_ELPG_CLAMP_EN;
 335                 if (enabled_port & TEGRA_XUSB_SS_P3)
 336                         elpg_program0 |= SSP3_ELPG_CLAMP_EN;
 337         } else {
 338                 if (enabled_port & TEGRA_XUSB_SS_P0)
 339                         elpg_program0 &= ~SSP0_ELPG_CLAMP_EN;
 340                 if (enabled_port & TEGRA_XUSB_SS_P1)
 341                         elpg_program0 &= ~SSP1_ELPG_CLAMP_EN;
 342                 if (enabled_port & TEGRA_XUSB_SS_P2)
 343                         elpg_program0 &= ~SSP2_ELPG_CLAMP_EN;
 344                 if (enabled_port & TEGRA_XUSB_SS_P3)
 345                         elpg_program0 &= ~SSP3_ELPG_CLAMP_EN;
 346         }
 347
 348 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 349         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
 350 #else
 351         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 352 #endif
 353         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 354
 355         /* wait for 250us for the writes to propogate */
 356         if (enable)
 357                 udelay(250);
 358 }
 359 EXPORT_SYMBOL_GPL(tegra_xhci_ss_wake_signal);
 360
 361 void tegra_xhci_ss_vcore(u32 enabled_port, bool enable)
 362 {
 363         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 364         u32 elpg_program0;
 365         unsigned long flags;
 366
 367         spin_lock_irqsave(&xusb_padctl_lock, flags);
 368         /* Assert vcore_off signal */
 369 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 370         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
 371 #else
 372         elpg_program0 = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 373 #endif
 374
 375         if (enable) {
 376                 if (enabled_port & TEGRA_XUSB_SS_P0)
 377                         elpg_program0 |= SSP0_ELPG_VCORE_DOWN;
 378                 if (enabled_port & TEGRA_XUSB_SS_P1)
 379                         elpg_program0 |= SSP1_ELPG_VCORE_DOWN;
 380                 if (enabled_port & TEGRA_XUSB_SS_P2)
 381                         elpg_program0 |= SSP2_ELPG_VCORE_DOWN;
 382                 if (enabled_port & TEGRA_XUSB_SS_P3)
 383                         elpg_program0 |= SSP3_ELPG_VCORE_DOWN;
 384         } else {
 385                 if (enabled_port & TEGRA_XUSB_SS_P0)
 386                         elpg_program0 &= ~SSP0_ELPG_VCORE_DOWN;
 387                 if (enabled_port & TEGRA_XUSB_SS_P1)
 388                         elpg_program0 &= ~SSP1_ELPG_VCORE_DOWN;
 389                 if (enabled_port & TEGRA_XUSB_SS_P2)
 390                         elpg_program0 &= ~SSP2_ELPG_VCORE_DOWN;
 391                 if (enabled_port & TEGRA_XUSB_SS_P3)
 392                         elpg_program0 &= ~SSP3_ELPG_VCORE_DOWN;
 393         }
 394 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 395         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
 396 #else
 397         writel(elpg_program0, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
 398 #endif
 399         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 400 }
 401 EXPORT_SYMBOL_GPL(tegra_xhci_ss_vcore);
 402
 403 static int pex_usb_pad_pll(bool assert)
 404 {
 405 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 406         static struct clk *pex_uphy;
 407         static int ref_count;
 408         unsigned long flags;
 409         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 410         u32 val;
 411
 412         if (!pex_uphy)
 413                 pex_uphy = clk_get_sys(NULL, "pex_uphy");
 414
 415         if (IS_ERR(pex_uphy)) {
 416                 pr_err("Fail to get pex_uphy clk\n");
 417                 return PTR_ERR(pex_uphy);
 418         }
 419
 420         pr_debug("%s ref_count %d assert %d\n", __func__, ref_count, assert);
 421
 422         spin_lock_irqsave(&pcie_pad_lock, flags);
 423
 424         if (!assert) {
 425                 if (ref_count == 0)
 426                         tegra_periph_reset_deassert(pex_uphy);
 427                 ref_count++;
 428         } else {
 429                 ref_count--;
 430                 if (ref_count == 0) {
 431                         val = readl(clk_base +
 432                                 CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0);
 433                         if (XUSBIO_SEQ_ENABLE & val)
 434                                 pr_info("%s: pex uphy already enabled",
 435                                         __func__);
 436                         else
 437                                 tegra_periph_reset_assert(pex_uphy);
 438                 }
 439         }
 440         spin_unlock_irqrestore(&pcie_pad_lock, flags);
 441
 442 #endif
 443         return 0;
 444 }
 445
 446 static int sata_usb_pad_pll(bool assert)
 447 {
 448 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 449         static struct clk *sata_uphy;
 450         static int ref_count;
 451         unsigned long flags;
 452         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 453         u32 val;
 454
 455         if (!sata_uphy)
 456                 sata_uphy = clk_get_sys(NULL, "sata_uphy");
 457
 458         if (IS_ERR(sata_uphy)) {
 459                 pr_err("Fail to get sata_uphy clk\n");
 460                 return PTR_ERR(sata_uphy);
 461         }
 462
 463         pr_debug("%s ref_count %d assert %d\n", __func__, ref_count, assert);
 464
 465         spin_lock_irqsave(&sata_pad_lock, flags);
 466
 467         if (!assert) {
 468                 if (ref_count == 0)
 469                         tegra_periph_reset_deassert(sata_uphy);
 470                 ref_count++;
 471         } else {
 472                 ref_count--;
 473                 if (ref_count == 0) {
 474                         val = readl(clk_base +
 475                                 CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
 476                         if (SATA_SEQ_ENABLE & val)
 477                                 pr_info("%s: sata uphy already enabled",
 478                                         __func__);
 479                         else
 480                                 tegra_periph_reset_assert(sata_uphy);
 481                 }
 482         }
 483         spin_unlock_irqrestore(&sata_pad_lock, flags);
 484
 485 #endif
 486         return 0;
 487 }
 488
 489 int pex_usb_pad_pll_reset_assert(void)
 490 {
 491         return pex_usb_pad_pll(true);
 492 }
 493 EXPORT_SYMBOL_GPL(pex_usb_pad_pll_reset_assert);
 494
 495 int pex_usb_pad_pll_reset_deassert(void)
 496 {
 497         return pex_usb_pad_pll(false);
 498 }
 499 EXPORT_SYMBOL_GPL(pex_usb_pad_pll_reset_deassert);
 500
 501 int sata_usb_pad_pll_reset_assert(void)
 502 {
 503         return sata_usb_pad_pll(true);
 504 }
 505 EXPORT_SYMBOL_GPL(sata_usb_pad_pll_reset_assert);
 506
 507 int sata_usb_pad_pll_reset_deassert(void)
 508 {
 509         return sata_usb_pad_pll(false);
 510 }
 511 EXPORT_SYMBOL_GPL(sata_usb_pad_pll_reset_deassert);
 512
 513 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 514 static bool tegra_xusb_partitions_powergated(void)
 515 {
 516         int partition_id_xusbb, partition_id_xusbc;
 517
 518 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 519         partition_id_xusbb = tegra_pd_get_powergate_id(tegra_xusbb_pd);
 520         if (partition_id_xusbb < 0)
 521                 return -EINVAL;
 522
 523         partition_id_xusbc = tegra_pd_get_powergate_id(tegra_xusbc_pd);
 524         if (partition_id_xusbc < 0)
 525                 return -EINVAL;
 526 #else
 527         partition_id_xusbb = TEGRA_POWERGATE_XUSBB;
 528         partition_id_xusbc = TEGRA_POWERGATE_XUSBC;
 529 #endif
 530         if (!tegra_powergate_is_powered(partition_id_xusbb)
 531                         && !tegra_powergate_is_powered(partition_id_xusbc))
 532                 return true;
 533         return false;
 534 }
 535 #else
 536 static bool tegra_xusb_partitions_powergated(void)
 537 {
 538         return true;
 539 }
 540 #endif
 541
 542 int utmi_phy_iddq_override(bool set)
 543 {
 544         unsigned long val, flags;
 545         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 546
 547         spin_lock_irqsave(&utmip_pad_lock, flags);
 548         val = readl(clk_base + UTMIPLL_HW_PWRDN_CFG0);
 549         if (set && !utmip_pad_count) {
 550                 if (!tegra_xusb_partitions_powergated()) {
 551                         pr_warn("XUSB partitions are on, trying to assert IDDQ");
 552                         goto out1;
 553                 }
 554                 if (val & UTMIPLL_LOCK) {
 555                         pr_warn("UTMIPLL is locked, trying to assert IDDQ");
 556                         goto out1;
 557                 }
 558                 val |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
 559         } else if (!set && utmip_pad_count)
 560                 val &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
 561         else
 562                 goto out1;
 563         val |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
 564         writel(val, clk_base + UTMIPLL_HW_PWRDN_CFG0);
 565
 566 out1:
 567         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 568         return 0;
 569 }
 570 EXPORT_SYMBOL_GPL(utmi_phy_iddq_override);
 571
 572 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
 573 static void utmi_phy_pad(bool enable)
 574 {
 575         unsigned long val;
 576         int port, xhci_port_present = 0;
 577         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
 578
 579         if (enable) {
 580                 val = readl(pad_base + UTMIP_BIAS_CFG0);
 581                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 582                 val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x3) |
 583                         UTMIP_HSDISCON_LEVEL_MSB;
 584                 writel(val, pad_base + UTMIP_BIAS_CFG0);
 585
 586 #if defined(CONFIG_USB_XHCI_HCD)
 587         tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0
 588                         , PD_MASK , 0);
 589 #endif
 590         } else {
 591
 592                 val = tegra_usb_pad_reg_read(XUSB_PADCTL_USB2_PAD_MUX_0);
 593                 for (port = 0; port < XUSB_UTMI_COUNT; port++) {
 594                         if ((val & PAD_PORT_MASK(port)) == PAD_PORT_XUSB(port))
 595                                 xhci_port_present = 1;
 596                 }
 597
 598                 val = readl(pad_base + UTMIP_BIAS_CFG0);
 599                 val |= UTMIP_OTGPD;
 600                 val |= UTMIP_BIASPD;
 601 #if defined(CONFIG_TEGRA_XHCI_ENABLE_CDP_PORT)
 602                 if (xhci_port_present)  /* xhci holds atleast one utmi port */
 603                         val &= ~UTMIP_BIASPD;
 604 #endif
 605                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
 606                         UTMIP_HSDISCON_LEVEL_MSB);
 607                 writel(val, pad_base + UTMIP_BIAS_CFG0);
 608
 609 #if defined(CONFIG_TEGRA_XHCI_ENABLE_CDP_PORT)
 610                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0
 611                         , PD_MASK , 0);
 612 #else
 613                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0
 614                         , PD_MASK , PD_MASK);
 615 #endif
 616         }
 617 }
 618
 619 int utmi_phy_pad_enable(void)
 620 {
 621         unsigned long flags;
 622         static struct clk *usb2_trk;
 623
 624         if (!usb2_trk)
 625                 usb2_trk = clk_get_sys(NULL, "usb2_trk");
 626
 627         if (!utmi_pad_clk)
 628                 utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
 629
 630         clk_enable(utmi_pad_clk);
 631         if (!IS_ERR_OR_NULL(usb2_trk))
 632                 clk_enable(usb2_trk);
 633
 634         spin_lock_irqsave(&utmip_pad_lock, flags);
 635         utmip_pad_count++;
 636
 637         utmi_phy_pad(true);
 638
 639         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 640
 641         clk_disable(utmi_pad_clk);
 642         if (!IS_ERR_OR_NULL(usb2_trk))
 643                 clk_disable(usb2_trk);
 644
 645         return 0;
 646 }
 647 EXPORT_SYMBOL_GPL(utmi_phy_pad_enable);
 648
 649 int utmi_phy_pad_disable(void)
 650 {
 651         unsigned long flags;
 652         static struct clk *usb2_trk;
 653
 654         if (!usb2_trk)
 655                 usb2_trk = clk_get_sys(NULL, "usb2_trk");
 656
 657         if (!utmi_pad_clk)
 658                 utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
 659
 660         clk_enable(utmi_pad_clk);
 661         if (!IS_ERR_OR_NULL(usb2_trk))
 662                 clk_enable(usb2_trk);
 663         spin_lock_irqsave(&utmip_pad_lock, flags);
 664
 665         if (!utmip_pad_count) {
 666                 pr_err("%s: utmip pad already powered off\n", __func__);
 667                 goto out;
 668         }
 669         if (--utmip_pad_count == 0)
 670                 utmi_phy_pad(false);
 671 out:
 672         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 673         clk_disable(utmi_pad_clk);
 674         if (!IS_ERR_OR_NULL(usb2_trk))
 675                 clk_disable(usb2_trk);
 676
 677         return 0;
 678 }
 679 EXPORT_SYMBOL_GPL(utmi_phy_pad_disable);
 680
 681 #else
 682
 683 static void utmi_phy_pad(struct tegra_prod_list *prod_list, bool enable)
 684 {
 685         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 686         int val;
 687
 688         if (IS_ERR_OR_NULL(prod_list))
 689                 prod_list = NULL;
 690
 691         if (tegra_platform_is_fpga())
 692                 return;
 693
 694         if (enable) {
 695                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_PAD_MUX_0,
 696                         BIAS_PAD_MASK, BIAS_PAD_XUSB);
 697                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_1,
 698                         TRK_START_TIMER_MASK, TRK_START_TIMER);
 699                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_1,
 700                         TRK_DONE_RESET_TIMER_MASK, TRK_DONE_RESET_TIMER);
 701
 702                 if (prod_list) {
 703                         const char *prod_name = "prod_c_bias";
 704                         if (tegra_chip_get_revision() >= TEGRA_REVISION_A02)
 705                                 prod_name = "prod_c_bias_a02";
 706                         val = tegra_prod_set_by_name(&pad_base, prod_name,
 707                                                         prod_list);
 708                         if (val < 0) {
 709                                 pr_err("%s(), failed with err:%d\n",
 710                                                         __func__, val);
 711                                 goto safe_settings;
 712                         }
 713                 } else {
 714 safe_settings:
 715                         tegra_usb_pad_reg_update(
 716                                 XUSB_PADCTL_USB2_BIAS_PAD_CTL_0,
 717                                 HS_SQUELCH_LEVEL(~0), HS_SQUELCH_LEVEL(2));
 718
 719                         tegra_usb_pad_reg_update(
 720                                 XUSB_PADCTL_USB2_BIAS_PAD_CTL_0,
 721                                 HS_DISCON_LEVEL(~0), HS_DISCON_LEVEL(7));
 722                 }
 723
 724                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0,
 725                         PD_MASK, 0);
 726
 727                 udelay(1);
 728
 729                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_1,
 730                         PD_TRK_MASK, 0);
 731         } else {
 732
 733                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_PAD_MUX_0,
 734                         BIAS_PAD_MASK, BIAS_PAD_XUSB);
 735                 tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0,
 736                         PD_MASK, PD_MASK);
 737         }
 738 }
 739
 740 int utmi_phy_pad_enable(struct tegra_prod_list *prod_list)
 741 {
 742         unsigned long flags;
 743         static struct clk *usb2_trk;
 744
 745         if (!usb2_trk)
 746                 usb2_trk = clk_get_sys(NULL, "usb2_trk");
 747
 748         if (!utmi_pad_clk)
 749                 utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
 750
 751         clk_enable(utmi_pad_clk);
 752         if (!IS_ERR_OR_NULL(usb2_trk))
 753                 clk_enable(usb2_trk);
 754
 755         spin_lock_irqsave(&utmip_pad_lock, flags);
 756         utmip_pad_count++;
 757
 758         utmi_phy_pad(prod_list, true);
 759
 760         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 761
 762         /* for tracking complete */
 763         usleep_range(50, 60);
 764
 765         clk_disable(utmi_pad_clk);
 766         if (!IS_ERR_OR_NULL(usb2_trk))
 767                 clk_disable(usb2_trk);
 768
 769         return 0;
 770 }
 771 EXPORT_SYMBOL_GPL(utmi_phy_pad_enable);
 772
 773 int utmi_phy_pad_disable(struct tegra_prod_list *prod_list)
 774 {
 775         unsigned long flags;
 776         static struct clk *usb2_trk;
 777
 778         if (!usb2_trk)
 779                 usb2_trk = clk_get_sys(NULL, "usb2_trk");
 780
 781         if (!utmi_pad_clk)
 782                 utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
 783
 784         clk_enable(utmi_pad_clk);
 785         if (!IS_ERR_OR_NULL(usb2_trk))
 786                 clk_enable(usb2_trk);
 787         spin_lock_irqsave(&utmip_pad_lock, flags);
 788
 789         if (!utmip_pad_count) {
 790                 pr_err("%s: utmip pad already powered off\n", __func__);
 791                 goto out;
 792         }
 793         if (--utmip_pad_count == 0)
 794                 utmi_phy_pad(prod_list, false);
 795 out:
 796         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 797         clk_disable(utmi_pad_clk);
 798         if (!IS_ERR_OR_NULL(usb2_trk))
 799                 clk_disable(usb2_trk);
 800
 801         return 0;
 802 }
 803 EXPORT_SYMBOL_GPL(utmi_phy_pad_disable);
 804 #endif
 805
 806 int hsic_trk_enable(void)
 807 {
 808 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 809         unsigned long flags;
 810
 811         /* TODO : need to enable HSIC_TRK clk */
 812         spin_lock_irqsave(&hsic_pad_lock, flags);
 813
 814         hsic_pad_count++;
 815         tegra_usb_pad_reg_update(XUSB_PADCTL_USB2_PAD_MUX_0,
 816                 HSIC_PAD_TRK(~0) , HSIC_PAD_TRK(HSIC_PAD_TRK_XUSB));
 817
 818         tegra_usb_pad_reg_update(XUSB_PADCTL_HSIC_PAD_TRK_CTL_0,
 819                 HSIC_TRK_START_TIMER(~0), HSIC_TRK_START_TIMER(0x1e));
 820
 821         tegra_usb_pad_reg_update(XUSB_PADCTL_HSIC_PAD_TRK_CTL_0,
 822                 HSIC_TRK_DONE_RESET_TIMER(~0) , HSIC_TRK_DONE_RESET_TIMER(0xa));
 823
 824         udelay(1);
 825
 826         tegra_usb_pad_reg_update(XUSB_PADCTL_HSIC_PAD_TRK_CTL_0,
 827                 HSIC_PD_TRK(~0), HSIC_PD_TRK(0));
 828
 829         spin_unlock_irqrestore(&hsic_pad_lock, flags);
 830         /* TODO : need to disable HSIC_TRK clk */
 831 #endif
 832         return 0;
 833 }
 834 EXPORT_SYMBOL_GPL(hsic_trk_enable);
 835
 836
 837 static void get_usb_calib_data(int pad, u32 *hs_curr_level_pad,
 838                 u32 *term_range_adj, u32 *rpd_ctl, u32 *hs_iref_cap)
 839 {
 840         u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
 841         /*
 842          * read from usb_calib0 and pass to driver
 843          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
 844          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
 845          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
 846          * set HS_IREF_CAP              = usb_calib0[14:13]
 847          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
 848          */
 849 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
 850         u32 usb_calib_ext = tegra_fuse_readl(FUSE_USB_CALIB_EXT_0);
 851         /* RPD_CTRL                     = USB_CALIB_EXT[4:0] */
 852
 853         pr_debug("usb_calib0 = 0x%08x\n", usb_calib0);
 854         pr_debug("usb_calib_ext = 0x%08x\n", usb_calib_ext);
 855
 856         *hs_curr_level_pad = (usb_calib0 >>
 857                 ((!pad) ? 0 : ((6 * (pad + 1)) - 1))) & 0x3f;
 858         *term_range_adj = (usb_calib0 >> 7) & 0xf;
 859         *rpd_ctl = (usb_calib_ext >> 0) & 0x1f;
 860         *hs_iref_cap = 0;
 861 #else
 862         pr_info("usb_calib0 = 0x%08x\n", usb_calib0);
 863         *hs_curr_level_pad = (usb_calib0 >>
 864                         ((!pad) ? 0 : (15 + 7 * (pad - 1)))) & 0x3f;
 865         *term_range_adj = (usb_calib0 >> 7) & 0xf;
 866         *hs_iref_cap = (usb_calib0 >> 13) & 0x3;
 867         *rpd_ctl = 0;
 868 #endif
 869 }
 870
 871 static u8 ss_pad_inited = 0x0;
 872 static u8 utmi_pad_inited = 0x0;
 873
 874 void xusb_utmi_pad_deinit(int pad)
 875 {
 876         unsigned long flags;
 877         spin_lock_irqsave(&xusb_padctl_lock, flags);
 878         utmi_pad_inited &= ~(1 << pad);
 879         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 880 }
 881 EXPORT_SYMBOL_GPL(xusb_utmi_pad_deinit);
 882
 883 void xusb_utmi_pad_init(int pad, u32 cap, bool external_pmic)
 884 {
 885         unsigned long val, flags;
 886         u32 ctl0_offset, ctl1_offset, batry_chg_1;
 887         static u32 hs_curr_level_pad, term_range_adj;
 888         static u32 rpd_ctl, hs_iref_cap;
 889         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 890
 891         spin_lock_irqsave(&xusb_padctl_lock, flags);
 892         /* Check if programmed */
 893         if (utmi_pad_inited & (1 << pad)) {
 894                 pr_warn("Already init for utmi pad %d\n", pad);
 895                 spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 896                 return;
 897         }
 898
 899         /* program utmi pad */
 900         val = readl(pad_base + XUSB_PADCTL_USB2_PAD_MUX_0);
 901         val &= ~PAD_PORT_MASK(pad);
 902         val |= PAD_PORT_XUSB(pad);
 903         writel(val, pad_base + XUSB_PADCTL_USB2_PAD_MUX_0);
 904
 905         val = readl(pad_base + XUSB_PADCTL_USB2_PORT_CAP_0);
 906         val &= ~USB2_OTG_PORT_CAP(pad, ~0);
 907         val |= cap;
 908         writel(val, pad_base + XUSB_PADCTL_USB2_PORT_CAP_0);
 909
 910         val = readl(pad_base + XUSB_PADCTL_USB2_OC_MAP_0);
 911         val &= ~PORT_OC_PIN(pad, ~0);
 912         val |= PORT_OC_PIN(pad, OC_DISABLED);
 913         writel(val, pad_base + XUSB_PADCTL_USB2_OC_MAP_0);
 914
 915         val = readl(pad_base + XUSB_PADCTL_VBUS_OC_MAP_0);
 916         val &= ~VBUS_OC_MAP(pad, ~0);
 917         val |= VBUS_OC_MAP(pad, OC_DISABLED);
 918         writel(val, pad_base + XUSB_PADCTL_VBUS_OC_MAP_0);
 919         /*
 920         * Modify only the bits which belongs to the port
 921         * and enable respective VBUS_PAD for the port
 922         */
 923         if (external_pmic) {
 924                 val = readl(pad_base + XUSB_PADCTL_OC_DET_0);
 925                 val &= ~VBUS_EN_OC_MAP(pad, ~0);
 926                 val |= VBUS_EN_OC_MAP(pad, OC_VBUS_PAD(pad));
 927                 writel(val, pad_base + XUSB_PADCTL_OC_DET_0);
 928         }
 929
 930         val = readl(pad_base + XUSB_PADCTL_USB2_OC_MAP_0);
 931         val &= ~PORT_OC_PIN(pad, ~0);
 932         val |= PORT_OC_PIN(pad, OC_VBUS_PAD(pad));
 933         writel(val, pad_base + XUSB_PADCTL_USB2_OC_MAP_0);
 934
 935         ctl0_offset = XUSB_PADCTL_USB2_OTG_PAD_CTL_0(pad);
 936         ctl1_offset = XUSB_PADCTL_USB2_OTG_PAD_CTL_1(pad);
 937
 938         get_usb_calib_data(pad, &hs_curr_level_pad,
 939                         &term_range_adj, &rpd_ctl, &hs_iref_cap);
 940
 941         val = readl(pad_base + ctl0_offset);
 942         val &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_PD_ZI);
 943         val |= hs_curr_level_pad | USB2_OTG_PD | USB2_OTG_PD2;
 944         writel(val, pad_base + ctl0_offset);
 945
 946         val = readl(pad_base + ctl1_offset);
 947         val &= ~(USB2_OTG_TERM_RANGE_ADJ | RPD_CTRL
 948                         | USB2_OTG_HS_IREF_CAP
 949                         | USB2_OTG_PD_CHRP_FORCE_POWERUP
 950                         | USB2_OTG_PD_DISC_FORCE_POWERUP);
 951         val |= (rpd_ctl << 26) |
 952                 (term_range_adj << 3) |
 953                 (hs_iref_cap << 9) | USB2_OTG_PD_DR;
 954         writel(val, pad_base + ctl1_offset);
 955
 956         batry_chg_1 = XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(pad);
 957
 958         val = readl(pad_base + batry_chg_1);
 959         val &= ~(VREG_FIX18 | VREG_LEV);
 960         if ((cap >> (4 * pad)) == XUSB_DEVICE_MODE)
 961                 val |= VREG_LEV_EN;
 962         if ((cap >> (4 * pad)) == XUSB_HOST_MODE)
 963                 val |= VREG_FIX18;
 964         writel(val, pad_base + batry_chg_1);
 965
 966         utmi_pad_inited |= (1 << pad);
 967         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
 968
 969         /* Dump register value */
 970         pr_debug("[%s] UTMI pad %d, cap %x\n", __func__ , pad, cap);
 971         pr_debug("XUSB_PADCTL_USB2_PAD_MUX_0 = 0x%x\n"
 972                         , readl(pad_base + XUSB_PADCTL_USB2_PAD_MUX_0));
 973         pr_debug("XUSB_PADCTL_USB2_PORT_CAP_0 = 0x%x\n"
 974                         , readl(pad_base + XUSB_PADCTL_USB2_PORT_CAP_0));
 975         pr_debug("XUSB_PADCTL_USB2_OC_MAP_0 = 0x%x\n"
 976                         , readl(pad_base + XUSB_PADCTL_USB2_OC_MAP_0));
 977         pr_debug("XUSB_PADCTL_VBUS_OC_MAP_0 = 0x%x\n"
 978                         , readl(pad_base + XUSB_PADCTL_VBUS_OC_MAP_0));
 979         pr_debug("XUSB_PADCTL_USB2_OTG_PAD_CTL_0 (0x%x) = 0x%x\n"
 980                         , ctl0_offset , readl(pad_base + ctl0_offset));
 981         pr_debug("XUSB_PADCTL_USB2_OTG_PAD_CTL_1 (0x%x) = 0x%x\n"
 982                         , ctl1_offset, readl(pad_base + ctl1_offset));
 983         pr_debug("XUSB_PADCTL_USB2_BATTERY_CHRG_CTL1 (0x%x) = 0x%x\n"
 984                         , batry_chg_1, readl(pad_base + batry_chg_1));
 985 }
 986 EXPORT_SYMBOL_GPL(xusb_utmi_pad_init);
 987
 988 void xusb_utmi_pad_driver_power(int pad, bool on)
 989 {
 990         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 991         u32 ctl0_val, ctl1_val, ctl0_offset, ctl1_offset;
 992         unsigned long flags;
 993
 994         ctl0_offset = XUSB_PADCTL_USB2_OTG_PAD_CTL_0(pad);
 995         ctl1_offset = XUSB_PADCTL_USB2_OTG_PAD_CTL_1(pad);
 996
 997         spin_lock_irqsave(&xusb_padctl_lock, flags);
 998
 999         ctl0_val = readl(pad_base + ctl0_offset);
1000         ctl1_val = readl(pad_base + ctl1_offset);
1001
1002         if (on) {
1003                 ctl0_val &= ~(USB2_OTG_PD | USB2_OTG_PD2);
1004                 ctl1_val &= ~(USB2_OTG_PD_DR);
1005         } else {
1006                 ctl0_val |= USB2_OTG_PD | USB2_OTG_PD2;
1007                 ctl1_val |= USB2_OTG_PD_DR;
1008         }
1009
1010         writel(ctl0_val, pad_base + ctl0_offset);
1011         writel(ctl1_val, pad_base + ctl1_offset);
1012
1013         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1014 }
1015 EXPORT_SYMBOL_GPL(xusb_utmi_pad_driver_power);
1016
1017 void xusb_ss_pad_deinit(int pad)
1018 {
1019         unsigned long flags;
1020         spin_lock_irqsave(&xusb_padctl_lock, flags);
1021         ss_pad_inited &= ~(1 << pad);
1022         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1023 }
1024 EXPORT_SYMBOL_GPL(xusb_ss_pad_deinit);
1025
1026 void xusb_ss_pad_init(int pad, int port_map, u32 cap)
1027 {
1028         unsigned long val, flags;
1029         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1030
1031         spin_lock_irqsave(&xusb_padctl_lock, flags);
1032         /* Check if programmed */
1033         if (ss_pad_inited & (1 << pad)) {
1034                 pr_warn("Already init for ss pad %d\n", pad);
1035                 spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1036                 return;
1037         }
1038
1039         /* Program ss pad */
1040         val = readl(pad_base + XUSB_PADCTL_SS_PORT_MAP);
1041         val &= ~SS_PORT_MAP(pad, ~0);
1042         val |= SS_PORT_MAP(pad, port_map);
1043         writel(val, pad_base + XUSB_PADCTL_SS_PORT_MAP);
1044
1045         val = readl(pad_base + XUSB_PADCTL_USB2_PORT_CAP_0);
1046         val &= ~USB2_OTG_PORT_CAP(port_map, ~0);
1047         val |= USB2_OTG_PORT_CAP(port_map, cap);
1048         writel(val, pad_base + XUSB_PADCTL_USB2_PORT_CAP_0);
1049
1050         ss_pad_inited |= (1 << pad);
1051         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1052         pr_debug("[%s] ss pad %d\n", __func__ , pad);
1053         pr_debug("XUSB_PADCTL_SS_PORT_MAP = 0x%x\n"
1054                         , readl(pad_base + XUSB_PADCTL_SS_PORT_MAP));
1055
1056 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1057         /* read and print xusb prod settings for the SS pad */
1058         val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_2_0(pad));
1059         val &= XUSB_PADCTL_UPHY_USB3_ECTL_2_0_RX_CTLE_MASK;
1060         pr_debug("xusb_prod port%d RX_CTLE = 0x%lx\n", pad, val);
1061
1062         val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_3_0(pad));
1063         pr_debug("xusb_prod port%d RX_DFE = 0x%lx\n", pad, val);
1064
1065         val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_4_0(pad));
1066         val &= XUSB_PADCTL_UPHY_USB3_ECTL_4_0_RX_CDR_CTRL_MASK;
1067         pr_debug("xusb_prod port%d RX_CDR_CTRL = 0x%lx\n", pad, val >> 16);
1068
1069         val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_6_0(pad));
1070         pr_debug("xusb_prod port%d RX_EQ_CTRL_H = 0x%lx\n", pad, val);
1071 #endif
1072 }
1073 EXPORT_SYMBOL_GPL(xusb_ss_pad_init);
1074
1075 void usb2_vbus_id_init(void)
1076 {
1077         unsigned long val, flags;
1078         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1079
1080         spin_lock_irqsave(&xusb_padctl_lock, flags);
1081         val = readl(pad_base + XUSB_PADCTL_USB2_VBUS_ID_0);
1082         val &= ~(VBUS_SOURCE_SELECT(~0) | ID_SOURCE_SELECT(~0));
1083         val |= (VBUS_SOURCE_SELECT(1) | ID_SOURCE_SELECT(1));
1084         writel(val, pad_base + XUSB_PADCTL_USB2_VBUS_ID_0);
1085
1086         /* clear wrong status change */
1087         val = readl(pad_base + XUSB_PADCTL_USB2_VBUS_ID_0);
1088         writel(val, pad_base + XUSB_PADCTL_USB2_VBUS_ID_0);
1089
1090         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1091         pr_debug("[%s] VBUS_ID\n", __func__);
1092         pr_debug("XUSB_PADCTL_USB2_VBUS_ID_0 = 0x%x\n"
1093                         , readl(pad_base + XUSB_PADCTL_USB2_VBUS_ID_0));
1094 }
1095 EXPORT_SYMBOL_GPL(usb2_vbus_id_init);
1096
1097 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1098 static void tegra_xusb_uphy_misc(bool ovrd, enum padctl_lane lane)
1099 {
1100         unsigned long val;
1101         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1102         u16 misc_pad_ctl2_regs[] = {
1103                 [PEX_P0] = XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2,
1104                 [PEX_P1] = XUSB_PADCTL_UPHY_MISC_PAD_P1_CTL2,
1105                 [PEX_P2] = XUSB_PADCTL_UPHY_MISC_PAD_P2_CTL2,
1106                 [PEX_P3] = XUSB_PADCTL_UPHY_MISC_PAD_P3_CTL2,
1107                 [PEX_P4] = XUSB_PADCTL_UPHY_MISC_PAD_P4_CTL2,
1108                 [PEX_P5] = XUSB_PADCTL_UPHY_MISC_PAD_P5_CTL2,
1109                 [PEX_P6] = XUSB_PADCTL_UPHY_MISC_PAD_P6_CTL2,
1110                 [SATA_S0] = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2,
1111         };
1112
1113         if ((lane < LANE_MIN) || (lane > LANE_MAX)) {
1114                 pr_warn("%s invalid lane number %d\n", __func__, lane);
1115                 return;
1116         }
1117
1118         pr_debug("%s lane %d override IDDQ %d\n", __func__, lane, ovrd);
1119
1120         /* WAR: Override pad controls and keep UPHy under IDDQ and */
1121         /* SLEEP 3 state during lane ownership changes and powergating */
1122         val = readl(pad_base + misc_pad_ctl2_regs[lane]);
1123         if (ovrd) {
1124                 /* register bit-fields are same across all lanes */
1125                 val |= XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_TX_IDDQ |
1126                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_RX_IDDQ |
1127                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_TX_IDDQ_OVRD |
1128                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_RX_IDDQ_OVRD |
1129                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_TX_SLEEP |
1130                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_RX_SLEEP |
1131                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_TX_PWR_OVRD |
1132                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_RX_PWR_OVRD;
1133                 udelay(1);
1134         } else {
1135                 val &= ~(XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_TX_PWR_OVRD |
1136                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_RX_PWR_OVRD |
1137                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_TX_IDDQ_OVRD |
1138                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2_RX_IDDQ_OVRD);
1139         }
1140         writel(val, pad_base + misc_pad_ctl2_regs[lane]);
1141 }
1142
1143 static void usb3_pad_mux_set(u8 lane)
1144 {
1145         unsigned long val;
1146         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1147
1148         if (lane == USB3_LANE_NOT_ENABLED)
1149                 return;
1150         val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1151         val &= ~PAD_MUX_PAD_LANE(lane, ~0);
1152         val |= PAD_MUX_PAD_LANE(lane, 1);
1153         writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1154
1155 }
1156
1157 static void usb3_lane_out_of_iddq(u8 lane)
1158 {
1159         unsigned long val;
1160         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1161
1162         if (lane == USB3_LANE_NOT_ENABLED)
1163                 return;
1164         /* Bring enabled lane out of IDDQ */
1165         val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1166         val |= PAD_MUX_PAD_LANE_IDDQ(lane, 1);
1167         writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1168 }
1169
1170 static void usb3_release_padmux_state_latch(void)
1171 {
1172         unsigned long val;
1173         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1174
1175         /* clear AUX_MUX_LP0 related bits in ELPG_PROGRAM_1 */
1176         udelay(1);
1177
1178         val = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
1179         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
1180         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
1181
1182         udelay(100);
1183
1184         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
1185         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
1186
1187         udelay(100);
1188
1189         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
1190         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_1);
1191
1192 }
1193
1194 static int tegra_xusb_padctl_phy_enable(void);
1195 static void tegra_xusb_padctl_phy_disable(void);
1196 static int usb3_phy_refcnt = 0x0;
1197
1198 void usb3_phy_pad_disable(void)
1199 {
1200         unsigned long flags;
1201         spin_lock_irqsave(&xusb_padctl_lock, flags);
1202
1203         pr_debug("%s usb3_phy_refcnt %d\n", __func__, usb3_phy_refcnt);
1204
1205         usb3_phy_refcnt--;
1206         if (usb3_phy_refcnt == 0)
1207                 tegra_xusb_padctl_phy_disable();
1208
1209         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1210 }
1211
1212 /*
1213  * Have below lane define used for each port
1214  * PCIE_LANEP6 0x6
1215  * PCIE_LANEP5 0x5
1216  * PCIE_LANEP4 0x4
1217  * PCIE_LANEP3 0x3
1218  * PCIE_LANEP2 0x2
1219  * PCIE_LANEP1 0x1
1220  * PCIE_LANEP0 0x0
1221  * SATA_LANE   0x8
1222  * NOT_SUPPORTED        0xF
1223  */
1224 int usb3_phy_pad_enable(u32 lane_owner)
1225 {
1226         unsigned long flags;
1227         int pad;
1228         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1229
1230         pr_debug("%s usb3_phy_refcnt %d\n", __func__, usb3_phy_refcnt);
1231         spin_lock_irqsave(&xusb_padctl_lock, flags);
1232
1233         if (usb3_phy_refcnt > 0)
1234                 goto done;
1235
1236         /* Program SATA pad phy */
1237         if ((lane_owner & 0xf000) == SATA_LANE)
1238                 t210_sata_uphy_pll_init(true);
1239
1240         tegra_xusb_padctl_phy_enable();
1241
1242         /* Check PCIe/SATA pad phy programmed */
1243         pr_debug("[%s] PCIe pad/ SATA pad phy parameter\n", __func__);
1244         pr_debug("XUSB_PADCTL_UPHY_PLL_S0_CTL_1_0 = 0x%x\n"
1245                         , readl(pad_base + XUSB_PADCTL_UPHY_PLL_S0_CTL_1_0));
1246         pr_debug("XUSB_PADCTL_UPHY_PLL_S0_CTL_2_0 = 0x%x\n"
1247                         , readl(pad_base + XUSB_PADCTL_UPHY_PLL_S0_CTL_2_0));
1248         pr_debug("XUSB_PADCTL_UPHY_PLL_S0_CTL_4_0 = 0x%x\n"
1249                         , readl(pad_base + XUSB_PADCTL_UPHY_PLL_S0_CTL_4_0));
1250         pr_debug("XUSB_PADCTL_UPHY_PLL_S0_CTL_5_0 = 0x%x\n"
1251                         , readl(pad_base + XUSB_PADCTL_UPHY_PLL_S0_CTL_5_0));
1252         pr_debug("XUSB_PADCTL_UPHY_PLL_P0_CTL2_0 = 0x%x\n"
1253                         , readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0));
1254         pr_debug("XUSB_PADCTL_UPHY_PLL_P0_CTL5_0 = 0x%x\n"
1255                         , readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL5_0));
1256
1257         for (pad = 0; pad < SS_PAD_COUNT; pad++) {
1258                 u8 lane = (lane_owner >> (pad * 4)) & 0xf;
1259                 enum padctl_lane lane_enum = usb3_laneowner_to_lane_enum(lane);
1260
1261                 if (lane == USB3_LANE_NOT_ENABLED)
1262                         continue;
1263                 tegra_xusb_uphy_misc(true, lane_enum);
1264                 usb3_pad_mux_set(lane);
1265                 tegra_xusb_uphy_misc(false, lane_enum);
1266         }
1267
1268         pr_debug("[%s] ss pad mux\n", __func__);
1269         pr_debug("XUSB_PADCTL_USB3_PAD_MUX_0 = 0x%x\n"
1270                         , readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0));
1271
1272         /* Bring out of IDDQ */
1273         for (pad = 0; pad < SS_PAD_COUNT; pad++)
1274                 usb3_lane_out_of_iddq((lane_owner >> (pad * 4)) & 0xf);
1275
1276         pr_debug("ss lane exit IDDQ\n");
1277         pr_debug("XUSB_PADCTL_USB3_PAD_MUX_0 = 0x%x\n"
1278                         , readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0));
1279
1280         pr_debug("ss release state latching\n");
1281         pr_debug("XUSB_PADCTL_ELPG_PROGRAM_1 = 0x%x\n"
1282                         , readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_1));
1283
1284 done:
1285         usb3_phy_refcnt++;
1286         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1287         return 0;
1288 }
1289
1290 #else
1291 void usb3_phy_pad_disable(void) {}
1292
1293 int usb3_phy_pad_enable(u32 lane_owner)
1294 {
1295         unsigned long val, flags;
1296         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1297
1298         spin_lock_irqsave(&xusb_padctl_lock, flags);
1299
1300         /* Program SATA pad phy */
1301         if (lane_owner & BIT(0)) {
1302                 void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
1303
1304                 val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1305                 val &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0_PLL0_REFCLK_NDIV_MASK;
1306                 val |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0_PLL0_REFCLK_NDIV;
1307                 writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1308
1309                 val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0);
1310                 val &= ~(XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_XDIGCLK_SEL_MASK |
1311                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_TXCLKREF_SEL |
1312                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_TCLKOUT_EN |
1313                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_PLL0_CP_CNTL_MASK |
1314                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_PLL1_CP_CNTL_MASK);
1315                 val |= XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_XDIGCLK_SEL |
1316                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_TXCLKREF_SEL |
1317                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_PLL0_CP_CNTL |
1318                         XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0_PLL1_CP_CNTL;
1319
1320                 writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_S0_CTL2_0);
1321
1322                 val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_S0_CTL3_0);
1323                 val &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL3_0_RCAL_BYPASS;
1324                 writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_S0_CTL3_0);
1325
1326                 /* Enable SATA PADPLL clocks */
1327                 val = readl(clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1328                 val &= ~SATA_PADPLL_RESET_SWCTL;
1329                 val |= SATA_PADPLL_USE_LOCKDET | SATA_SEQ_START_STATE;
1330                 writel(val, clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1331
1332                 udelay(1);
1333
1334                 val = readl(clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1335                 val |= SATA_SEQ_ENABLE;
1336                 writel(val, clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1337         }
1338
1339         if ((lane_owner & BIT(1)) || (lane_owner & BIT(2))) {
1340                 val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_0);
1341                 val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL2_PLL0_CP_CNTL_MASK;
1342                 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_PLL0_CP_CNTL_VAL;
1343                 writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_0);
1344         }
1345
1346         /*
1347          * program ownership of lanes owned by USB3 based on odmdata[28:30]
1348          * odmdata[28] = 0 (SATA lane owner = SATA),
1349          * odmdata[28] = 1 (SATA lane owner = USB3_SS port1)
1350          * odmdata[29] = 0 (PCIe lane1 owner = PCIe),
1351          * odmdata[29] = 1 (PCIe lane1 owner = USB3_SS port1)
1352          * odmdata[30] = 0 (PCIe lane0 owner = PCIe),
1353          * odmdata[30] = 1 (PCIe lane0 owner = USB3_SS port0)
1354          * FIXME: Check any GPIO settings needed ?
1355          */
1356         val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1357         /* USB3_SS port1 can either be mapped to SATA lane or PCIe lane1 */
1358         if (lane_owner & BIT(0)) {
1359                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0;
1360                 val |= XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_OWNER_USB3_SS;
1361         } else if (lane_owner & BIT(1)) {
1362                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1;
1363                 val |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1_OWNER_USB3_SS;
1364         }
1365         /* USB_SS port0 is alwasy mapped to PCIe lane0 */
1366         if (lane_owner & BIT(2)) {
1367                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0;
1368                 val |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0_OWNER_USB3_SS;
1369         }
1370         writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1371
1372         /* Bring enabled lane out of IDDQ */
1373         val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1374         if (lane_owner & BIT(0))
1375                 val |= XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
1376         else if (lane_owner & BIT(1))
1377                 val |= XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
1378         if (lane_owner & BIT(2))
1379                 val |= XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
1380         writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1381
1382         udelay(1);
1383
1384         /* clear AUX_MUX_LP0 related bits in ELPG_PROGRAM */
1385         val = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
1386         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
1387         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
1388
1389         udelay(100);
1390
1391         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
1392         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
1393
1394         udelay(100);
1395
1396         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
1397         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
1398
1399         usb_lanes = lane_owner;
1400
1401         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1402         return 0;
1403 }
1404
1405 #endif
1406 EXPORT_SYMBOL_GPL(usb3_phy_pad_enable);
1407 EXPORT_SYMBOL_GPL(usb3_phy_pad_disable);
1408
1409 void tegra_usb_pad_reg_update(u32 reg_offset, u32 mask, u32 val)
1410 {
1411         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1412         unsigned long flags;
1413         u32 reg;
1414
1415         spin_lock_irqsave(&xusb_padctl_reg_lock, flags);
1416
1417         reg = readl(pad_base + reg_offset);
1418         reg &= ~mask;
1419         reg |= val;
1420         writel(reg, pad_base + reg_offset);
1421
1422         spin_unlock_irqrestore(&xusb_padctl_reg_lock, flags);
1423 }
1424 EXPORT_SYMBOL_GPL(tegra_usb_pad_reg_update);
1425
1426 u32 tegra_usb_pad_reg_read(u32 reg_offset)
1427 {
1428         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1429         unsigned long flags;
1430         u32 reg;
1431
1432         spin_lock_irqsave(&xusb_padctl_reg_lock, flags);
1433         reg = readl(pad_base + reg_offset);
1434         spin_unlock_irqrestore(&xusb_padctl_reg_lock, flags);
1435
1436         return reg;
1437 }
1438 EXPORT_SYMBOL_GPL(tegra_usb_pad_reg_read);
1439
1440 void tegra_usb_pad_reg_write(u32 reg_offset, u32 val)
1441 {
1442         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1443         unsigned long flags;
1444         spin_lock_irqsave(&xusb_padctl_reg_lock, flags);
1445         writel(val, pad_base + reg_offset);
1446         spin_unlock_irqrestore(&xusb_padctl_reg_lock, flags);
1447 }
1448 EXPORT_SYMBOL_GPL(tegra_usb_pad_reg_write);
1449
1450 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1451 int t210_sata_uphy_pll_init(bool sata_used_by_xusb)
1452 {
1453         u32 val;
1454         int calib_timeout;
1455         u8 freq_ndiv;
1456         u8 txclkref_sel;
1457         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
1458
1459         val = readl(clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1460         if (SATA_SEQ_ENABLE & val) {
1461                 pr_info("%s: sata uphy already enabled\n", __func__);
1462                 return 0;
1463         }
1464
1465         pr_info("%s: init sata uphy pll\n", __func__);
1466
1467         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0,
1468                 S0_CTL2_PLL0_CAL_CTRL(~0),
1469                 S0_CTL2_PLL0_CAL_CTRL(0x136));
1470
1471         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL5_0,
1472                 S0_CTL5_PLL0_DCO_CTRL(~0),
1473                 S0_CTL5_PLL0_DCO_CTRL(0x2a));
1474
1475         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL1_0,
1476                 S0_CTL1_PLL0_PWR_OVRD, S0_CTL1_PLL0_PWR_OVRD);
1477
1478         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0,
1479                 S0_CTL2_PLL0_CAL_OVRD, S0_CTL2_PLL0_CAL_OVRD);
1480
1481         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0,
1482                 S0_CTL8_PLL0_RCAL_OVRD, S0_CTL8_PLL0_RCAL_OVRD);
1483
1484         pr_info("%s %s uses SATA Lane\n", __func__,
1485                         sata_used_by_xusb ? "XUSB" : "SATA");
1486
1487         if (sata_used_by_xusb) {
1488                 txclkref_sel = 0x2;
1489                 freq_ndiv = 0x19;
1490         } else {
1491                 txclkref_sel = 0x0;
1492                 freq_ndiv = 0x1e;
1493         }
1494
1495         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL4_0,
1496                 S0_PLL0_TXCLKREF_SEL(~0), S0_PLL0_TXCLKREF_SEL(txclkref_sel));
1497
1498         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL1_0,
1499                 S0_PLL0_FREQ_NDIV(~0), S0_PLL0_FREQ_NDIV(freq_ndiv));
1500
1501         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL1_0,
1502                 (S0_CTL1_PLL0_IDDQ | S0_CTL1_PLL0_SLEEP), 0);
1503
1504         udelay(1);
1505
1506         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0,
1507                 S0_CTL2_PLL0_CAL_EN, S0_CTL2_PLL0_CAL_EN);
1508
1509         calib_timeout = 20; /* 200 us in total */
1510         do {
1511                 val = tegra_usb_pad_reg_read(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0);
1512                 udelay(10);
1513                 if (--calib_timeout == 0) {
1514                         pr_err("%s: timeout for CAL_DONE set\n", __func__);
1515                         break;
1516                 }
1517         } while (!(val & S0_CTL2_PLL0_CAL_DONE));
1518
1519         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0,
1520                 S0_CTL2_PLL0_CAL_EN, 0);
1521
1522         calib_timeout = 20; /* 200 us in total */
1523         do {
1524                 val = tegra_usb_pad_reg_read(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0);
1525                 udelay(10);
1526                 if (--calib_timeout == 0) {
1527                         pr_err("%s: timeout for CAL_DONE clear\n", __func__);
1528                         break;
1529                 }
1530         } while (val & S0_CTL2_PLL0_CAL_DONE);
1531
1532         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL1_0,
1533                 S0_CTL1_PLL0_ENABLE, S0_CTL1_PLL0_ENABLE);
1534
1535         calib_timeout = 20; /* 200 us in total */
1536         do {
1537                 val = tegra_usb_pad_reg_read(XUSB_PADCTL_UPHY_PLL_S0_CTL1_0);
1538                 udelay(10);
1539                 if (--calib_timeout == 0) {
1540                         pr_err("%s: timeout for LOCKDET set\n", __func__);
1541                         break;
1542                 }
1543         } while (!(val & S0_CTL1_PLL0_LOCKDET_STATUS));
1544
1545         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0,
1546                 S0_CTL8_PLL0_RCAL_EN, S0_CTL8_PLL0_RCAL_EN);
1547
1548         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0,
1549                 S0_CTL8_PLL0_RCAL_CLK_EN, S0_CTL8_PLL0_RCAL_CLK_EN);
1550
1551         calib_timeout = 20; /* 200 us in total */
1552         do {
1553                 val = tegra_usb_pad_reg_read(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0);
1554                 udelay(10);
1555                 if (--calib_timeout == 0) {
1556                         pr_err("%s: timeout for RCAL_DONE set\n", __func__);
1557                         break;
1558                 }
1559         } while (!(val & S0_CTL8_PLL0_RCAL_DONE));
1560
1561         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0,
1562                 S0_CTL8_PLL0_RCAL_EN, 0);
1563
1564         calib_timeout = 20; /* 200 us in total */
1565         do {
1566                 val = tegra_usb_pad_reg_read(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0);
1567                 udelay(10);
1568                 if (--calib_timeout == 0) {
1569                         pr_err("%s: timeout for RCAL_DONE clear\n", __func__);
1570                         break;
1571                 }
1572         } while (val & S0_CTL8_PLL0_RCAL_DONE);
1573
1574         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0,
1575                 S0_CTL8_PLL0_RCAL_CLK_EN, 0);
1576
1577         /* Enable SATA PADPLL HW power sequencer */
1578         val = readl(clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1579         val &= ~SATA_PADPLL_RESET_SWCTL;
1580         val |= SATA_PADPLL_USE_LOCKDET | SATA_PADPLL_SLEEP_IDDQ;
1581         writel(val, clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1582
1583         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL1_0,
1584                 S0_CTL1_PLL0_PWR_OVRD, 0);
1585
1586         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL2_0,
1587                 S0_CTL2_PLL0_CAL_OVRD, 0);
1588
1589         tegra_usb_pad_reg_update(XUSB_PADCTL_UPHY_PLL_S0_CTL8_0,
1590                 S0_CTL8_PLL0_RCAL_OVRD, 0);
1591
1592         udelay(1);
1593         val = readl(clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1594         val |= SATA_SEQ_ENABLE;
1595         writel(val, clk_base + CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1596
1597         return 0;
1598 }
1599 EXPORT_SYMBOL_GPL(t210_sata_uphy_pll_init);
1600
1601 static int pex_pll_refcnt;
1602 static void tegra_xusb_padctl_phy_disable(void)
1603 {
1604         pr_debug("%s pex_pll_refcnt %d\n", __func__, pex_pll_refcnt);
1605         pex_pll_refcnt--;
1606 }
1607
1608 static int tegra_xusb_padctl_phy_enable(void)
1609 {
1610         unsigned long val, timeout;
1611         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1612         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
1613
1614         pr_debug("%s pex_pll_refcnt %d\n", __func__, pex_pll_refcnt);
1615
1616         if (pex_pll_refcnt > 0)
1617                 goto done; /* already done */
1618
1619         val = readl(clk_base + CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0);
1620         if (XUSBIO_SEQ_ENABLE & val) {
1621                 pr_info("%s: pex uphy already enabled\n", __func__);
1622                 goto done;
1623         }
1624
1625         pr_info("%s: init pex uphy pll\n", __func__);
1626
1627         /* Enable overrides to enable SW control over PLL */
1628         /* init UPHY, Set PWR/CAL/RCAL OVRD */
1629         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1630         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
1631         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL;
1632         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1633
1634         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL5_0);
1635         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
1636         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL;
1637         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL5_0);
1638
1639         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1640         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
1641         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1642
1643         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1644         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
1645         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1646
1647         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1648         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
1649         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1650
1651         /* Select REFCLK, TXCLKREF and Enable */
1652         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL4_0);
1653         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL_MASK;
1654         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL_MASK;
1655         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL;
1656         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN;
1657         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL4_0);
1658
1659         /* FREQ_MDIV & FREQ_NDIV programming for 500 MHz */
1660         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1661         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV_MASK;
1662         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV_MASK;
1663         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV;
1664         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1665
1666         /* Clear PLL0 iddq and sleep */
1667         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1668         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_IDDQ;
1669         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1670         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1671         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_SLEEP;
1672         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1673         udelay(1);
1674
1675         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL4_0);
1676         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN;
1677         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL4_0);
1678
1679         /* Perform PLL calibration */
1680         /* Set PLL0_CAL_EN and wait for PLL0_CAL_DONE being set */
1681         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1682         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
1683         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1684         timeout = 20;
1685         do {
1686                 val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1687                 udelay(10);
1688                 if (--timeout == 0) {
1689                         pr_err("PCIe error: timeout for PLL0_CAL_DONE set\n");
1690                         break;
1691                 }
1692         } while (!(val & XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_DONE));
1693
1694         /* Clear PLL0_CAL_EN and wait for PLL0_CAL_DONE being cleared */
1695         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1696         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
1697         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1698         timeout = 20;
1699         do {
1700                 val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1701                 udelay(10);
1702                 if (--timeout == 0) {
1703                         pr_err("PCIe error: timeout for PLL0_CAL_DONE cleared\n");
1704                         break;
1705                 }
1706         } while (val & XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_DONE);
1707
1708         /* Set PLL0_ENABLE */
1709         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1710         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_ENABLE;
1711         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1712
1713         /* Wait for the PLL to lock */
1714         timeout = 20;
1715         do {
1716                 val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1717                 udelay(10);
1718                 if (--timeout == 0) {
1719                         pr_err("Tegra PCIe error: timeout waiting for PLL\n");
1720                         break;
1721                 }
1722         } while (!(val & XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS));
1723
1724         /* Perform register calibration */
1725         /* Set PLL0_RCAL_EN and wait for PLL0_RCAL_DONE being set */
1726         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1727         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
1728         val |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
1729         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1730         timeout = 10;
1731         do {
1732                 val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1733                 udelay(1);
1734                 if (--timeout == 0) {
1735                         pr_err("PCIe error: timeout for PLL0_RCAL_DONE set\n");
1736                         break;
1737                 }
1738         } while (!(val & XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE));
1739
1740         /* Clear PLL0_RCAL_EN and wait for PLL0_RCAL_DONE being cleared */
1741         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1742         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
1743         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1744         timeout = 10;
1745         do {
1746                 val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1747                 udelay(1);
1748                 if (--timeout == 0) {
1749                         pr_err("PCIe error: timeout for PLL0_RCAL_DONE cleared\n");
1750                         break;
1751                 }
1752         } while (val & XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE);
1753
1754         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1755         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
1756         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1757
1758         /* Enable PEX PADPLL clocks */
1759         val = readl(clk_base + CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0);
1760         val &= ~XUSBIO_CLK_ENABLE_SWCTL;
1761         val &= ~XUSBIO_PADPLL_RESET_SWCTL;
1762         val |= XUSBIO_PADPLL_USE_LOCKDET | XUSBIO_PADPLL_SLEEP_IDDQ;
1763         writel(val, clk_base + CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0);
1764
1765         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1766         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
1767         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL1_0);
1768
1769         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1770         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
1771         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL2_0);
1772
1773         val = readl(pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1774         val &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
1775         writel(val, pad_base + XUSB_PADCTL_UPHY_PLL_P0_CTL8_0);
1776
1777         udelay(1);
1778         val = readl(clk_base + CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0);
1779         val |= XUSBIO_SEQ_ENABLE;
1780         writel(val, clk_base + CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0);
1781
1782 done:
1783         pex_pll_refcnt++;
1784         return 0;
1785 }
1786 #else
1787 static void tegra_xusb_padctl_phy_disable(void)
1788 {
1789
1790 }
1791 static int tegra_xusb_padctl_phy_enable(void)
1792 {
1793         unsigned long val, timeout;
1794         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1795
1796         /* set up PLL inputs in PLL_CTL1 */
1797         val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
1798         val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
1799         val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL;
1800         writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
1801
1802         /* set TX ref sel to div5 in PLL_CTL2 */
1803         /* T124 is div5 while T30 is div10,beacuse CAR will divide 2 */
1804         /* in GEN1 mode in T124,and if div10,it will be 125MHZ */
1805         val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_0);
1806         val |= (XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
1807                 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
1808                 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL);
1809         writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_0);
1810 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1811         /* recommended prod setting */
1812         val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_0);
1813         val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL2_PLL0_CP_CNTL_MASK;
1814         val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_PLL0_CP_CNTL_VAL;
1815         writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL2_0);
1816 #endif
1817         /* take PLL out of reset */
1818         val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
1819         val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST_;
1820         writel(val, pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
1821
1822         /* Wait for the PLL to lock */
1823         timeout = 300;
1824         do {
1825                 val = readl(pad_base + XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
1826                 udelay(100);
1827                 if (--timeout == 0) {
1828                         pr_err("Tegra PCIe error: timeout waiting for PLL\n");
1829                         return -EBUSY;
1830                 }
1831         } while (!(val & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET));
1832
1833         return 0;
1834 }
1835 #endif
1836
1837 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1838 static void t210_padctl_force_sata_seq(bool force_off)
1839 {
1840         u32 val;
1841         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
1842
1843         val = readl(clk_base +
1844                         CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1845
1846         if (force_off)
1847                 val |= (SATA_SEQ_IN_SWCTL |
1848                                 SATA_SEQ_RESET_INPUT_VALUE |
1849                                 SATA_SEQ_LANE_PD_INPUT_VALUE |
1850                                 SATA_SEQ_PADPLL_PD_INPUT_VALUE);
1851         else
1852                 val &= ~(SATA_SEQ_IN_SWCTL |
1853                                 SATA_SEQ_RESET_INPUT_VALUE |
1854                                 SATA_SEQ_LANE_PD_INPUT_VALUE |
1855                                 SATA_SEQ_PADPLL_PD_INPUT_VALUE);
1856
1857         writel(val, clk_base +
1858                         CLK_RST_CONTROLLER_SATA_PLL_CFG0_0);
1859 }
1860
1861 static void t210_padctl_enable_sata_idle_detector(bool enable)
1862 {
1863         if (enable)
1864                 tegra_usb_pad_reg_update(
1865                         XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL_1_0,
1866                         AUX_RX_TERM_EN | AUX_RX_MODE_OVRD |
1867                                 AUX_TX_IDDQ | AUX_TX_IDDQ_OVRD |
1868                                 AUX_RX_IDLE_EN,
1869                         AUX_RX_IDLE_EN);
1870         else
1871                 tegra_usb_pad_reg_update(
1872                         XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL_1_0,
1873                         AUX_RX_TERM_EN | AUX_RX_MODE_OVRD |
1874                                 AUX_TX_IDDQ | AUX_TX_IDDQ_OVRD |
1875                                 AUX_RX_IDLE_EN,
1876                         AUX_RX_TERM_EN | AUX_RX_MODE_OVRD |
1877                                 AUX_TX_IDDQ | AUX_TX_IDDQ_OVRD);
1878 }
1879 #endif
1880
1881 int tegra_padctl_init_sata_pad(void)
1882 {
1883 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1884         unsigned long flags;
1885
1886         if (sata_usb_pad_pll_reset_deassert())
1887                 pr_err("%s: fail to deassert sata uphy\n",
1888                         __func__);
1889
1890         spin_lock_irqsave(&xusb_padctl_lock, flags);
1891         if (t210_sata_uphy_pll_init(false))
1892                 pr_err("%s: fail to init sata uphy\n",
1893                         __func__);
1894         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1895
1896         /* this is only to decrease refcnt */
1897         sata_usb_pad_pll_reset_assert();
1898
1899         spin_lock_irqsave(&xusb_padctl_lock, flags);
1900         tegra_usb_pad_reg_update(
1901                 XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL_1_0,
1902                 AUX_RX_MODE_OVRD | AUX_RX_IDLE_EN |
1903                         AUX_RX_IDLE_TH(0x3),
1904                 AUX_RX_MODE_OVRD | AUX_RX_IDLE_EN |
1905                         AUX_RX_IDLE_TH(0x1));
1906         usb3_lane_out_of_iddq(SATA_S0);
1907         usb3_release_padmux_state_latch();
1908         udelay(200);
1909         tegra_usb_pad_reg_update(
1910                 XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL_4_0,
1911                 RX_TERM_EN | RX_TERM_OVRD,
1912                 RX_TERM_EN | RX_TERM_OVRD);
1913         t210_padctl_force_sata_seq(false);
1914         t210_padctl_enable_sata_idle_detector(true);
1915         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1916 #endif
1917
1918         return 0;
1919 }
1920 EXPORT_SYMBOL_GPL(tegra_padctl_init_sata_pad);
1921
1922 int tegra_padctl_enable_sata_pad(bool enable)
1923 {
1924 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1925         unsigned long flags;
1926
1927         spin_lock_irqsave(&xusb_padctl_lock, flags);
1928
1929         if (enable) {
1930                 t210_padctl_enable_sata_idle_detector(true);
1931                 t210_padctl_force_sata_seq(false);
1932                 tegra_xusb_uphy_misc(false, SATA_S0);
1933         } else {
1934                 t210_padctl_force_sata_seq(true);
1935                 tegra_xusb_uphy_misc(true, SATA_S0);
1936                 t210_padctl_enable_sata_idle_detector(false);
1937         }
1938
1939         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
1940 #endif
1941
1942         return 0;
1943 }
1944 EXPORT_SYMBOL_GPL(tegra_padctl_enable_sata_pad);
1945
1946 static int tegra_pcie_lane_iddq(bool enable, int lane_owner)
1947 {
1948         unsigned long val;
1949         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1950
1951 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
1952         /*
1953          * USB 3.0 lanes and PCIe lanes are shared
1954          *
1955          * Honour the XUSB lane ownership information while modifying
1956          * the controls for PCIe
1957          */
1958         bool pcie_modify_lane0_iddq = (usb_lanes & BIT(2)) ? false : true;
1959         bool pcie_modify_lane1_iddq =
1960                 (!(usb_lanes & BIT(0)) && (usb_lanes & BIT(1))) ? false : true;
1961 #endif
1962
1963         val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
1964         switch (lane_owner) {
1965 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1966         case PCIE_LANES_X4_X1:
1967         if (enable)
1968                 val |=
1969                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
1970         else
1971                 val &=
1972                 ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
1973         case PCIE_LANES_X4_X0:
1974         if (enable)
1975                 val |=
1976                 (XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 |
1977                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 |
1978                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 |
1979                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4);
1980         else
1981                 val &=
1982                 ~(XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 |
1983                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 |
1984                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 |
1985                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4);
1986                 break;
1987         case PCIE_LANES_X2_X1:
1988         if (enable)
1989                 val |=
1990                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
1991         else
1992                 val &=
1993                 ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
1994         case PCIE_LANES_X2_X0:
1995         if (enable)
1996                 val |=
1997                 (XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 |
1998                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2);
1999         else
2000                 val &=
2001                 ~(XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 |
2002                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2);
2003                 break;
2004         case PCIE_LANES_X0_X1:
2005         if (enable)
2006                 val |=
2007                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
2008         else
2009                 val &=
2010                 ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
2011                 break;
2012 #else
2013         case PCIE_LANES_X4_X1:
2014         if (pcie_modify_lane0_iddq) {
2015                 if (enable)
2016                         val |=
2017                         XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
2018                 else
2019                         val &=
2020                         ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
2021         }
2022         case PCIE_LANES_X4_X0:
2023         if (pcie_modify_lane1_iddq) {
2024                 if (enable)
2025                         val |=
2026                         XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
2027                 else
2028                         val &=
2029                         ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
2030         }
2031         case PCIE_LANES_X2_X1:
2032         if (enable)
2033                 val |=
2034                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
2035         else
2036                 val &=
2037                 ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
2038         case PCIE_LANES_X2_X0:
2039         if (enable)
2040                 val |=
2041                 (XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 |
2042                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4);
2043         else
2044                 val &=
2045                 ~(XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 |
2046                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4);
2047                 break;
2048         case PCIE_LANES_X0_X1:
2049         if (enable)
2050                 val |=
2051                 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
2052         else
2053                 val &=
2054                 ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
2055                 break;
2056 #endif
2057         default:
2058                 pr_err("Tegra PCIe IDDQ error: wrong lane config\n");
2059                 return -ENXIO;
2060         }
2061         writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
2062         return 0;
2063 }
2064
2065 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2066 static void tegra_pcie_lane_aux_idle(bool ovdr, int lane)
2067 {
2068         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
2069         unsigned long val;
2070         u16 misc_pad_ctl1_regs[] = {
2071                 [PEX_P0] = XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL2,
2072                 [PEX_P1] = XUSB_PADCTL_UPHY_MISC_PAD_P1_CTL2,
2073                 [PEX_P2] = XUSB_PADCTL_UPHY_MISC_PAD_P2_CTL2,
2074                 [PEX_P3] = XUSB_PADCTL_UPHY_MISC_PAD_P3_CTL2,
2075                 [PEX_P4] = XUSB_PADCTL_UPHY_MISC_PAD_P4_CTL2,
2076         };
2077
2078         if (!ovdr)
2079                 return;
2080         /* reduce idle detect threshold for compliance purpose */
2081         val = readl(pad_base + misc_pad_ctl1_regs[lane]);
2082         val &= ~XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL1_AUX_RX_IDLE_TH_MASK;
2083         val |= XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL1_AUX_RX_IDLE_TH;
2084         writel(val, pad_base + misc_pad_ctl1_regs[lane]);
2085 }
2086
2087 bool tegra_phy_get_lane_rdet(u8 lane_num)
2088 {
2089         u32 data;
2090         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
2091
2092         switch (lane_num) {
2093         case 0:
2094                 data = readl(pad_base + XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL1);
2095                 data = data &
2096                         XUSB_PADCTL_UPHY_MISC_PAD_P0_CTL1_AUX_TX_RDET_STATUS;
2097                 break;
2098         case 1:
2099                 data = readl(pad_base + XUSB_PADCTL_UPHY_MISC_PAD_P1_CTL1);
2100                 data = data &
2101                         XUSB_PADCTL_UPHY_MISC_PAD_P1_CTL1_AUX_TX_RDET_STATUS;
2102                 break;
2103         case 2:
2104                 data = readl(pad_base + XUSB_PADCTL_UPHY_MISC_PAD_P2_CTL1);
2105                 data = data &
2106                         XUSB_PADCTL_UPHY_MISC_PAD_P2_CTL1_AUX_TX_RDET_STATUS;
2107                 break;
2108         case 3:
2109                 data = readl(pad_base + XUSB_PADCTL_UPHY_MISC_PAD_P3_CTL1);
2110                 data = data &
2111                         XUSB_PADCTL_UPHY_MISC_PAD_P3_CTL1_AUX_TX_RDET_STATUS;
2112                 break;
2113         case 4:
2114                 data = readl(pad_base + XUSB_PADCTL_UPHY_MISC_PAD_P4_CTL1);
2115                 data = data &
2116                         XUSB_PADCTL_UPHY_MISC_PAD_P4_CTL1_AUX_TX_RDET_STATUS;
2117                 break;
2118         default:
2119                 return 0;
2120         }
2121         return !(!data);
2122 }
2123 EXPORT_SYMBOL_GPL(tegra_phy_get_lane_rdet);
2124 #endif
2125
2126 static void tegra_pcie_lane_misc_pad_override(bool ovdr, int lane_owner)
2127 {
2128 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2129         switch (lane_owner) {
2130         case PCIE_LANES_X4_X1:
2131                 tegra_xusb_uphy_misc(ovdr, PEX_P0);
2132                 tegra_pcie_lane_aux_idle(ovdr, PEX_P0);
2133                 /* fall through */
2134         case PCIE_LANES_X4_X0:
2135                 tegra_xusb_uphy_misc(ovdr, PEX_P1);
2136                 tegra_pcie_lane_aux_idle(ovdr, PEX_P1);
2137                 tegra_xusb_uphy_misc(ovdr, PEX_P2);
2138                 tegra_pcie_lane_aux_idle(ovdr, PEX_P2);
2139                 tegra_xusb_uphy_misc(ovdr, PEX_P3);
2140                 tegra_pcie_lane_aux_idle(ovdr, PEX_P3);
2141                 tegra_xusb_uphy_misc(ovdr, PEX_P4);
2142                 tegra_pcie_lane_aux_idle(ovdr, PEX_P4);
2143                 break;
2144         case PCIE_LANES_X2_X1:
2145                 tegra_xusb_uphy_misc(ovdr, PEX_P0);
2146                 tegra_pcie_lane_aux_idle(ovdr, PEX_P0);
2147                 /* fall through */
2148         case PCIE_LANES_X2_X0:
2149                 tegra_xusb_uphy_misc(ovdr, PEX_P1);
2150                 tegra_pcie_lane_aux_idle(ovdr, PEX_P1);
2151                 tegra_xusb_uphy_misc(ovdr, PEX_P2);
2152                 tegra_pcie_lane_aux_idle(ovdr, PEX_P2);
2153                 break;
2154         case PCIE_LANES_X0_X1:
2155                 tegra_xusb_uphy_misc(ovdr, PEX_P0);
2156                 tegra_pcie_lane_aux_idle(ovdr, PEX_P0);
2157                 break;
2158         }
2159 #endif
2160 }
2161
2162 int pcie_phy_pad_enable(bool enable, int lane_owner)
2163 {
2164         unsigned long val, flags;
2165         void __iomem *pad_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
2166         int ret = 0;
2167 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
2168         bool pcie_modify_lane0_owner, pcie_modify_lane1_owner;
2169 #endif
2170
2171         spin_lock_irqsave(&xusb_padctl_lock, flags);
2172
2173 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
2174         /*
2175          * USB 3.0 lanes and PCIe lanes are shared
2176          *
2177          * Honour the XUSB lane ownership information while modifying
2178          * the controls for PCIe
2179          */
2180         pcie_modify_lane0_owner = (usb_lanes & BIT(2)) ? false : true;
2181         pcie_modify_lane1_owner =
2182                 (!(usb_lanes & BIT(0)) && (usb_lanes & BIT(1))) ? false : true;
2183 #endif
2184
2185         if (enable) {
2186                 ret = tegra_xusb_padctl_phy_enable();
2187                 if (ret)
2188                         goto exit;
2189         }
2190         ret = tegra_pcie_lane_iddq(enable, lane_owner);
2191         if (ret || !enable) {
2192                 if (!enable) {
2193                         tegra_xusb_padctl_phy_disable();
2194                         tegra_pcie_lane_misc_pad_override(true, lane_owner);
2195                 }
2196                 goto exit;
2197         }
2198
2199         /* clear AUX_MUX_LP0 related bits in ELPG_PROGRAM */
2200 #ifndef CONFIG_ARCH_TEGRA_21x_SOC
2201         val = readl(pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
2202         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
2203         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
2204         udelay(1);
2205         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
2206         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
2207         udelay(100);
2208         val &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
2209         writel(val, pad_base + XUSB_PADCTL_ELPG_PROGRAM_0);
2210         udelay(100);
2211 #endif
2212         tegra_pcie_lane_misc_pad_override(true, lane_owner);
2213
2214         val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
2215         switch (lane_owner) {
2216 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2217         case PCIE_LANES_X4_X1:
2218                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0;
2219         case PCIE_LANES_X4_X0:
2220                 val |= (XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1 |
2221                         XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE2 |
2222                         XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE3 |
2223                         XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE4);
2224                 break;
2225         case PCIE_LANES_X2_X1:
2226                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0;
2227         case PCIE_LANES_X2_X0:
2228                 val |= (XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1 |
2229                         XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE2);
2230                 break;
2231         case PCIE_LANES_X0_X1:
2232                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0;
2233                 break;
2234 #else
2235         case PCIE_LANES_X4_X1:
2236                 if (pcie_modify_lane0_owner)
2237                         val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0;
2238         case PCIE_LANES_X4_X0:
2239                 if (pcie_modify_lane1_owner)
2240                         val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1;
2241         case PCIE_LANES_X2_X1:
2242                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE2;
2243         case PCIE_LANES_X2_X0:
2244                 val &= ~(XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE3 |
2245                         XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE4);
2246                 break;
2247         case PCIE_LANES_X0_X1:
2248                 val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE2;
2249                 break;
2250 #endif
2251         default:
2252                 pr_err("Tegra PCIe error: wrong lane config\n");
2253                 ret = -ENXIO;
2254                 goto exit;
2255         }
2256         writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
2257         tegra_pcie_lane_misc_pad_override(false, lane_owner);
2258 exit:
2259         spin_unlock_irqrestore(&xusb_padctl_lock, flags);
2260         return ret;
2261 }
2262 EXPORT_SYMBOL_GPL(pcie_phy_pad_enable);
2263
2264 void xusb_enable_pad_protection(bool devmode)
2265 {
2266         u32 otgpad_ctl0 = tegra_usb_pad_reg_read(
2267                         XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(0));
2268
2269         otgpad_ctl0 &= ~(VREG_FIX18 | VREG_LEV);
2270
2271         otgpad_ctl0 |= devmode ? VREG_LEV_EN : VREG_FIX18;
2272
2273         tegra_usb_pad_reg_write(
2274                 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(0), otgpad_ctl0);
2275 }
2276 EXPORT_SYMBOL_GPL(xusb_enable_pad_protection);
2277
2278 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2279
2280 static int
2281 tegra_padctl_enable_regulator(struct platform_device *pdev)
2282 {
2283         int err = 0;
2284         struct tegra_padctl *padctl;
2285
2286         padctl = platform_get_drvdata(pdev);
2287
2288         err = regulator_bulk_enable(padctl->soc_data->num_regulator,
2289                 padctl->regulator);
2290         if (err)
2291                 dev_err(&pdev->dev, "fail to enable regulator %d\n", err);
2292
2293         return err;
2294 }
2295
2296 static void
2297 tegra_padctl_disable_regulator(struct platform_device *pdev)
2298 {
2299         int err = 0;
2300         struct tegra_padctl *padctl;
2301
2302         padctl = platform_get_drvdata(pdev);
2303
2304         err = regulator_bulk_disable(padctl->soc_data->num_regulator,
2305                 padctl->regulator);
2306         if (err)
2307                 dev_err(&pdev->dev, "fail to disable regulator %d\n", err);
2308 }
2309
2310 static int
2311 tegra_padctl_enable_plle(struct platform_device *pdev)
2312 {
2313         int err = 0;
2314         struct tegra_padctl *padctl;
2315
2316         padctl = platform_get_drvdata(pdev);
2317
2318         err = clk_enable(padctl->plle_clk);
2319         if (err)
2320                 dev_err(&pdev->dev, "fail to enable plle clock\n");
2321
2322         return err;
2323 }
2324
2325 static void
2326 tegra_padctl_disable_plle(struct platform_device *pdev)
2327 {
2328         struct tegra_padctl *padctl;
2329
2330         padctl = platform_get_drvdata(pdev);
2331
2332         clk_disable(padctl->plle_clk);
2333 }
2334
2335 static int
2336 tegra_padctl_enable_uphy_pll(struct platform_device *pdev)
2337 {
2338         int err = 0;
2339         struct tegra_padctl *padctl;
2340
2341         padctl = platform_get_drvdata(pdev);
2342
2343         err = pex_usb_pad_pll_reset_deassert();
2344         if (err) {
2345                 dev_err(&pdev->dev, "fail to deassert pex pll\n");
2346                 goto done;
2347         }
2348
2349         err = sata_usb_pad_pll_reset_deassert();
2350         if (err) {
2351                 dev_err(&pdev->dev, "fail to deassert sata pll\n");
2352                 goto done;
2353         }
2354
2355         if ((padctl->lane_owner & 0xf000) != SATA_LANE) {
2356                 /* sata driver owns sata lane */
2357                 t210_sata_uphy_pll_init(false);
2358                 usb3_lane_out_of_iddq(SATA_S0);
2359                 t210_padctl_enable_sata_idle_detector(false);
2360                 t210_padctl_force_sata_seq(true);
2361         }
2362
2363         usb3_phy_pad_enable(padctl->lane_owner);
2364
2365         if (padctl->lane_map)
2366                 pcie_phy_pad_enable(true, padctl->lane_map);
2367
2368         usb3_release_padmux_state_latch();
2369
2370 done:
2371         return err;
2372 }
2373
2374 static void
2375 tegra_padctl_disable_uphy_pll(struct platform_device *pdev)
2376 {
2377         struct tegra_padctl *padctl;
2378
2379         padctl = platform_get_drvdata(pdev);
2380
2381         usb3_phy_pad_disable();
2382
2383         if (padctl->lane_map)
2384                 pcie_phy_pad_enable(false, padctl->lane_map);
2385
2386         /* this doesn't assert uphy pll if sequencers are enabled */
2387         if (pex_usb_pad_pll_reset_assert())
2388                 dev_err(&pdev->dev, "fail to assert pex pll\n");
2389         if (sata_usb_pad_pll_reset_assert())
2390                 dev_err(&pdev->dev, "fail to assert sata pll\n");
2391 }
2392
2393 static int
2394 tegra_padctl_enable_plle_hw(struct platform_device *pdev)
2395 {
2396         int err = 0;
2397         struct tegra_padctl *padctl;
2398
2399         padctl = platform_get_drvdata(pdev);
2400
2401         err = clk_enable(padctl->plle_hw_clk);
2402         if (err)
2403                 dev_err(&pdev->dev, "fail to enable plle_hw\n");
2404
2405         return err;
2406 }
2407
2408 static void
2409 tegra_padctl_disable_plle_hw(struct platform_device *pdev)
2410 {
2411         struct tegra_padctl *padctl;
2412
2413         padctl = platform_get_drvdata(pdev);
2414
2415         clk_disable(padctl->plle_hw_clk);
2416 }
2417
2418 static int
2419 tegra_padctl_uphy_init(struct platform_device *pdev)
2420 {
2421         int err = 0;
2422
2423         err = tegra_padctl_enable_plle(pdev);
2424         if (err)
2425                 goto done;
2426
2427         err = tegra_padctl_enable_uphy_pll(pdev);
2428         if (err)
2429                 goto fail1;
2430
2431         err = tegra_padctl_enable_plle_hw(pdev);
2432         if (err)
2433                 goto fail2;
2434
2435         goto done;
2436
2437 fail2:
2438         tegra_padctl_disable_uphy_pll(pdev);
2439 fail1:
2440         tegra_padctl_disable_plle(pdev);
2441 done:
2442         return err;
2443 }
2444
2445 static void
2446 tegra_padctl_uphy_deinit(struct platform_device *pdev)
2447 {
2448         tegra_padctl_disable_plle_hw(pdev);
2449         tegra_padctl_disable_uphy_pll(pdev);
2450         tegra_padctl_disable_plle(pdev);
2451 }
2452
2453 static int
2454 tegra_padctl_get_regulator(struct platform_device *pdev)
2455 {
2456         int err = 0;
2457         struct tegra_padctl *padctl;
2458         const struct tegra_padctl_soc_data *soc_data;
2459         size_t size;
2460         int i;
2461
2462         padctl = platform_get_drvdata(pdev);
2463         soc_data = padctl->soc_data;
2464
2465         size = soc_data->num_regulator *
2466                 sizeof(struct regulator_bulk_data);
2467         padctl->regulator = devm_kzalloc(&pdev->dev, size, GFP_ATOMIC);
2468         if (IS_ERR(padctl->regulator)) {
2469                 dev_err(&pdev->dev, "fail to alloc regulator\n");
2470                 err = -ENOMEM;
2471                 goto done;
2472         }
2473
2474         for (i = 0; i < soc_data->num_regulator; i++)
2475                 padctl->regulator[i].supply =
2476                         soc_data->regulator_name[i];
2477
2478         err = devm_regulator_bulk_get(&pdev->dev, soc_data->num_regulator,
2479                 padctl->regulator);
2480         if (err) {
2481                 dev_err(&pdev->dev, "fail to get regulator %d\n", err);
2482                 goto done;
2483         }
2484
2485 done:
2486         return err;
2487 }
2488
2489 static char * const tegra210_padctl_regulator_name[] = {
2490         "avdd_pll_uerefe", "hvdd_pex_pll_e",
2491         "dvdd_pex_pll", "hvddio_pex", "dvddio_pex",
2492         "hvdd_sata", "dvdd_sata_pll", "hvddio_sata", "dvddio_sata"
2493 };
2494
2495 static const struct tegra_padctl_soc_data tegra210_padctl_data = {
2496         .regulator_name = tegra210_padctl_regulator_name,
2497         .num_regulator =
2498                 ARRAY_SIZE(tegra210_padctl_regulator_name),
2499 };
2500
2501 static struct of_device_id tegra_padctl_of_match[] = {
2502         {
2503                 .compatible = "nvidia,tegra210-padctl",
2504                 .data = &tegra210_padctl_data,
2505         },
2506         { },
2507 };
2508
2509 static int
2510 tegra_padctl_probe(struct platform_device *pdev)
2511 {
2512         u32 lane_owner;
2513         u32 lane_map;
2514         bool enable_sata_port;
2515         int err = 0;
2516         const struct of_device_id *match;
2517         struct clk *plle_clk;
2518         struct clk *plle_hw_clk;
2519
2520         if (of_property_read_u32(pdev->dev.of_node, "nvidia,lane_owner",
2521                 (u32 *) &lane_owner))
2522                 lane_owner = 0xffff;
2523         if (of_property_read_u32(pdev->dev.of_node, "nvidia,lane-map",
2524                 (u32 *) &lane_map))
2525                 lane_map = 0;
2526         enable_sata_port = of_property_read_bool(pdev->dev.of_node,
2527                                 "nvidia,enable-sata-port");
2528
2529         if ((lane_owner == 0xffff) && (lane_map == 0) && !enable_sata_port)
2530                 return -ENODEV;
2531
2532         padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl),
2533                         GFP_KERNEL);
2534         if (IS_ERR(padctl)) {
2535                 dev_err(&pdev->dev, "fail to alloc padctl struct\n");
2536                 err = -ENOMEM;
2537                 goto done;
2538         }
2539         padctl->pdev = pdev;
2540         platform_set_drvdata(pdev, padctl);
2541
2542         padctl->lane_owner = lane_owner;
2543         padctl->lane_map = lane_map;
2544         padctl->enable_sata_port = enable_sata_port;
2545
2546         match = of_match_device(tegra_padctl_of_match, &pdev->dev);
2547         if (!match) {
2548                 dev_err(&pdev->dev, "no device match\n");
2549                 return -ENODEV;
2550         }
2551         padctl->soc_data = match->data;
2552
2553         /* get regulators */
2554         err = tegra_padctl_get_regulator(pdev);
2555         if (err)
2556                 goto done;
2557
2558         /* get pll_e */
2559         plle_clk = devm_clk_get(&pdev->dev, "pll_e");
2560         if (IS_ERR(plle_clk)) {
2561                 dev_err(&pdev->dev, "pll_e not found\n");
2562                 err = -ENODEV;
2563                 goto done;
2564         }
2565         padctl->plle_clk = plle_clk;
2566
2567         /* get pll_e_hw */
2568         plle_hw_clk = clk_get_sys(NULL, "pll_e_hw");
2569         if (IS_ERR(plle_hw_clk)) {
2570                 dev_err(&pdev->dev, "pll_e_hw not found\n");
2571                 err = -ENODEV;
2572                 goto done;
2573         }
2574         padctl->plle_hw_clk = plle_hw_clk;
2575
2576         err = tegra_padctl_enable_regulator(pdev);
2577         if (err)
2578                 goto done;
2579
2580         err = tegra_padctl_uphy_init(pdev);
2581
2582 done:
2583         return err;
2584 }
2585
2586 static int
2587 tegra_padctl_remove(struct platform_device *pdev)
2588 {
2589         tegra_padctl_uphy_deinit(pdev);
2590         tegra_padctl_disable_regulator(pdev);
2591         return 0;
2592 }
2593
2594 static int
2595 tegra_padctl_suspend_noirq(struct device *dev)
2596 {
2597         struct platform_device *pdev = to_platform_device(dev);
2598
2599         tegra_padctl_uphy_deinit(pdev);
2600
2601         return 0;
2602 }
2603
2604 static int
2605 tegra_padctl_resume_noirq(struct device *dev)
2606 {
2607         struct platform_device *pdev = to_platform_device(dev);
2608
2609         return tegra_padctl_uphy_init(pdev);
2610 }
2611
2612 static const struct dev_pm_ops tegra_padctl_pm_ops = {
2613         .suspend_noirq = tegra_padctl_suspend_noirq,
2614         .resume_noirq = tegra_padctl_resume_noirq,
2615 };
2616
2617 static struct platform_driver tegra_padctl_driver = {
2618         .probe  = tegra_padctl_probe,
2619         .remove = tegra_padctl_remove,
2620         .driver = {
2621                 .name = "tegra-padctl",
2622                 .of_match_table = tegra_padctl_of_match,
2623                 .pm = &tegra_padctl_pm_ops,
2624         },
2625 };
2626
2627 static int __init tegra_xusb_padctl_init(void)
2628 {
2629         platform_driver_register(&tegra_padctl_driver);
2630
2631         return 0;
2632 }
2633 fs_initcall(tegra_xusb_padctl_init);
2634
2635 #define reg_dump(_name, _reg) \
2636         pr_debug("%s @%x = 0x%x\n", #_name, (_reg), \
2637                  ioread32(IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE) + (_reg)))
2638 static bool clamp_en_early_enabled[4] = {false};
2639 void t210_clamp_en_early(unsigned port, bool on)
2640 {
2641         u32 mask;
2642
2643         if ((on && clamp_en_early_enabled[port]) ||
2644                         (!on && !clamp_en_early_enabled[port]))
2645                 return;
2646
2647         clamp_en_early_enabled[port] = on;
2648         pr_debug("%s %s SS port %d\n", __func__,
2649                         on ? "enable" : "disable", port);
2650
2651         mask = SSPX_ELPG_CLAMP_EN_EARLY(port);
2652         if (on) {
2653                 tegra_usb_pad_reg_update(XUSB_PADCTL_ELPG_PROGRAM_1, 0, mask);
2654                 udelay(60);
2655         } else
2656                 tegra_usb_pad_reg_update(XUSB_PADCTL_ELPG_PROGRAM_1, mask, 0);
2657
2658         reg_dump("elpg_program1", XUSB_PADCTL_ELPG_PROGRAM_1);
2659 }
2660 EXPORT_SYMBOL_GPL(t210_clamp_en_early);
2661
2662 static bool receiver_detector_disabled[4] = {false};
2663 void t210_receiver_detector(unsigned port, bool on)
2664 {
2665         u8 lane;
2666         enum padctl_lane lane_enum;
2667         u32 misc_pad_ctl1, misc_pad_ctl2;
2668         u32 mask;
2669
2670         if (!padctl)
2671                 return;
2672
2673         lane = (padctl->lane_owner >> (port * 4)) & 0xf;
2674         lane_enum = usb3_laneowner_to_lane_enum(lane);
2675         if ((lane == USB3_LANE_NOT_ENABLED) || (lane_enum < 0))
2676                 return;
2677
2678         if ((on && !receiver_detector_disabled[port]) ||
2679                         (!on && receiver_detector_disabled[port]))
2680                 return;
2681
2682         receiver_detector_disabled[port] = !on;
2683
2684         if (lane_enum == SATA_S0) {
2685                 misc_pad_ctl1 = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1;
2686                 misc_pad_ctl2 = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2;
2687         } else {
2688                 misc_pad_ctl1 = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane_enum);
2689                 misc_pad_ctl2 = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(lane_enum);
2690         }
2691
2692         pr_debug("%s %s SS port %d lane %d CTL1 addr 0x%x CTL2 addr 0x%x\n",
2693                 __func__, on ? "enable" : "disable", port, lane_enum,
2694                 misc_pad_ctl1, misc_pad_ctl2);
2695
2696         if (!on) {
2697                 mask = XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ |
2698                         XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
2699                 tegra_usb_pad_reg_update(misc_pad_ctl2, mask, 0);
2700
2701                 mask = XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD |
2702                         XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
2703                 tegra_usb_pad_reg_update(misc_pad_ctl2, 0, mask);
2704
2705                 mask = (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_TX_RDET_CLK_EN |
2706                         XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_TX_RDET_BYP |
2707                         XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_TX_RDET_EN |
2708                         XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_TX_TERM_EN);
2709                 tegra_usb_pad_reg_update(misc_pad_ctl1, mask, 0);
2710
2711                 mask = XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_TX_MODE_OVRD;
2712                 tegra_usb_pad_reg_update(misc_pad_ctl1, 0, mask);
2713         } else {
2714                 mask = XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_TX_MODE_OVRD;
2715                 tegra_usb_pad_reg_update(misc_pad_ctl1, mask, 0);
2716
2717                 mask = XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD |
2718                         XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
2719                 tegra_usb_pad_reg_update(misc_pad_ctl2, mask, 0);
2720         }
2721
2722         reg_dump("ctrl1", misc_pad_ctl1);
2723         reg_dump("ctrl2", misc_pad_ctl2);
2724         reg_dump("elpg_program1", XUSB_PADCTL_ELPG_PROGRAM_1);
2725 }
2726 EXPORT_SYMBOL_GPL(t210_receiver_detector);
2727
2728 #else
2729
2730 /* save restore below pad control register when cross LP0 */
2731 struct xusb_padctl_restore_context {
2732         u32 padctl_usb3_pad_mux;
2733 };
2734 static struct xusb_padctl_restore_context context;
2735
2736 static int tegra_xusb_padctl_suspend(void)
2737 {
2738         context.padctl_usb3_pad_mux = tegra_usb_pad_reg_read(
2739                 XUSB_PADCTL_USB3_PAD_MUX_0);
2740         return 0;
2741 }
2742
2743 static void tegra_xusb_padctl_resume(void)
2744 {
2745         tegra_usb_pad_reg_write(XUSB_PADCTL_USB3_PAD_MUX_0,
2746                 context.padctl_usb3_pad_mux);
2747 }
2748
2749 static struct syscore_ops tegra_padctl_syscore_ops = {
2750         .suspend = tegra_xusb_padctl_suspend,
2751         .resume = tegra_xusb_padctl_resume,
2752         .save = tegra_xusb_padctl_suspend,
2753         .restore = tegra_xusb_padctl_resume,
2754 };
2755
2756 static int __init tegra_xusb_padctl_init(void)
2757 {
2758         register_syscore_ops(&tegra_padctl_syscore_ops);
2759         return 0;
2760 }
2761 late_initcall(tegra_xusb_padctl_init);
2762
2763 #endif