2 * include/linux/tegra_profiler.h
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef __TEGRA_PROFILER_H
18 #define __TEGRA_PROFILER_H
20 #include <linux/ioctl.h>
22 #define QUADD_SAMPLES_VERSION 33
23 #define QUADD_IO_VERSION 18
25 #define QUADD_IO_VERSION_DYNAMIC_RB 5
26 #define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
27 #define QUADD_IO_VERSION_MOD_STATE_STATUS_FIELD 7
28 #define QUADD_IO_VERSION_BT_KERNEL_CTX 8
29 #define QUADD_IO_VERSION_GET_MMAP 9
30 #define QUADD_IO_VERSION_BT_UNWIND_TABLES 10
31 #define QUADD_IO_VERSION_UNWIND_MIXED 11
32 #define QUADD_IO_VERSION_EXTABLES_MMAP 12
33 #define QUADD_IO_VERSION_ARCH_TIMER_OPT 13
34 #define QUADD_IO_VERSION_DATA_MMAP 14
35 #define QUADD_IO_VERSION_BT_LOWER_BOUND 15
36 #define QUADD_IO_VERSION_STACK_OFFSET 16
37 #define QUADD_IO_VERSION_SECTIONS_INFO 17
38 #define QUADD_IO_VERSION_UNW_METHODS_OPT 18
40 #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
41 #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
42 #define QUADD_SAMPLE_VERSION_THREAD_STATE_FLD 19
43 #define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22
44 #define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23
45 #define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24
46 #define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25
47 #define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE 26
48 #define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER 27
49 #define QUADD_SAMPLE_VERSION_SCHED_SAMPLES 28
50 #define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29
51 #define QUADD_SAMPLE_VERSION_HDR_ARCH_TIMER 30
52 #define QUADD_SAMPLE_VERSION_STACK_OFFSET 31
53 #define QUADD_SAMPLE_VERSION_SCHED_TASK_STATE 32
54 #define QUADD_SAMPLE_VERSION_URCS 33
56 #define QUADD_MMAP_HEADER_VERSION 1
58 #define QUADD_MAX_COUNTERS 32
59 #define QUADD_MAX_PROCESS 64
61 #define QUADD_DEVICE_NAME "quadd"
62 #define QUADD_AUTH_DEVICE_NAME "quadd_auth"
64 #define QUADD_MOD_DEVICE_NAME "quadd_mod"
65 #define QUADD_MOD_AUTH_DEVICE_NAME "quadd_mod_auth"
67 #define QUADD_IOCTL 100
70 * Setup params (profiling frequency, etc.)
72 #define IOCTL_SETUP _IOW(QUADD_IOCTL, 0, struct quadd_parameters)
77 #define IOCTL_START _IO(QUADD_IOCTL, 1)
82 #define IOCTL_STOP _IO(QUADD_IOCTL, 2)
85 * Getting capabilities
87 #define IOCTL_GET_CAP _IOR(QUADD_IOCTL, 3, struct quadd_comm_cap)
90 * Getting state of module
92 #define IOCTL_GET_STATE _IOR(QUADD_IOCTL, 4, struct quadd_module_state)
95 * Getting version of module
97 #define IOCTL_GET_VERSION _IOR(QUADD_IOCTL, 5, struct quadd_module_version)
100 * Send exception-handling tables info
101 * This ioctl is obsolete
103 /*#define IOCTL_SET_EXTAB _IOW(QUADD_IOCTL, 6, struct quadd_extables)*/
106 * Send ring buffer mmap info
108 #define IOCTL_SET_MMAP_RB _IOW(QUADD_IOCTL, 7, struct quadd_mmap_rb_info)
113 #define IOCTL_SET_SECTIONS_INFO _IOW(QUADD_IOCTL, 8, struct quadd_sections)
115 #define QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP (1 << 29) /* LP CPU */
116 #define QUADD_CPUMODE_THUMB (1 << 30) /* thumb mode */
118 enum quadd_events_id {
119 QUADD_EVENT_TYPE_CPU_CYCLES = 0,
121 QUADD_EVENT_TYPE_INSTRUCTIONS,
122 QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS,
123 QUADD_EVENT_TYPE_BRANCH_MISSES,
124 QUADD_EVENT_TYPE_BUS_CYCLES,
126 QUADD_EVENT_TYPE_L1_DCACHE_READ_MISSES,
127 QUADD_EVENT_TYPE_L1_DCACHE_WRITE_MISSES,
128 QUADD_EVENT_TYPE_L1_ICACHE_MISSES,
130 QUADD_EVENT_TYPE_L2_DCACHE_READ_MISSES,
131 QUADD_EVENT_TYPE_L2_DCACHE_WRITE_MISSES,
132 QUADD_EVENT_TYPE_L2_ICACHE_MISSES,
134 QUADD_EVENT_TYPE_MAX,
145 enum quadd_record_type {
146 QUADD_RECORD_TYPE_SAMPLE = 1,
147 QUADD_RECORD_TYPE_MMAP,
148 QUADD_RECORD_TYPE_MA,
149 QUADD_RECORD_TYPE_COMM,
150 QUADD_RECORD_TYPE_DEBUG,
151 QUADD_RECORD_TYPE_HEADER,
152 QUADD_RECORD_TYPE_POWER_RATE,
153 QUADD_RECORD_TYPE_ADDITIONAL_SAMPLE,
154 QUADD_RECORD_TYPE_SCHED,
157 enum quadd_event_source {
158 QUADD_EVENT_SOURCE_PMU = 1,
159 QUADD_EVENT_SOURCE_PL310,
162 enum quadd_cpu_mode {
163 QUADD_CPU_MODE_KERNEL = 1,
168 #pragma pack(push, 1)
170 #define QUADD_SAMPLE_RES_URCS_ENABLED (1 << 0)
172 #define QUADD_SAMPLE_URC_MASK 0xff
174 #define QUADD_SAMPLE_URC_SHIFT_FP 0
175 #define QUADD_SAMPLE_URC_SHIFT_UT (1 * 8)
176 #define QUADD_SAMPLE_URC_SHIFT_DWARF (2 * 8)
179 QUADD_URC_SUCCESS = 0,
181 QUADD_URC_IDX_NOT_FOUND,
182 QUADD_URC_TBL_NOT_EXIST,
184 QUADD_URC_TBL_IS_CORRUPT,
185 QUADD_URC_CANTUNWIND,
186 QUADD_URC_UNHANDLED_INSTRUCTION,
187 QUADD_URC_REFUSE_TO_UNWIND,
188 QUADD_URC_SP_INCORRECT,
189 QUADD_URC_SPARE_ENCODING,
190 QUADD_URC_UNSUPPORTED_PR,
191 QUADD_URC_PC_INCORRECT,
192 QUADD_URC_LEVEL_TOO_DEEP,
193 QUADD_URC_FP_INCORRECT,
198 #define QUADD_SED_IP64 (1 << 0)
200 #define QUADD_SED_STACK_OFFSET_SHIFT 1
201 #define QUADD_SED_STACK_OFFSET_MASK (0xffff << QUADD_SED_STACK_OFFSET_SHIFT)
204 QUADD_UNW_TYPE_FP = 0,
206 QUADD_UNW_TYPE_LR_FP,
207 QUADD_UNW_TYPE_LR_UT,
209 QUADD_UNW_TYPE_DWARF_EH,
210 QUADD_UNW_TYPE_DWARF_DF,
213 struct quadd_sample_data {
230 #define QUADD_MMAP_ED_IS_FILE_EXISTS (1 << 0)
232 struct quadd_mmap_data {
242 struct quadd_ma_data {
250 struct quadd_power_rate_data {
259 struct quadd_additional_sample {
267 QUADD_SCHED_IDX_TASK_STATE = 0,
268 QUADD_SCHED_IDX_RESERVED,
271 struct quadd_sched_data {
284 QM_DEBUG_SAMPLE_TYPE_SCHED_IN = 1,
285 QM_DEBUG_SAMPLE_TYPE_SCHED_OUT,
287 QM_DEBUG_SAMPLE_TYPE_TIMER_HANDLE,
288 QM_DEBUG_SAMPLE_TYPE_TIMER_START,
289 QM_DEBUG_SAMPLE_TYPE_TIMER_CANCEL,
290 QM_DEBUG_SAMPLE_TYPE_TIMER_FORWARD,
292 QM_DEBUG_SAMPLE_TYPE_READ_COUNTER,
294 QM_DEBUG_SAMPLE_TYPE_SOURCE_START,
295 QM_DEBUG_SAMPLE_TYPE_SOURCE_STOP,
298 struct quadd_debug_data {
314 #define QUADD_HEADER_MAGIC 0x1122
316 #define QUADD_HDR_BT_FP (1 << 0)
317 #define QUADD_HDR_BT_UT (1 << 1)
318 #define QUADD_HDR_BT_UT_CE (1 << 2)
319 #define QUADD_HDR_USE_ARCH_TIMER (1 << 3)
320 #define QUADD_HDR_STACK_OFFSET (1 << 4)
321 #define QUADD_HDR_BT_DWARF (1 << 5)
323 struct quadd_header_data {
333 reserved:26; /* reserved fields for future extensions */
343 struct quadd_record_data {
346 /* sample: it should be the biggest size */
348 struct quadd_sample_data sample;
349 struct quadd_mmap_data mmap;
350 struct quadd_ma_data ma;
351 struct quadd_debug_data debug;
352 struct quadd_header_data hdr;
353 struct quadd_power_rate_data power_rate;
354 struct quadd_sched_data sched;
355 struct quadd_additional_sample additional_sample;
361 #define QUADD_MAX_PACKAGE_NAME 320
364 QUADD_PARAM_IDX_SIZE_OF_RB = 0,
365 QUADD_PARAM_IDX_EXTRA = 1,
366 QUADD_PARAM_IDX_BT_LOWER_BOUND = 2,
369 #define QUADD_PARAM_EXTRA_GET_MMAP (1 << 0)
370 #define QUADD_PARAM_EXTRA_BT_FP (1 << 1)
371 #define QUADD_PARAM_EXTRA_BT_UT (1 << 2)
372 #define QUADD_PARAM_EXTRA_BT_MIXED (1 << 3)
373 #define QUADD_PARAM_EXTRA_USE_ARCH_TIMER (1 << 4)
374 #define QUADD_PARAM_EXTRA_STACK_OFFSET (1 << 5)
375 #define QUADD_PARAM_EXTRA_BT_UT_CE (1 << 6)
376 #define QUADD_PARAM_EXTRA_BT_DWARF (1 << 7)
378 struct quadd_parameters {
388 u32 pids[QUADD_MAX_PROCESS];
391 u8 package_name[QUADD_MAX_PACKAGE_NAME];
393 u32 events[QUADD_MAX_COUNTERS];
396 u32 reserved[16]; /* reserved fields for future extensions */
399 struct quadd_events_cap {
402 branch_instructions:1,
406 l1_dcache_read_misses:1,
407 l1_dcache_write_misses:1,
410 l2_dcache_read_misses:1,
411 l2_dcache_write_misses:1,
416 QUADD_COMM_CAP_IDX_EXTRA = 0,
419 #define QUADD_COMM_CAP_EXTRA_BT_KERNEL_CTX (1 << 0)
420 #define QUADD_COMM_CAP_EXTRA_GET_MMAP (1 << 1)
421 #define QUADD_COMM_CAP_EXTRA_GROUP_SAMPLES (1 << 2)
422 #define QUADD_COMM_CAP_EXTRA_BT_UNWIND_TABLES (1 << 3)
423 #define QUADD_COMM_CAP_EXTRA_SUPPORT_AARCH64 (1 << 4)
424 #define QUADD_COMM_CAP_EXTRA_SPECIAL_ARCH_MMAP (1 << 5)
425 #define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED (1 << 6)
426 #define QUADD_COMM_CAP_EXTRA_UNW_ENTRY_TYPE (1 << 7)
427 #define QUADD_COMM_CAP_EXTRA_ARCH_TIMER (1 << 8)
428 #define QUADD_COMM_CAP_EXTRA_RB_MMAP_OP (1 << 9)
430 struct quadd_comm_cap {
434 l2_multiple_events:1,
438 struct quadd_events_cap events_cap;
440 u32 reserved[16]; /* reserved fields for future extensions */
444 QUADD_MOD_STATE_IDX_RB_MAX_FILL_COUNT = 0,
445 QUADD_MOD_STATE_IDX_STATUS,
448 #define QUADD_MOD_STATE_STATUS_IS_ACTIVE (1 << 0)
449 #define QUADD_MOD_STATE_STATUS_IS_AUTH_OPEN (1 << 1)
451 struct quadd_module_state {
453 u64 nr_skipped_samples;
456 u32 buffer_fill_size;
458 u32 reserved[16]; /* reserved fields for future extensions */
461 struct quadd_module_version {
468 u32 reserved[4]; /* reserved fields for future extensions */
472 QUADD_SEC_TYPE_EXTAB = 0,
473 QUADD_SEC_TYPE_EXIDX,
475 QUADD_SEC_TYPE_EH_FRAME,
476 QUADD_SEC_TYPE_EH_FRAME_HDR,
478 QUADD_SEC_TYPE_DEBUG_FRAME,
479 QUADD_SEC_TYPE_DEBUG_FRAME_HDR,
484 struct quadd_sec_info {
491 struct quadd_sections {
495 struct quadd_sec_info sec[QUADD_SEC_TYPE_MAX];
499 u64 reserved[4]; /* reserved fields for future extensions */
502 struct quadd_mmap_rb_info {
508 u32 reserved[4]; /* reserved fields for future extensions */
511 #define QUADD_MMAP_HEADER_MAGIC 0x33445566
513 struct quadd_mmap_header {
520 u32 reserved[4]; /* reserved fields for future extensions */
524 QUADD_RB_STATE_NONE = 0,
525 QUADD_RB_STATE_ACTIVE,
526 QUADD_RB_STATE_STOPPED,
529 struct quadd_ring_buffer_hdr {
539 u32 reserved[4]; /* reserved fields for future extensions */
547 struct vm_area_struct;
549 #ifdef CONFIG_TEGRA_PROFILER
550 extern void __quadd_task_sched_in(struct task_struct *prev,
551 struct task_struct *task);
552 extern void __quadd_task_sched_out(struct task_struct *prev,
553 struct task_struct *next);
555 extern void __quadd_event_mmap(struct vm_area_struct *vma);
557 static inline void quadd_task_sched_in(struct task_struct *prev,
558 struct task_struct *task)
560 __quadd_task_sched_in(prev, task);
563 static inline void quadd_task_sched_out(struct task_struct *prev,
564 struct task_struct *next)
566 __quadd_task_sched_out(prev, next);
569 static inline void quadd_event_mmap(struct vm_area_struct *vma)
571 __quadd_event_mmap(vma);
574 #else /* CONFIG_TEGRA_PROFILER */
576 static inline void quadd_task_sched_in(struct task_struct *prev,
577 struct task_struct *task)
581 static inline void quadd_task_sched_out(struct task_struct *prev,
582 struct task_struct *next)
586 static inline void quadd_event_mmap(struct vm_area_struct *vma)
590 #endif /* CONFIG_TEGRA_PROFILER */
592 #endif /* __KERNEL__ */
594 #endif /* __TEGRA_PROFILER_H */