drivers/video/tegra/dc/hdmi2.0.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi2.0.c
   3  *
   4  * Copyright (c) 2014-2016, NVIDIA CORPORATION, All rights reserved.
   5  * Author: Animesh Kishore <ankishore@nvidia.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mutex.h>
  23 #include <linux/device.h>
  24 #include <linux/clk/tegra.h>
  25 #include <linux/nvhost.h>
  26 #include <linux/gpio.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/debugfs.h>
  29 #include <linux/unistd.h>
  30 #ifdef CONFIG_SWITCH
  31 #include <linux/switch.h>
  32 #endif
  33 #include <linux/of_address.h>
  34 #include <linux/tegra_pm_domains.h>
  35
  36 #include <mach/dc.h>
  37 #include <mach/fb.h>
  38 #include <mach/powergate.h>
  39
  40 #include "dc_reg.h"
  41 #include "dc_priv.h"
  42 #include "sor.h"
  43 #include "sor_regs.h"
  44 #include "edid.h"
  45 #include "hdmi2.0.h"
  46 #include "hdmihdcp.h"
  47 #include "dpaux.h"
  48 #ifdef CONFIG_ADF_TEGRA
  49 #include "tegra_adf.h"
  50 #endif
  51 #include "hda_dc.h"
  52 #include "hdmivrr.h"
  53
  54 #include <linux/tegra_prod.h>
  55 #include "../../../../arch/arm/mach-tegra/iomap.h"
  56
  57 #define TMDS_NODE       "/host1x/sor1"
  58
  59 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
  60 static struct of_device_id tegra_sor_pd[] = {
  61         { .compatible = "nvidia, tegra210-sor-pd", },
  62         { .compatible = "nvidia, tegra132-sor-pd", },
  63         { .compatible = "nvidia, tegra124-sor-pd", },
  64         {},
  65 };
  66 #endif
  67
  68 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
  69         struct kobj_attribute *attr, const char *buf, size_t count);
  70
  71 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
  72         struct kobj_attribute *attr, char *buf);
  73
  74 static struct kobj_attribute hdmi_ddc_power_config =
  75         __ATTR(config, 0640, hdmi_ddc_power_show, hdmi_ddc_power_toggle);
  76
  77 static struct kobject *hdmi_ddc;
  78
  79 struct tmds_prod_pair {
  80         int clk;
  81         const char *name;
  82 };
  83
  84 static struct tmds_prod_pair tmds_config_modes[] = {
  85         { /* 54 MHz */
  86         .clk = 54000000,
  87         .name = "prod_c_54M"
  88         },
  89         { /* 75 MHz */
  90         .clk = 75000000,
  91         .name = "prod_c_75M"
  92         },
  93         { /* 150 MHz */
  94         .clk = 150000000,
  95         .name = "prod_c_150M"
  96         },
  97         { /* 300 MHz */
  98         .clk = 300000000,
  99         .name = "prod_c_300M"
 100         },
 101         { /* HDMI 2.0 */
 102         .clk = 600000000,
 103         .name = "prod_c_600M"
 104         }
 105 };
 106
 107 static struct tegra_hdmi *dc_hdmi;
 108
 109 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi);
 110 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type);
 111 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk);
 112 static void tegra_hdmi_scdc_worker(struct work_struct *work);
 113 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi);
 114
 115 static inline bool tegra_hdmi_is_connected(struct tegra_hdmi *hdmi)
 116 {
 117         return (hdmi->mon_spec.misc & FB_MISC_HDMI) ||
 118                 (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM);
 119 }
 120
 121 static inline void tegra_hdmi_irq_enable(struct tegra_hdmi *hdmi)
 122 {
 123         if (tegra_platform_is_fpga())
 124                 return;
 125
 126         enable_irq(hdmi->irq);
 127 }
 128
 129 static inline void tegra_hdmi_irq_disable(struct tegra_hdmi *hdmi)
 130 {
 131         if (tegra_platform_is_fpga())
 132                 return;
 133
 134         disable_irq(hdmi->irq);
 135 }
 136
 137 static inline bool tegra_hdmi_hpd_asserted(struct tegra_hdmi *hdmi)
 138 {
 139         return tegra_dc_hpd(hdmi->dc);
 140 }
 141
 142 static inline void tegra_hdmi_reset(struct tegra_hdmi *hdmi)
 143 {
 144         if (tegra_platform_is_linsim())
 145                 return;
 146
 147         tegra_periph_reset_assert(hdmi->sor->sor_clk);
 148         mdelay(20);
 149         tegra_periph_reset_deassert(hdmi->sor->sor_clk);
 150         mdelay(20);
 151 }
 152
 153 static inline void _tegra_hdmi_ddc_enable(struct tegra_hdmi *hdmi)
 154 {
 155         mutex_lock(&hdmi->ddc_refcount_lock);
 156         if (hdmi->ddc_refcount++)
 157                 goto fail;
 158         tegra_hdmi_get(hdmi->dc);
 159         /*
 160          * hdmi uses i2c lane muxed on dpaux1 pad.
 161          * Enable dpaux1 pads and configure the mux.
 162          */
 163         tegra_dpaux_config_pad_mode(hdmi->dc, TEGRA_DPAUX_INSTANCE_1,
 164                                         TEGRA_DPAUX_PAD_MODE_I2C);
 165
 166 fail:
 167         mutex_unlock(&hdmi->ddc_refcount_lock);
 168 }
 169
 170 static inline void _tegra_hdmi_ddc_disable(struct tegra_hdmi *hdmi)
 171 {
 172         mutex_lock(&hdmi->ddc_refcount_lock);
 173
 174         if (WARN_ONCE(hdmi->ddc_refcount <= 0, "ddc refcount imbalance"))
 175                 goto fail;
 176         if (--hdmi->ddc_refcount != 0)
 177                 goto fail;
 178
 179         /*
 180          * hdmi uses i2c lane muxed on dpaux1 pad.
 181          * Disable dpaux1 pads.
 182          */
 183         tegra_dpaux_pad_power(hdmi->dc, TEGRA_DPAUX_INSTANCE_1, false);
 184         tegra_hdmi_put(hdmi->dc);
 185
 186 fail:
 187         mutex_unlock(&hdmi->ddc_refcount_lock);
 188 }
 189
 190 static int tegra_hdmi_ddc_i2c_xfer(struct tegra_dc *dc,
 191                                         struct i2c_msg *msgs, int num)
 192 {
 193         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 194         int ret;
 195
 196         _tegra_hdmi_ddc_enable(hdmi);
 197         ret = i2c_transfer(hdmi->ddc_i2c_client->adapter, msgs, num);
 198         _tegra_hdmi_ddc_disable(hdmi);
 199         return ret;
 200 }
 201
 202 static int tegra_hdmi_ddc_init(struct tegra_hdmi *hdmi, int edid_src)
 203 {
 204         struct tegra_dc *dc = hdmi->dc;
 205         struct i2c_adapter *i2c_adap;
 206         int err = 0;
 207         struct i2c_board_info i2c_dev_info = {
 208                 .type = "tegra_hdmi2.0",
 209                 .addr = 0x50,
 210         };
 211         if (edid_src == 0)
 212                 hdmi->edid = tegra_edid_create(dc, tegra_hdmi_ddc_i2c_xfer);
 213         else if (edid_src == 1)
 214                 hdmi->edid = tegra_edid_create(dc, tegra_dc_edid_blob);
 215         if (IS_ERR_OR_NULL(hdmi->edid)) {
 216                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
 217                 return PTR_ERR(hdmi->edid);
 218         }
 219         tegra_dc_set_edid(dc, hdmi->edid);
 220
 221         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
 222         if (!i2c_adap) {
 223                 dev_err(&dc->ndev->dev,
 224                         "hdmi: can't get adpater for ddc bus %d\n",
 225                         dc->out->ddc_bus);
 226                 err = -EBUSY;
 227                 goto fail_edid_free;
 228         }
 229         hdmi->ddc_i2c_original_rate = i2c_get_adapter_bus_clk_rate(i2c_adap);
 230
 231         hdmi->ddc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
 232         i2c_put_adapter(i2c_adap);
 233         if (!hdmi->ddc_i2c_client) {
 234                 dev_err(&dc->ndev->dev, "hdmi: can't create new i2c device\n");
 235                 err = -EBUSY;
 236                 goto fail_edid_free;
 237         }
 238
 239         return 0;
 240 fail_edid_free:
 241         tegra_edid_destroy(hdmi->edid);
 242         return err;
 243 }
 244
 245 static int tegra_hdmi_scdc_i2c_xfer(struct tegra_dc *dc,
 246                                         struct i2c_msg *msgs, int num)
 247 {
 248         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 249
 250         return i2c_transfer(hdmi->scdc_i2c_client->adapter, msgs, num);
 251 }
 252
 253 static int tegra_hdmi_scdc_init(struct tegra_hdmi *hdmi)
 254 {
 255         struct tegra_dc *dc = hdmi->dc;
 256         struct i2c_adapter *i2c_adap;
 257         int err = 0;
 258         struct i2c_board_info i2c_dev_info = {
 259                 .type = "tegra_hdmi_scdc",
 260                 .addr = 0x54,
 261         };
 262
 263         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
 264         if (!i2c_adap) {
 265                 dev_err(&dc->ndev->dev,
 266                         "hdmi: can't get adpater for scdc bus %d\n",
 267                         dc->out->ddc_bus);
 268                 err = -EBUSY;
 269                 goto fail;
 270         }
 271
 272         hdmi->scdc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
 273         i2c_put_adapter(i2c_adap);
 274         if (!hdmi->scdc_i2c_client) {
 275                 dev_err(&dc->ndev->dev,
 276                         "hdmi: can't create scdc i2c device\n");
 277                 err = -EBUSY;
 278                 goto fail;
 279         }
 280
 281         INIT_DELAYED_WORK(&hdmi->scdc_work, tegra_hdmi_scdc_worker);
 282
 283         return 0;
 284 fail:
 285         return err;
 286 }
 287
 288 static bool tegra_hdmi_check_dc_constraint(const struct fb_videomode *mode)
 289 {
 290         return (mode->hsync_len >= 1) && (mode->vsync_len >= 1) &&
 291                 (mode->lower_margin + mode->vsync_len +
 292                 mode->upper_margin > 1) &&
 293                 (mode->xres >= 16) && (mode->yres >= 16);
 294 }
 295
 296 /*  does not return precise tmds character rate */
 297 static u32 tegra_hdmi_mode_min_tmds_rate(const struct fb_videomode *mode)
 298 {
 299         u32 tmds_csc_8bpc_khz = PICOS2KHZ(mode->pixclock);
 300
 301         if (mode->vmode & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
 302                 tmds_csc_8bpc_khz /= 2;
 303
 304         return tmds_csc_8bpc_khz;
 305 }
 306
 307 __maybe_unused
 308 static bool tegra_hdmi_fb_mode_filter(const struct tegra_dc *dc,
 309                                         struct fb_videomode *mode)
 310 {
 311         struct tegra_hdmi *hdmi = dc->out_data;
 312
 313         if (!mode->pixclock)
 314                 return false;
 315
 316         if (mode->xres > 4096)
 317                 return false;
 318
 319         /* some non-compliant edids list 420vdb modes in vdb */
 320         if ((mode->vmode & FB_VMODE_Y420) &&
 321                 !(tegra_edid_is_hfvsdb_present(hdmi->edid) &&
 322                 tegra_edid_is_scdc_present(hdmi->edid)) &&
 323                 tegra_edid_is_420db_present(hdmi->edid)) {
 324                 mode->vmode &= ~FB_VMODE_Y420;
 325                 mode->vmode |= FB_VMODE_Y420_ONLY;
 326         }
 327
 328         if (mode->vmode & FB_VMODE_YUV_MASK &&
 329                 tegra_edid_get_quirks(hdmi->edid) & TEGRA_EDID_QUIRK_NO_YUV)
 330                 return false;
 331
 332         /*
 333          * There are currently many TVs in the market that actually do NOT support
 334          * 4k@60fps 4:4:4 (594 MHz), (especially on the HDCP 2.2 ports), but
 335          * advertise it in the DTD block in their EDIDs. The workaround for this port
 336          * is to disable the 594 MHz mode if no HF-VSDB is present or if no SCDC
 337          * support is indicated
 338          */
 339         if (tegra_hdmi_mode_min_tmds_rate(mode) / 1000 >= 340 &&
 340                 (!tegra_edid_is_hfvsdb_present(hdmi->edid) ||
 341                 !tegra_edid_is_scdc_present(hdmi->edid)))
 342                 return false;
 343
 344         /*
 345          * Check if mode's pixel clock requirement can be satisfied. Note that
 346          * the pixclock value is in pico seconds.
 347          */
 348         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
 349                 mode->pixclock < tegra_dc_get_out_max_pixclock(dc))
 350                 return false;
 351
 352         /*
 353          * Work around for modes that fail the constraint:
 354          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
 355          */
 356         if (mode->lower_margin == 1) {
 357                 mode->lower_margin++;
 358                 mode->upper_margin--;
 359                 mode->vmode |= FB_VMODE_ADJUSTED;
 360         }
 361
 362         if (!tegra_hdmi_check_dc_constraint(mode))
 363                 return false;
 364
 365         return true;
 366 }
 367
 368 static void tegra_hdmi_ddc_power_toggle(int value)
 369 {
 370         int partition_id;
 371         if (dc_hdmi == NULL)
 372                 return;
 373
 374 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
 375         partition_id = tegra_pd_get_powergate_id(tegra_sor_pd);
 376         if (partition_id < 0)
 377                 return;
 378 #else
 379         partition_id = TEGRA_POWERGATE_SOR;
 380 #endif
 381
 382         if (value == 0) {
 383                 _tegra_hdmi_ddc_disable(dc_hdmi);
 384                 tegra_powergate_partition(partition_id);
 385         } else if (value == 1) {
 386                 tegra_unpowergate_partition(partition_id);
 387                 _tegra_hdmi_ddc_enable(dc_hdmi);
 388         }
 389
 390         return;
 391 }
 392
 393 static int tegra_hdmi_get_mon_spec(struct tegra_hdmi *hdmi)
 394 {
 395 #define MAX_RETRY 100
 396 #define MIN_RETRY_DELAY_US 200
 397 #define MAX_RETRY_DELAY_US (MIN_RETRY_DELAY_US + 200)
 398
 399         size_t attempt_cnt = 0;
 400         int err = 0;
 401         struct i2c_adapter *i2c_adap = i2c_get_adapter(hdmi->dc->out->ddc_bus);
 402
 403         if (IS_ERR_OR_NULL(hdmi->edid)) {
 404                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid not initialized\n");
 405                 return PTR_ERR(hdmi->edid);
 406         }
 407
 408         tegra_edid_i2c_adap_change_rate(i2c_adap, hdmi->ddc_i2c_original_rate);
 409
 410         hdmi->mon_spec_valid = false;
 411         if (hdmi->mon_spec_valid)
 412                 fb_destroy_modedb(hdmi->mon_spec.modedb);
 413         memset(&hdmi->mon_spec, 0, sizeof(hdmi->mon_spec));
 414
 415         do {
 416                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
 417                 if (err < 0)
 418                         usleep_range(MIN_RETRY_DELAY_US, MAX_RETRY_DELAY_US);
 419                 else
 420                         break;
 421         } while (++attempt_cnt < MAX_RETRY);
 422
 423         if (err < 0) {
 424                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid read failed\n");
 425                 /* Try to load and parse the fallback edid */
 426                 hdmi->edid->errors = EDID_ERRORS_READ_FAILED;
 427                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
 428                 if (err < 0) {
 429                         dev_err(&hdmi->dc->ndev->dev,
 430                                 "hdmi: parsing fallback edid failed\n");
 431                         return err;
 432                 } else {
 433                         dev_err(&hdmi->dc->ndev->dev,
 434                                 "hdmi: using fallback edid\n");
 435                 }
 436         }
 437
 438         hdmi->mon_spec_valid = true;
 439         return 0;
 440
 441 #undef MAX_RETRY_DELAY_US
 442 #undef MIN_RETRY_DELAY_US
 443 #undef MAX_RETRY
 444 }
 445
 446 static inline int tegra_hdmi_edid_read(struct tegra_hdmi *hdmi)
 447 {
 448         int err;
 449
 450         err = tegra_hdmi_get_mon_spec(hdmi);
 451
 452         return err;
 453 }
 454
 455 static int tegra_hdmi_get_eld(struct tegra_hdmi *hdmi)
 456 {
 457         int err;
 458
 459         hdmi->eld_valid = false;
 460         memset(&hdmi->eld, 0, sizeof(hdmi->eld));
 461
 462         err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
 463         if (err < 0) {
 464                 dev_err(&hdmi->dc->ndev->dev, "hdmi: eld not available\n");
 465                 return err;
 466         }
 467
 468         hdmi->eld_valid = true;
 469         return 0;
 470 }
 471
 472 static inline int tegra_hdmi_eld_read(struct tegra_hdmi *hdmi)
 473 {
 474         return tegra_hdmi_get_eld(hdmi);
 475 }
 476
 477 static void tegra_hdmi_edid_config(struct tegra_hdmi *hdmi)
 478 {
 479 #define CM_TO_MM(x) (x * 10)
 480
 481         struct tegra_dc *dc = hdmi->dc;
 482
 483         if (!hdmi->mon_spec_valid)
 484                 return;
 485
 486         dc->out->h_size = CM_TO_MM(hdmi->mon_spec.max_x);
 487         dc->out->v_size = CM_TO_MM(hdmi->mon_spec.max_y);
 488
 489         hdmi->dvi = !tegra_hdmi_is_connected(hdmi);
 490 #undef CM_TO_MM
 491 }
 492
 493 static void tegra_hdmi_hotplug_notify(struct tegra_hdmi *hdmi,
 494                                         bool is_asserted)
 495 {
 496         struct tegra_dc *dc = hdmi->dc;
 497         struct fb_monspecs *mon_spec;
 498
 499         if (is_asserted)
 500                 mon_spec = &hdmi->mon_spec;
 501         else
 502                 mon_spec = NULL;
 503
 504 #ifdef CONFIG_ADF_TEGRA
 505         if (dc->adf)
 506                 tegra_adf_process_hotplug_connected(hdmi->dc->adf, mon_spec);
 507 #else
 508         if (dc->fb) {
 509                 tegra_fb_update_monspecs(hdmi->dc->fb, mon_spec,
 510                                         tegra_hdmi_fb_mode_filter);
 511                 tegra_fb_update_fix(hdmi->dc->fb, mon_spec);
 512         }
 513 #endif
 514
 515         dc->connected = is_asserted;
 516         tegra_dc_ext_process_hotplug(dc->ndev->id, is_asserted);
 517
 518 #ifdef CONFIG_SWITCH
 519         switch_set_state(&hdmi->hpd_switch, is_asserted ? 1 : 0);
 520 #endif
 521 }
 522
 523 static int tegra_hdmi_edid_eld_setup(struct tegra_hdmi *hdmi)
 524 {
 525         int err;
 526
 527         tegra_dc_unpowergate_locked(hdmi->dc);
 528
 529         err = tegra_hdmi_edid_read(hdmi);
 530         if (err < 0)
 531                 goto fail;
 532
 533         err = tegra_hdmi_eld_read(hdmi);
 534         if (err < 0)
 535                 goto fail;
 536
 537         err = tegra_hdmivrr_setup(hdmi);
 538         if (err < 0)
 539                 dev_info(&hdmi->dc->ndev->dev, "vrr_setup failed\n");
 540
 541         tegra_dc_powergate_locked(hdmi->dc);
 542
 543         tegra_hdmi_edid_config(hdmi);
 544
 545         /*
 546          * eld is configured when audio needs it
 547          * via tegra_hdmi_edid_config()
 548          */
 549
 550         tegra_hdmi_hotplug_notify(hdmi, true);
 551         return 0;
 552 fail:
 553         tegra_dc_powergate_locked(hdmi->dc);
 554         return err;
 555 }
 556
 557 static int tegra_hdmi_controller_disable(struct tegra_hdmi *hdmi)
 558 {
 559         struct tegra_dc_sor_data *sor = hdmi->sor;
 560         struct tegra_dc *dc = hdmi->dc;
 561
 562         tegra_dc_get(dc);
 563
 564         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
 565         tegra_dc_sor_detach(sor);
 566         tegra_sor_power_lanes(sor, 4, false);
 567         tegra_sor_hdmi_pad_power_down(sor);
 568         tegra_hdmi_reset(hdmi);
 569         tegra_hdmi_put(dc);
 570
 571         tegra_dc_put(dc);
 572
 573         return 0;
 574 }
 575
 576 static int tegra_hdmi_disable(struct tegra_hdmi *hdmi)
 577 {
 578         struct tegra_dc *dc = hdmi->dc;
 579
 580         if (!hdmi->enabled) {
 581                 dc->connected = false;
 582                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
 583 #ifdef CONFIG_SWITCH
 584                 switch_set_state(&hdmi->hpd_switch, 0);
 585 #endif
 586                 return 0;
 587         }
 588
 589         hdmi->enabled = false;
 590         hdmi->eld_valid = false;
 591         hdmi->mon_spec_valid = false;
 592
 593         tegra_dc_disable(hdmi->dc);
 594
 595         tegra_hdmi_hotplug_notify(hdmi, false);
 596
 597         return 0;
 598 }
 599
 600 static int (*tegra_hdmi_state_func[])(struct tegra_hdmi *) = {
 601         tegra_hdmi_disable,
 602         tegra_hdmi_edid_eld_setup,
 603 };
 604
 605 enum tegra_hdmi_plug_states {
 606         TEGRA_HDMI_MONITOR_DISABLE,
 607         TEGRA_HDMI_MONITOR_ENABLE,
 608 };
 609
 610 static int read_edid_into_buffer(struct tegra_hdmi *hdmi,
 611                                  u8 *edid_data, size_t edid_data_len)
 612 {
 613         int err, i;
 614         int extension_blocks;
 615         int max_ext_blocks = (edid_data_len / 128) - 1;
 616
 617         err = tegra_edid_read_block(hdmi->edid, 0, edid_data);
 618         if (err) {
 619                 dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(0) returned err %d\n",
 620                         err);
 621                 return err;
 622         }
 623         extension_blocks = edid_data[0x7e];
 624         dev_info(&hdmi->dc->ndev->dev, "%s: extension_blocks = %d, max_ext_blocks = %d\n",
 625                 __func__, extension_blocks, max_ext_blocks);
 626         if (extension_blocks > max_ext_blocks)
 627                 extension_blocks = max_ext_blocks;
 628         for (i = 1; i <= extension_blocks; i++) {
 629                 err = tegra_edid_read_block(hdmi->edid, i, edid_data + i * 128);
 630                 if (err) {
 631                         dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(%d) returned err %d\n",
 632                                 i, err);
 633                         return err;
 634                 }
 635         }
 636         return i * 128;
 637 }
 638
 639 static int hdmi_recheck_edid(struct tegra_hdmi *hdmi, int *match)
 640 {
 641         int ret;
 642         u8 tmp[HDMI_EDID_MAX_LENGTH] = {0};
 643         ret = read_edid_into_buffer(hdmi, tmp, sizeof(tmp));
 644         dev_info(&hdmi->dc->ndev->dev, "%s: read_edid_into_buffer() returned %d\n",
 645                 __func__, ret);
 646         if (ret > 0) {
 647                 struct tegra_dc_edid *data = tegra_edid_get_data(hdmi->edid);
 648                 dev_info(&hdmi->dc->ndev->dev, "old edid len = %ld\n",
 649                         (long int)data->len);
 650                 *match = ((ret == data->len) &&
 651                           !memcmp(tmp, data->buf, data->len));
 652                 if (*match == 0) {
 653                         print_hex_dump(KERN_INFO, "tmp :", DUMP_PREFIX_ADDRESS,
 654                                        16, 4, tmp, ret, true);
 655                         print_hex_dump(KERN_INFO, "data:", DUMP_PREFIX_ADDRESS,
 656                                        16, 4, data->buf, data->len, true);
 657                 }
 658                 tegra_edid_put_data(data);
 659                 ret = 0;
 660         }
 661
 662         return ret;
 663 }
 664 static void tegra_hdmi_hpd_worker(struct work_struct *work)
 665 {
 666         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
 667                                 struct tegra_hdmi, hpd_worker);
 668         int err;
 669         bool connected;
 670         enum tegra_hdmi_plug_states orig_state;
 671         int match = 0;
 672
 673         mutex_lock(&hdmi->hpd_lock);
 674
 675         connected = tegra_dc_hpd(hdmi->dc);
 676         orig_state = hdmi->plug_state;
 677
 678         if ((connected && orig_state == TEGRA_HDMI_MONITOR_ENABLE)) {
 679                 if (hdmi_recheck_edid(hdmi, &match)) {
 680                         dev_info(&hdmi->dc->ndev->dev, "hdmi: unable to read EDID\n");
 681                         goto fail;
 682                 } else {
 683                         if (match) {
 684                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: No EDID change after HPD bounce, taking no action.\n");
 685                                 goto fail;
 686                         } else
 687                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: EDID change after HPD bounce, resetting\n");
 688                 }
 689         }
 690
 691         if ((!connected && orig_state == TEGRA_HDMI_MONITOR_DISABLE)) {
 692                 dev_info(&hdmi->dc->ndev->dev, "hdmi: spurious interrupt\n");
 693                 mutex_unlock(&hdmi->hpd_lock);
 694                 return;
 695         }
 696
 697         if (connected)
 698                 hdmi->plug_state = TEGRA_HDMI_MONITOR_ENABLE;
 699         else
 700                 hdmi->plug_state = TEGRA_HDMI_MONITOR_DISABLE;
 701
 702         err = tegra_hdmi_state_func[hdmi->plug_state](hdmi);
 703
 704         if (err < 0) {
 705                         dev_info(&hdmi->dc->ndev->dev,
 706                                 "hdmi state %d failed during %splug\n",
 707                                 hdmi->plug_state, connected ? "" : "un");
 708                         hdmi->plug_state = orig_state;
 709                 } else {
 710                         dev_info(&hdmi->dc->ndev->dev, "hdmi: %splugged\n",
 711                                         connected ? "" : "un");
 712                 }
 713
 714 fail:
 715         mutex_unlock(&hdmi->hpd_lock);
 716         return;
 717 }
 718
 719 static irqreturn_t tegra_hdmi_hpd_irq_handler(int irq, void *ptr)
 720 {
 721         struct tegra_dc *dc = ptr;
 722         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 723
 724         if (atomic_read(&hdmi->suspended))
 725                 return IRQ_HANDLED;
 726
 727         cancel_delayed_work(&hdmi->hpd_worker);
 728         schedule_delayed_work(&hdmi->hpd_worker,
 729                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS));
 730
 731         return IRQ_HANDLED;
 732 }
 733
 734 static int tegra_hdmi_hpd_init(struct tegra_hdmi *hdmi)
 735 {
 736         struct tegra_dc *dc = hdmi->dc;
 737         int hotplug_gpio = dc->out->hotplug_gpio;
 738         int hotplug_irq;
 739         int err;
 740
 741         if (!gpio_is_valid(hotplug_gpio)) {
 742                 dev_err(&dc->ndev->dev, "hdmi: invalid hotplug gpio\n");
 743                 return -EINVAL;
 744         }
 745
 746         hotplug_irq = gpio_to_irq(hotplug_gpio);
 747         if (hotplug_irq < 0) {
 748                 dev_err(&dc->ndev->dev,
 749                         "hdmi: hotplug gpio to irq map failed\n");
 750                 return -EINVAL;
 751         }
 752
 753         err = gpio_request(hotplug_gpio, "hdmi2.0_hpd");
 754         if (err < 0)
 755                 dev_err(&dc->ndev->dev,
 756                         "hdmi: hpd gpio_request failed %d\n", err);
 757         gpio_direction_input(hotplug_gpio);
 758
 759         err = request_threaded_irq(hotplug_irq,
 760                                 NULL, tegra_hdmi_hpd_irq_handler,
 761                                 (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
 762                                 IRQF_ONESHOT),
 763                                 dev_name(&dc->ndev->dev), dc);
 764         if (err) {
 765                 dev_err(&dc->ndev->dev,
 766                         "hdmi: request_threaded_irq failed: %d\n", err);
 767                 goto fail;
 768         }
 769
 770
 771         INIT_DELAYED_WORK(&hdmi->hpd_worker, tegra_hdmi_hpd_worker);
 772
 773         mutex_init(&hdmi->hpd_lock);
 774         hdmi->irq = hotplug_irq;
 775
 776         return 0;
 777 fail:
 778         gpio_free(hotplug_gpio);
 779         return err;
 780 }
 781
 782 static int tegra_hdmi_tmds_init(struct tegra_hdmi *hdmi)
 783 {
 784         struct device_node *np_prod = of_find_node_by_path(TMDS_NODE);
 785
 786         if (!np_prod) {
 787                 dev_warn(&hdmi->dc->ndev->dev,
 788                         "hdmi: find tmds prod node failed\n");
 789                 return -EINVAL;
 790         }
 791
 792         hdmi->prod_list =
 793                 tegra_prod_init((const struct device_node *)np_prod);
 794         if (IS_ERR(hdmi->prod_list)) {
 795                 dev_warn(&hdmi->dc->ndev->dev,
 796                         "hdmi: prod list init failed with error %ld\n",
 797                         PTR_ERR(hdmi->prod_list));
 798                 of_node_put(np_prod);
 799                 return -EINVAL;
 800         }
 801
 802         of_node_put(np_prod);
 803         return 0;
 804 }
 805
 806 static int tegra_hdmi_config_tmds(struct tegra_hdmi *hdmi)
 807 {
 808         size_t tmds_len;
 809         int i;
 810         int err = 0;
 811
 812         /* Select mode with smallest clk freq > pclk */
 813         tmds_len = ARRAY_SIZE(tmds_config_modes);
 814         for (i = 0; i < tmds_len - 1 &&
 815                 tmds_config_modes[i].clk < hdmi->dc->mode.pclk; i++);
 816
 817         if (tegra_platform_is_linsim())
 818                 return 0;
 819
 820         err = tegra_prod_set_by_name(&hdmi->sor->base,
 821                                 tmds_config_modes[i].name, hdmi->prod_list);
 822         if (err) {
 823                 dev_warn(&hdmi->dc->ndev->dev,
 824                         "hdmi: tmds prod set failed\n");
 825                 return -EINVAL;
 826         }
 827
 828         return 0;
 829 }
 830
 831 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 832 {
 833         struct tegra_hdmi *hdmi;
 834         int err;
 835         struct device_node *np = dc->ndev->dev.of_node;
 836 #ifdef CONFIG_OF
 837         struct device_node *np_hdmi = of_find_node_by_path(HDMI_NODE);
 838 #else
 839         struct device_node *np_hdmi = NULL;
 840 #endif
 841         struct device_node *np_panel = NULL;
 842         int edid_src = 0;
 843
 844         hdmi = devm_kzalloc(&dc->ndev->dev, sizeof(*hdmi), GFP_KERNEL);
 845         if (!hdmi) {
 846                 of_node_put(np_hdmi);
 847                 return -ENOMEM;
 848         }
 849
 850         hdmi->sor = tegra_dc_sor_init(dc, NULL);
 851         if (IS_ERR_OR_NULL(hdmi->sor)) {
 852                 err = PTR_ERR(hdmi->sor);
 853                 goto fail;
 854         }
 855
 856         if (np) {
 857                 if (np_hdmi && of_device_is_available(np_hdmi)) {
 858                         np_panel = tegra_get_panel_node_out_type_check(dc,
 859                                 TEGRA_DC_OUT_HDMI);
 860                         if (np_panel && of_device_is_available(np_panel)) {
 861                                 if (of_property_read_bool(np_panel,
 862                                                         "nvidia,edid"))
 863                                         edid_src = 1;
 864                                 of_node_put(np_panel);
 865                         }
 866                 } else {
 867                         err = -EINVAL;
 868                         of_node_put(np_panel);
 869                         goto fail;
 870                 }
 871         }
 872
 873         hdmi->pdata = dc->pdata->default_out->hdmi_out;
 874         hdmi->dc = dc;
 875         dc_hdmi = hdmi;
 876         hdmi->ddc_refcount = 0; /* assumes this is disabled when starting */
 877         mutex_init(&hdmi->ddc_refcount_lock);
 878         hdmi->nvhdcp = NULL;
 879         hdmi->mon_spec_valid = false;
 880         hdmi->eld_valid = false;
 881         hdmi->device_shutdown = false;
 882         if (0) {
 883                 /* TODO: seamless boot mode needs initialize the state */
 884         } else {
 885                 hdmi->enabled = false;
 886                 atomic_set(&hdmi->clock_refcount, 0);
 887         }
 888         atomic_set(&hdmi->suspended, 0);
 889
 890 #ifdef CONFIG_TEGRA_HDMIHDCP
 891         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
 892                         dc->out->ddc_bus);
 893         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
 894                 err = PTR_ERR(hdmi->nvhdcp);
 895                 goto fail;
 896         }
 897         tegra_nvhdcp_debugfs_init(hdmi->nvhdcp);
 898 #endif
 899
 900         tegra_hdmi_ddc_init(hdmi, edid_src);
 901
 902         tegra_hdmi_scdc_init(hdmi);
 903
 904         tegra_hdmi_hpd_init(hdmi);
 905
 906         tegra_hdmi_vrr_init(hdmi);
 907
 908         tegra_hdmi_debugfs_init(hdmi);
 909
 910         tegra_hdmi_tmds_init(hdmi);
 911
 912         tegra_dc_set_outdata(dc, hdmi);
 913
 914         /* NOTE: Below code is applicable to L4T or embedded systems and is
 915          * protected accordingly. This section early enables DC with first mode
 916          * from the monitor specs.
 917          * In case there is no hotplug we are falling back
 918          * to default VGA mode.
 919          */
 920         if ((config_enabled(CONFIG_FRAMEBUFFER_CONSOLE) ||
 921                         ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
 922                          (dc->pdata->flags & TEGRA_DC_FLAG_SET_EARLY_MODE))) &&
 923                         dc->out && (dc->out->type == TEGRA_DC_OUT_HDMI)) {
 924                 struct fb_monspecs specs;
 925                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
 926                         if (!tegra_edid_get_monspecs(hdmi->edid, &specs))
 927                                 tegra_dc_set_fb_mode(dc, specs.modedb, false);
 928                         else {
 929                         /* if for some reason there is no edid upon hotplug */
 930                                 tegra_dc_set_fb_mode(dc,
 931                                                 &tegra_dc_vga_mode, false);
 932                         }
 933                 } else
 934                         tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, false);
 935         }
 936
 937 #ifdef CONFIG_SWITCH
 938         hdmi->hpd_switch.name = "hdmi";
 939         err = switch_dev_register(&hdmi->hpd_switch);
 940         if (err)
 941                 dev_err(&dc->ndev->dev,
 942                         "hdmi: failed to register hpd switch %d\n", err);
 943
 944         hdmi->audio_switch.name = "hdmi_audio";
 945         err = switch_dev_register(&hdmi->audio_switch);
 946         if (err)
 947                 dev_err(&dc->ndev->dev,
 948                         "hdmi: failed to register audio switch %d\n", err);
 949 #endif
 950
 951         hdmi_ddc = kobject_create_and_add("hdmi_ddc_power_toggle", kernel_kobj);
 952         if (!hdmi_ddc) {
 953                 pr_warn("kobject create_and_add hdmi_ddc_power_toggle failed\n");
 954                 return 0;
 955         }
 956         err = sysfs_create_file(hdmi_ddc, &hdmi_ddc_power_config.attr);
 957         if (err) {
 958                 pr_warn("sysfs create file hdmi_ddc_power_toggle failed\n");
 959                 return 0;
 960         }
 961
 962         of_node_put(np_hdmi);
 963         return 0;
 964 fail:
 965         devm_kfree(&dc->ndev->dev, hdmi);
 966         of_node_put(np_hdmi);
 967         return err;
 968 }
 969
 970 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
 971 {
 972         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
 973
 974         tegra_dc_sor_destroy(hdmi->sor);
 975         tegra_edid_destroy(hdmi->edid);
 976         tegra_nvhdcp_destroy(hdmi->nvhdcp);
 977         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 978         gpio_free(dc->out->hotplug_gpio);
 979         devm_kfree(&dc->ndev->dev, hdmi);
 980         tegra_prod_release(&hdmi->prod_list);
 981
 982 #ifdef CONFIG_SWITCH
 983         switch_dev_unregister(&hdmi->hpd_switch);
 984         switch_dev_unregister(&hdmi->audio_switch);
 985 #endif
 986 }
 987
 988 static void tegra_hdmi_config(struct tegra_hdmi *hdmi)
 989 {
 990         struct tegra_dc_sor_data *sor = hdmi->sor;
 991         struct tegra_dc *dc = hdmi->dc;
 992 #ifndef CONFIG_TEGRA_NVDISPLAY
 993         u32 h_pulse_start, h_pulse_end;
 994 #endif
 995         u32 hblank, max_ac, rekey;
 996         unsigned long val;
 997         u32 dispclk_div_8_2;
 998
 999         if (tegra_platform_is_linsim())
1000                 return;
1001
1002         tegra_sor_write_field(sor, NV_SOR_INPUT_CONTROL,
1003                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED |
1004                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB,
1005                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL |
1006                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB);
1007
1008         dispclk_div_8_2 = clk_get_rate(hdmi->sor->sor_clk) / 1000000 * 4;
1009         tegra_sor_writel(sor, NV_SOR_REFCLK,
1010                         NV_SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1011                         NV_SOR_REFCLK_DIV_FRAC(dispclk_div_8_2));
1012
1013         rekey = NV_SOR_HDMI_CTRL_REKEY_DEFAULT;
1014         hblank = dc->mode.h_sync_width + dc->mode.h_back_porch +
1015                         dc->mode.h_front_porch;
1016         max_ac = (hblank - rekey - 18) / 32;
1017
1018         val = 0;
1019         val |= hdmi->dvi ? 0x0 : NV_SOR_HDMI_CTRL_ENABLE;
1020         /* The register wants "-2" of the required rekey val */
1021         val |= NV_SOR_HDMI_CTRL_REKEY(rekey - 2);
1022         val |= NV_SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac);
1023         val |= NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT;
1024         tegra_sor_writel(sor, NV_SOR_HDMI_CTRL, val);
1025
1026 #ifndef CONFIG_TEGRA_NVDISPLAY
1027         tegra_dc_writel(dc, 0x180, DC_DISP_H_PULSE2_CONTROL);
1028         h_pulse_start = dc->mode.h_ref_to_sync +
1029                                         dc->mode.h_sync_width +
1030                                         dc->mode.h_back_porch - 10;
1031         h_pulse_end = h_pulse_start + 8;
1032         tegra_dc_writel(dc, PULSE_START(h_pulse_start) | PULSE_END(h_pulse_end),
1033                   DC_DISP_H_PULSE2_POSITION_A);
1034
1035         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1036         val |= H_PULSE_2_ENABLE;
1037         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
1038 #endif
1039 }
1040
1041 void tegra_hdmi_infoframe_pkt_write(struct tegra_hdmi *hdmi,
1042                                                 u32 header_reg, u8 pkt_type,
1043                                                 u8 pkt_vs, u8 pkt_len,
1044                                                 void *reg_payload,
1045                                                 u32 reg_payload_len,
1046                                                 bool sw_checksum)
1047 {
1048         struct tegra_dc_sor_data *sor = hdmi->sor;
1049         u32 val;
1050         u32 *data = reg_payload;
1051         u32 data_reg = header_reg + 1;
1052
1053         val = NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(pkt_type) |
1054                 NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(pkt_vs) |
1055                 NV_SOR_HDMI_INFOFRAME_HEADER_LEN(pkt_len);
1056         tegra_sor_writel(sor, header_reg, val);
1057
1058         if (sw_checksum) {
1059                 u8 checksum = pkt_type + pkt_vs + pkt_len;
1060
1061                 for (val = 1; val <= pkt_len; val++)
1062                         checksum += ((u8 *)reg_payload)[val];
1063
1064                 /* The first byte of the payload must always be the checksum
1065                  * that we are going to calculate in SW */
1066                 ((u8 *)reg_payload)[0] = (256 - checksum);
1067         }
1068
1069         for (val = 0; val < reg_payload_len; val += 4, data_reg++, data++)
1070                 tegra_sor_writel(sor, data_reg, *data);
1071 }
1072
1073 u32 tegra_hdmi_get_cea_modedb_size(struct tegra_hdmi *hdmi)
1074 {
1075         if (!tegra_hdmi_is_connected(hdmi) || !hdmi->mon_spec_valid)
1076                 return 0;
1077
1078         return (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM) ?
1079                 CEA_861_F_MODEDB_SIZE : CEA_861_D_MODEDB_SIZE;
1080 }
1081
1082 static void tegra_hdmi_get_cea_fb_videomode(struct fb_videomode *m,
1083                                                 struct tegra_hdmi *hdmi)
1084 {
1085         struct tegra_dc *dc = hdmi->dc;
1086         struct tegra_dc_mode dc_mode;
1087         int yuv_flag;
1088
1089         memcpy(&dc_mode, &dc->mode, sizeof(dc->mode));
1090
1091         /* get CEA video timings */
1092         yuv_flag = dc_mode.vmode & FB_VMODE_YUV_MASK;
1093         if (yuv_flag == (FB_VMODE_Y420      | FB_VMODE_Y24) ||
1094             yuv_flag == (FB_VMODE_Y420_ONLY | FB_VMODE_Y24)) {
1095                 dc_mode.h_back_porch *= 2;
1096                 dc_mode.h_front_porch *= 2;
1097                 dc_mode.h_sync_width *= 2;
1098                 dc_mode.h_active *= 2;
1099                 dc_mode.pclk *= 2;
1100         } else if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) {
1101                 dc_mode.h_back_porch = (dc_mode.h_back_porch * 8) / 5;
1102                 dc_mode.h_front_porch = (dc_mode.h_front_porch * 8) / 5;
1103                 dc_mode.h_sync_width = (dc_mode.h_sync_width * 8) / 5;
1104                 dc_mode.h_active = (dc_mode.h_active * 8) / 5;
1105                 dc_mode.pclk = (dc_mode.pclk / 5) * 8;
1106         }
1107
1108         tegra_dc_to_fb_videomode(m, &dc_mode);
1109
1110         /* only interlaced required for VIC identification */
1111         m->vmode &= FB_VMODE_INTERLACED;
1112 }
1113
1114 __maybe_unused
1115 static int tegra_hdmi_find_cea_vic(struct tegra_hdmi *hdmi)
1116 {
1117         struct fb_videomode m;
1118         struct tegra_dc *dc = hdmi->dc;
1119         unsigned i;
1120         unsigned best = 0;
1121         u32 modedb_size = tegra_hdmi_get_cea_modedb_size(hdmi);
1122
1123         if (dc->initialized) {
1124                 u32 vic = tegra_sor_readl(hdmi->sor,
1125                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH) & 0xff;
1126                 if (!vic)
1127                         dev_warn(&dc->ndev->dev, "hdmi: BL set VIC 0\n");
1128                 return vic;
1129         }
1130
1131         tegra_hdmi_get_cea_fb_videomode(&m, hdmi);
1132
1133         m.flag &= ~FB_FLAG_RATIO_MASK;
1134         m.flag |= tegra_dc_get_aspect_ratio(dc);
1135
1136         for (i = 1; i < modedb_size; i++) {
1137                 const struct fb_videomode *curr = &cea_modes[i];
1138
1139                 if (!fb_mode_is_equal_tolerance(curr, &m,
1140                         FB_MODE_TOLERANCE_DEFAULT))
1141                         continue;
1142
1143                 if (!best)
1144                         best = i;
1145                 /* if either flag is set, then match is required */
1146                 if (curr->flag &
1147                         (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9 |
1148                         FB_FLAG_RATIO_64_27 | FB_FLAG_RATIO_256_135)) {
1149                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1150                                 best = i;
1151                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1152                                 best = i;
1153                         else if (m.flag & curr->flag & FB_FLAG_RATIO_64_27)
1154                                 best = i;
1155                         else if (m.flag & curr->flag & FB_FLAG_RATIO_256_135)
1156                                 best = i;
1157                 } else {
1158                         best = i;
1159                 }
1160         }
1161         return best;
1162 }
1163
1164 static u32 tegra_hdmi_get_aspect_ratio(struct tegra_hdmi *hdmi)
1165 {
1166         u32 aspect_ratio;
1167
1168         switch (hdmi->dc->mode.avi_m) {
1169         case TEGRA_DC_MODE_AVI_M_4_3:
1170                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1171                 break;
1172         case TEGRA_DC_MODE_AVI_M_16_9:
1173                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1174                 break;
1175         /*
1176          * no avi_m field for picture aspect ratio 64:27 and 256:135.
1177          * sink detects via VIC, avi_m is 0.
1178          */
1179         case TEGRA_DC_MODE_AVI_M_64_27: /* fall through */
1180         case TEGRA_DC_MODE_AVI_M_256_135: /* fall through */
1181         default:
1182                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1183         }
1184
1185         /* For seamless HDMI, read aspect ratio parameters from bootloader
1186          * set AVI Infoframe parameters
1187          */
1188         if ((aspect_ratio == HDMI_AVI_ASPECT_RATIO_NO_DATA) &&
1189                                         (hdmi->dc->initialized)) {
1190                 u32 temp = 0;
1191                 temp = tegra_sor_readl(hdmi->sor,
1192                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1193                 temp = (temp >> 20) & 0x3;
1194                 switch (temp) {
1195                 case 1:
1196                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1197                 break;
1198                 case 2:
1199                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1200                 break;
1201                 default:
1202                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1203                 }
1204         }
1205         return aspect_ratio;
1206 }
1207
1208 static u32 tegra_hdmi_get_rgb_ycc(struct tegra_hdmi *hdmi)
1209 {
1210         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1211
1212         /*
1213          * For seamless HDMI, read YUV flag parameters from bootloader
1214          * set AVI Infoframe parameters
1215          */
1216         if (hdmi->dc->initialized) {
1217                 u32 temp = 0;
1218                 temp = tegra_sor_readl(hdmi->sor,
1219                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1220                 temp = (temp >> 12) & 0x3;
1221                 switch (temp) {
1222                 case HDMI_AVI_RGB:
1223                         return HDMI_AVI_RGB;
1224                 case HDMI_AVI_YCC_420:
1225                         return HDMI_AVI_YCC_420;
1226                 default:
1227                         dev_warn(&hdmi->dc->ndev->dev, "hdmi: BL didn't set RGB/YUV indicator flag\n");
1228                         break;
1229                 }
1230         }
1231
1232         if (yuv_flag & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
1233                 return HDMI_AVI_YCC_420;
1234         else if (yuv_flag & FB_VMODE_Y422)
1235                 return HDMI_AVI_YCC_422;
1236
1237         return HDMI_AVI_RGB;
1238 }
1239
1240 static bool tegra_hdmi_is_ex_colorimetry(struct tegra_hdmi *hdmi)
1241 {
1242         return !!(hdmi->dc->mode.vmode & FB_VMODE_EC_ENABLE);
1243 }
1244
1245 static u32 tegra_hdmi_get_ex_colorimetry(struct tegra_hdmi *hdmi)
1246 {
1247         u32 vmode = hdmi->dc->mode.vmode;
1248
1249         return tegra_hdmi_is_ex_colorimetry(hdmi) ?
1250                 ((vmode & FB_VMODE_EC_MASK) >> FB_VMODE_EC_SHIFT) :
1251                 HDMI_AVI_EXT_COLORIMETRY_INVALID;
1252 }
1253
1254 static void tegra_hdmi_avi_infoframe_update(struct tegra_hdmi *hdmi)
1255 {
1256         struct hdmi_avi_infoframe *avi = &hdmi->avi;
1257
1258         memset(&hdmi->avi, 0, sizeof(hdmi->avi));
1259
1260         if (tegra_platform_is_linsim())
1261                 return;
1262
1263         avi->scan = HDMI_AVI_UNDERSCAN;
1264         avi->bar_valid = HDMI_AVI_BAR_INVALID;
1265         avi->act_fmt_valid = HDMI_AVI_ACTIVE_FORMAT_VALID;
1266         avi->rgb_ycc = tegra_hdmi_get_rgb_ycc(hdmi);
1267
1268         avi->act_format = HDMI_AVI_ACTIVE_FORMAT_SAME;
1269         avi->aspect_ratio = tegra_hdmi_get_aspect_ratio(hdmi);
1270         avi->colorimetry = tegra_hdmi_is_ex_colorimetry(hdmi) ?
1271                         HDMI_AVI_COLORIMETRY_EXTENDED_VALID :
1272                         HDMI_AVI_COLORIMETRY_DEFAULT;
1273
1274         avi->scaling = HDMI_AVI_SCALING_UNKNOWN;
1275         avi->rgb_quant = HDMI_AVI_RGB_QUANT_DEFAULT;
1276         avi->ext_colorimetry = tegra_hdmi_get_ex_colorimetry(hdmi);
1277         avi->it_content = HDMI_AVI_IT_CONTENT_FALSE;
1278
1279         /* set correct vic if video format is cea defined else set 0 */
1280         avi->video_format = tegra_hdmi_find_cea_vic(hdmi);
1281
1282         avi->pix_rep = HDMI_AVI_NO_PIX_REPEAT;
1283         avi->it_content_type = HDMI_AVI_IT_CONTENT_NONE;
1284         avi->ycc_quant = HDMI_AVI_YCC_QUANT_NONE;
1285
1286         avi->top_bar_end_line_low_byte = 0;
1287         avi->top_bar_end_line_high_byte = 0;
1288
1289         avi->bot_bar_start_line_low_byte = 0;
1290         avi->bot_bar_start_line_high_byte = 0;
1291
1292         avi->left_bar_end_pixel_low_byte = 0;
1293         avi->left_bar_end_pixel_high_byte = 0;
1294
1295         avi->right_bar_start_pixel_low_byte = 0;
1296         avi->right_bar_start_pixel_high_byte = 0;
1297 }
1298
1299 static void tegra_hdmi_avi_infoframe(struct tegra_hdmi *hdmi)
1300 {
1301         struct tegra_dc_sor_data *sor = hdmi->sor;
1302
1303         if (hdmi->dvi)
1304                 return;
1305
1306         if (tegra_platform_is_linsim())
1307                 return;
1308
1309         /* disable avi infoframe before configuring except for seamless case */
1310         if (!hdmi->dc->initialized)
1311                 tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL, 0);
1312
1313         tegra_hdmi_avi_infoframe_update(hdmi);
1314
1315         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_AVI_INFOFRAME_HEADER,
1316                                         HDMI_INFOFRAME_TYPE_AVI,
1317                                         HDMI_INFOFRAME_VS_AVI,
1318                                         HDMI_INFOFRAME_LEN_AVI,
1319                                         &hdmi->avi, sizeof(hdmi->avi),
1320                                         false);
1321
1322         /* Send infoframe every frame, checksum hw generated */
1323         tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL,
1324                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES |
1325                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE |
1326                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE |
1327                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1328 }
1329
1330 static int tegra_hdmi_get_extended_vic(const struct tegra_dc_mode *mode)
1331 {
1332         struct fb_videomode m;
1333         unsigned i;
1334
1335         tegra_dc_to_fb_videomode(&m, mode);
1336
1337         /* only interlaced required for VIC identification */
1338         m.vmode &= FB_VMODE_INTERLACED;
1339
1340         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1341                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1342
1343                 if (fb_mode_is_equal_tolerance(curr, &m,
1344                         FB_MODE_TOLERANCE_DEFAULT))
1345                         return i;
1346         }
1347         return 0;
1348 }
1349
1350 static void tegra_hdmi_vendor_infoframe_update(struct tegra_hdmi *hdmi)
1351 {
1352         struct hdmi_vendor_infoframe *vsi = &hdmi->vsi;
1353         u8 extended_vic;
1354
1355         memset(&hdmi->vsi, 0, sizeof(hdmi->vsi));
1356
1357         vsi->oui = HDMI_LICENSING_LLC_OUI;
1358
1359         extended_vic = tegra_hdmi_get_extended_vic(&hdmi->dc->mode);
1360         if (extended_vic) {
1361                 vsi->video_format =
1362                         HDMI_VENDOR_VIDEO_FORMAT_EXTENDED;
1363                 vsi->extended_vic = extended_vic;
1364         }
1365 }
1366
1367 static void tegra_hdmi_vendor_infoframe(struct tegra_hdmi *hdmi)
1368 {
1369 /* hdmi licensing, LLC vsi playload len as per hdmi1.4b  */
1370 #define HDMI_INFOFRAME_LEN_VENDOR_LLC   (6)
1371
1372         struct tegra_dc_sor_data *sor = hdmi->sor;
1373
1374         if (hdmi->dvi)
1375                 return;
1376
1377         /* disable vsi infoframe before configuring */
1378         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL, 0);
1379
1380         tegra_hdmi_vendor_infoframe_update(hdmi);
1381
1382         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_VSI_INFOFRAME_HEADER,
1383                                         HDMI_INFOFRAME_TYPE_VENDOR,
1384                                         HDMI_INFOFRAME_VS_VENDOR,
1385                                         HDMI_INFOFRAME_LEN_VENDOR_LLC,
1386                                         &hdmi->vsi, sizeof(hdmi->vsi),
1387                                         false);
1388
1389         /* Send infoframe every frame, checksum hw generated */
1390         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL,
1391                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES |
1392                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE |
1393                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE |
1394                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1395
1396 #undef HDMI_INFOFRAME_LEN_VENDOR_LLC
1397 }
1398
1399 static void tegra_hdmi_hdr_infoframe_update(struct tegra_hdmi *hdmi)
1400 {
1401         struct hdmi_hdr_infoframe *hdr = &hdmi->hdr;
1402
1403         memset(&hdmi->hdr, 0, sizeof(hdmi->hdr));
1404
1405         if (tegra_platform_is_linsim())
1406                 return;
1407
1408         hdr->eotf = hdmi->dc->hdr.eotf;
1409         hdr->static_metadata_id = hdmi->dc->hdr.static_metadata_id;
1410
1411         /* PB3-14 : Group 1 : Static Metadata*/
1412         hdr->display_primaries_x_0_lsb = hdmi->dc->hdr.static_metadata[0];
1413         hdr->display_primaries_x_0_msb = hdmi->dc->hdr.static_metadata[1];
1414         hdr->display_primaries_y_0_lsb = hdmi->dc->hdr.static_metadata[2];
1415         hdr->display_primaries_y_0_msb = hdmi->dc->hdr.static_metadata[3];
1416         hdr->display_primaries_x_1_lsb = hdmi->dc->hdr.static_metadata[4];
1417         hdr->display_primaries_x_1_msb = hdmi->dc->hdr.static_metadata[5];
1418         hdr->display_primaries_y_1_lsb = hdmi->dc->hdr.static_metadata[6];
1419         hdr->display_primaries_y_1_msb = hdmi->dc->hdr.static_metadata[7];
1420         hdr->display_primaries_x_2_lsb = hdmi->dc->hdr.static_metadata[8];
1421         hdr->display_primaries_x_2_msb = hdmi->dc->hdr.static_metadata[9];
1422         hdr->display_primaries_y_2_lsb = hdmi->dc->hdr.static_metadata[10];
1423         hdr->display_primaries_y_2_msb = hdmi->dc->hdr.static_metadata[11];
1424
1425         /* PB15-18 : Group 2 : Static Metadata*/
1426         hdr->white_point_x_lsb = hdmi->dc->hdr.static_metadata[12];
1427         hdr->white_point_x_msb = hdmi->dc->hdr.static_metadata[13];
1428         hdr->white_point_y_lsb = hdmi->dc->hdr.static_metadata[14];
1429         hdr->white_point_y_msb = hdmi->dc->hdr.static_metadata[15];
1430
1431         /* PB19-20 : Group 3 : Static Metadata*/
1432         hdr->max_display_mastering_luminance_lsb =
1433                                         hdmi->dc->hdr.static_metadata[16];
1434         hdr->max_display_mastering_luminance_msb =
1435                                         hdmi->dc->hdr.static_metadata[17];
1436
1437         /* PB21-22 : Group 4 : Static Metadata*/
1438         hdr->min_display_mastering_luminance_lsb =
1439                                         hdmi->dc->hdr.static_metadata[18];
1440         hdr->min_display_mastering_luminance_msb =
1441                                         hdmi->dc->hdr.static_metadata[19];
1442
1443         /* PB23-24 : Group 5 : Static Metadata*/
1444         hdr->max_content_light_level_lsb = hdmi->dc->hdr.static_metadata[20];
1445         hdr->max_content_light_level_msb = hdmi->dc->hdr.static_metadata[21];
1446
1447         /* PB25-26 : Group 6 : Static Metadata*/
1448         hdr->max_frame_avg_light_level_lsb = hdmi->dc->hdr.static_metadata[22];
1449         hdr->min_frame_avg_light_level_msb = hdmi->dc->hdr.static_metadata[23];
1450
1451         return;
1452 }
1453
1454 static void tegra_hdmi_hdr_infoframe(struct tegra_hdmi *hdmi)
1455 {
1456         struct tegra_dc_sor_data *sor = hdmi->sor;
1457         u32 val;
1458
1459         /* set_bits = contains all the bits to be set
1460          * for NV_SOR_HDMI_GENERIC_CTRL reg */
1461         u32 set_bits = (NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES |
1462                         NV_SOR_HDMI_GENERIC_CTRL_OTHER_DISABLE |
1463                         NV_SOR_HDMI_GENERIC_CTRL_SINGLE_DISABLE);
1464
1465         /* read the current value to restore some bit values */
1466         val = (tegra_sor_readl(sor, NV_SOR_HDMI_GENERIC_CTRL)
1467                                 & ~set_bits);
1468
1469         /* disable generic infoframe before configuring */
1470         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL, 0);
1471
1472         tegra_hdmi_hdr_infoframe_update(hdmi);
1473
1474         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_GENERIC_HEADER,
1475                                         HDMI_INFOFRAME_TYPE_HDR,
1476                                         HDMI_INFOFRAME_VS_HDR,
1477                                         HDMI_INFOFRAME_LEN_HDR,
1478                                         &hdmi->hdr, sizeof(hdmi->hdr),
1479                                         true);
1480
1481         /* set the required bits in NV_SOR_HDMI_GENERIC_CTRL*/
1482         val = val | set_bits;
1483
1484         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL, val);
1485
1486         return;
1487 }
1488
1489 __maybe_unused
1490 static int tegra_hdmi_scdc_read(struct tegra_hdmi *hdmi,
1491                                         u8 offset_data[][2], u32 n_entries)
1492 {
1493         u32 i;
1494         struct i2c_msg msg[] = {
1495                 {
1496                         .addr = 0x54,
1497                         .len = 1,
1498                         .buf = NULL,
1499                 },
1500                 {
1501                         .addr = 0x54,
1502                         .flags = I2C_M_RD,
1503                         .len = 1,
1504                         .buf = NULL,
1505                 },
1506         };
1507
1508         _tegra_hdmi_ddc_enable(hdmi);
1509
1510         for (i = 0; i < n_entries; i++) {
1511                 msg[0].buf = offset_data[i];
1512                 msg[1].buf = &offset_data[i][1];
1513                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1514         }
1515
1516         _tegra_hdmi_ddc_disable(hdmi);
1517
1518         return 0;
1519 }
1520
1521 static int tegra_hdmi_scdc_write(struct tegra_hdmi *hdmi,
1522                                         u8 offset_data[][2], u32 n_entries)
1523 {
1524         u32 i;
1525         struct i2c_msg msg[] = {
1526                 {
1527                         .addr = 0x54,
1528                         .len = 2,
1529                         .buf = NULL,
1530                 },
1531         };
1532
1533         _tegra_hdmi_ddc_enable(hdmi);
1534
1535         for (i = 0; i < n_entries; i++) {
1536                 msg[0].buf = offset_data[i];
1537                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1538         }
1539
1540         _tegra_hdmi_ddc_disable(hdmi);
1541
1542         return 0;
1543 }
1544
1545 static int tegra_hdmi_v2_x_mon_config(struct tegra_hdmi *hdmi, bool enable)
1546 {
1547         u8 tmds_config_en[][2] = {
1548                 {
1549                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1550                         (HDMI_SCDC_TMDS_CONFIG_BIT_CLK_RATIO_40 |
1551                         HDMI_SCDC_TMDS_CONFIG_SCRAMBLING_EN)
1552                 },
1553         };
1554         u8 tmds_config_dis[][2] = {
1555                 {
1556                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1557                         0
1558                 },
1559         };
1560
1561         if (hdmi->dc->vedid)
1562                 goto skip_scdc_i2c;
1563
1564         tegra_hdmi_scdc_write(hdmi,
1565                         enable ? tmds_config_en : tmds_config_dis,
1566                         ARRAY_SIZE(tmds_config_en));
1567
1568 skip_scdc_i2c:
1569         return 0;
1570 }
1571
1572 static void tegra_hdmi_v2_x_host_config(struct tegra_hdmi *hdmi, bool enable)
1573 {
1574         u32 val = NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1575                 NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4;
1576
1577         tegra_sor_write_field(hdmi->sor, NV_SOR_HDMI2_CTRL,
1578                         NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1579                         NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4,
1580                         enable ? val : 0);
1581 }
1582
1583 static int _tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1584 {
1585 #define SCDC_STABILIZATION_DELAY_MS (20)
1586
1587         /* disable hdmi2.x config on host and monitor only
1588          * if bootloader didn't initialize hdmi
1589          */
1590         if (!hdmi->dc->initialized) {
1591                 tegra_hdmi_v2_x_mon_config(hdmi, false);
1592                 tegra_hdmi_v2_x_host_config(hdmi, false);
1593         }
1594
1595         /* enable hdmi2.x config on host and monitor */
1596         tegra_hdmi_v2_x_mon_config(hdmi, true);
1597         msleep(SCDC_STABILIZATION_DELAY_MS);
1598
1599         tegra_hdmi_v2_x_host_config(hdmi, true);
1600
1601         return 0;
1602 #undef SCDC_STABILIZATION_DELAY_MS
1603 }
1604
1605 static int tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1606 {
1607         _tegra_hdmi_v2_x_config(hdmi);
1608
1609         return 0;
1610 }
1611
1612 static void tegra_hdmi_scdc_worker(struct work_struct *work)
1613 {
1614         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
1615                                 struct tegra_hdmi, scdc_work);
1616         u8 rd_status_flags[][2] = {
1617                 {HDMI_SCDC_STATUS_FLAGS, 0x0}
1618         };
1619
1620         if (!hdmi->enabled || hdmi->dc->mode.pclk <= 340000000)
1621                 return;
1622
1623         if (hdmi->dc->vedid)
1624                 goto skip_scdc_i2c;
1625
1626         if (!tegra_edid_is_scdc_present(hdmi->dc->edid))
1627                 return;
1628
1629         tegra_hdmi_scdc_read(hdmi, rd_status_flags,
1630                                         ARRAY_SIZE(rd_status_flags));
1631         if (!rd_status_flags[0][1]  && (hdmi->dc->mode.pclk > 340000000)) {
1632                 dev_info(&hdmi->dc->ndev->dev, "hdmi: scdc scrambling status is reset, "
1633                                                 "trying to reconfigure.\n");
1634                 _tegra_hdmi_v2_x_config(hdmi);
1635         }
1636
1637 skip_scdc_i2c:
1638         /* reschedule the worker */
1639         cancel_delayed_work(&hdmi->scdc_work);
1640         schedule_delayed_work(&hdmi->scdc_work,
1641                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1642 }
1643
1644 static void _tegra_hdmi_clock_enable(struct tegra_hdmi *hdmi)
1645 {
1646         struct tegra_dc_sor_data *sor = hdmi->sor;
1647         tegra_disp_clk_prepare_enable(sor->safe_clk);
1648         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
1649         tegra_sor_clk_enable(sor);
1650 }
1651
1652 static void _tegra_hdmi_clock_disable(struct tegra_hdmi *hdmi)
1653 {
1654         struct tegra_dc_sor_data *sor = hdmi->sor;
1655         tegra_sor_clk_disable(sor);
1656 }
1657
1658 void tegra_hdmi_get(struct tegra_dc *dc)
1659 {
1660         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1661
1662         if (atomic_inc_return(&hdmi->clock_refcount) == 1)
1663                 _tegra_hdmi_clock_enable(hdmi);
1664 }
1665
1666 void tegra_hdmi_put(struct tegra_dc *dc)
1667 {
1668         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1669
1670         if (WARN_ONCE(atomic_read(&hdmi->clock_refcount) <= 0,
1671                 "hdmi: clock refcount imbalance"))
1672                 return;
1673         if (atomic_dec_return(&hdmi->clock_refcount) == 0)
1674                 _tegra_hdmi_clock_disable(hdmi);
1675 }
1676
1677 /* TODO: add support for other deep colors */
1678 static inline u32 tegra_hdmi_get_bpp(struct tegra_hdmi *hdmi)
1679 {
1680         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1681
1682         if ((yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) ||
1683                 (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y30)))
1684                 return 30;
1685         else if (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y36))
1686                 return 36;
1687         else if (yuv_flag == (FB_VMODE_Y422 | FB_VMODE_Y36))
1688                 return 24;
1689         else
1690                 return 0;
1691 }
1692
1693 static u32 tegra_hdmi_gcp_color_depth(struct tegra_hdmi *hdmi)
1694 {
1695         u32 gcp_cd = 0;
1696
1697         switch (tegra_hdmi_get_bpp(hdmi)) {
1698         case 0:
1699                 gcp_cd = TEGRA_HDMI_BPP_UNKNOWN;
1700                 break;
1701         case 24:
1702                 gcp_cd = TEGRA_HDMI_BPP_24;
1703                 break;
1704         case 30:
1705                 gcp_cd = TEGRA_HDMI_BPP_30;
1706                 break;
1707         case 36:
1708                 gcp_cd = TEGRA_HDMI_BPP_36;
1709                 break;
1710         case 48:
1711                 gcp_cd = TEGRA_HDMI_BPP_48;
1712                 break;
1713         default:
1714                 dev_WARN(&hdmi->dc->ndev->dev,
1715                         "hdmi: unknown gcp color depth\n");
1716         };
1717
1718         return gcp_cd;
1719 }
1720
1721 /* return packing phase of last pixel in preceding video data period */
1722 static u32 tegra_hdmi_gcp_packing_phase(struct tegra_hdmi *hdmi)
1723 {
1724         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1725
1726         if (!tegra_hdmi_gcp_color_depth(hdmi))
1727                 return 0;
1728
1729         if (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y36))
1730                 return 2;
1731         else
1732                 return 0;
1733 }
1734
1735 static bool tegra_hdmi_gcp_default_phase_en(struct tegra_hdmi *hdmi)
1736 {
1737         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1738
1739         if (!tegra_hdmi_gcp_color_depth(hdmi))
1740                 return false;
1741
1742         if ((yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) ||
1743                         (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y36)))
1744                 return true;
1745         else
1746                 return false;
1747 }
1748
1749 /* general control packet */
1750 static void tegra_hdmi_gcp(struct tegra_hdmi *hdmi)
1751 {
1752 #define GCP_SB1_PP_SHIFT 4
1753
1754         struct tegra_dc_sor_data *sor = hdmi->sor;
1755         u8 sb1, sb2;
1756
1757         /* disable gcp before configuring */
1758         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL, 0);
1759
1760         sb1 = tegra_hdmi_gcp_packing_phase(hdmi) << GCP_SB1_PP_SHIFT |
1761                 tegra_hdmi_gcp_color_depth(hdmi);
1762         sb2 = !!tegra_hdmi_gcp_default_phase_en(hdmi);
1763         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_SUBPACK(0),
1764                         sb1 << NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT |
1765                         sb2 << NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT);
1766
1767         /* Send gcp every frame */
1768         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL,
1769                         NV_SOR_HDMI_GCP_CTRL_ENABLE |
1770                         NV_SOR_HDMI_GCP_CTRL_OTHER_DIS |
1771                         NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS);
1772
1773 #undef GCP_SB1_PP_SHIFT
1774 }
1775
1776 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi)
1777 {
1778         struct tegra_dc *dc = hdmi->dc;
1779         struct tegra_dc_sor_data *sor = hdmi->sor;
1780
1781         tegra_dc_get(dc);
1782         tegra_hdmi_get(dc);
1783
1784         tegra_sor_hdmi_pad_power_up(sor);
1785
1786         tegra_sor_power_lanes(sor, 4, true);
1787
1788         tegra_dc_sor_set_internal_panel(sor, false);
1789         tegra_hdmi_config(hdmi);
1790         tegra_hdmi_avi_infoframe(hdmi);
1791         tegra_hdmi_vendor_infoframe(hdmi);
1792
1793         tegra_sor_pad_cal_power(sor, true);
1794         tegra_hdmi_config_tmds(hdmi);
1795         tegra_sor_pad_cal_power(sor, false);
1796
1797         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_BRICK_CLK);
1798         tegra_dc_sor_attach(sor);
1799         tegra_nvhdcp_set_plug(hdmi->nvhdcp, true);
1800
1801         tegra_dc_setup_clk(dc, dc->clk);
1802         tegra_dc_hdmi_setup_clk(dc, hdmi->sor->sor_clk);
1803         tegra_hdmi_config(hdmi);
1804
1805         tegra_sor_config_xbar(hdmi->sor);
1806
1807         /* TODO: Confirm sequence with HW */
1808         tegra_sor_writel(sor,  NV_SOR_SEQ_INST(0), 0x8080);
1809         tegra_sor_writel(sor,  NV_SOR_PWR, 0x80000001);
1810
1811         if (hdmi->dc->mode.pclk > 340000000) {
1812                 tegra_hdmi_v2_x_config(hdmi);
1813                 schedule_delayed_work(&hdmi->scdc_work,
1814                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1815         }
1816
1817         tegra_hdmi_gcp(hdmi);
1818
1819         tegra_dc_put(dc);
1820         return 0;
1821 }
1822
1823 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
1824 {
1825         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1826
1827         if (hdmi->enabled)
1828                 return;
1829
1830         tegra_hdmi_controller_enable(hdmi);
1831
1832         hdmi->enabled = true;
1833         tegra_hda_set_data(hdmi, SINK_HDMI);
1834 #ifdef CONFIG_SWITCH
1835         if (!hdmi->dvi)
1836                 switch_set_state(&hdmi->audio_switch, 1);
1837 #endif
1838 }
1839
1840 static inline u32 tegra_hdmi_get_shift_clk_div(struct tegra_hdmi *hdmi)
1841 {
1842         /*
1843          * HW does not support deep color yet
1844          * always return 0
1845          */
1846
1847         return 0;
1848 }
1849
1850 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
1851 {
1852         if (clk_type == hdmi->clk_type)
1853                 return;
1854
1855         if (tegra_platform_is_linsim())
1856                 return;
1857
1858         if (clk_type == TEGRA_HDMI_BRICK_CLK) {
1859                 u32 val;
1860                 struct tegra_dc_sor_data *sor = hdmi->sor;
1861                 int div = hdmi->dc->mode.pclk < 340000000 ? 1 : 2;
1862                 unsigned long rate = clk_get_rate(sor->src_switch_clk);
1863                 unsigned long parent_rate =
1864                         clk_get_rate(clk_get_parent(sor->src_switch_clk));
1865
1866                 /* Set sor divider */
1867                 if (rate != DIV_ROUND_UP(parent_rate, div)) {
1868                         rate = DIV_ROUND_UP(parent_rate, div);
1869                         clk_set_rate(sor->src_switch_clk, rate);
1870                 }
1871
1872                 /* Select brick muxes */
1873                 val = (hdmi->dc->mode.pclk < 340000000) ?
1874                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 :
1875                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4;
1876
1877                 val |= NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
1878                 tegra_sor_writel(hdmi->sor, NV_SOR_CLK_CNTRL, val);
1879                 usleep_range(250, 300); /* sor brick pll stabilization delay */
1880
1881                 /*
1882                  * Report brick configuration and rate, so that SOR clock tree
1883                  * is properly updated. No h/w changes by clock api calls below,
1884                  * just sync s/w state with brick h/w.
1885                  */
1886                 rate = rate/NV_SOR_HDMI_BRICK_DIV*NV_SOR_HDMI_BRICK_MUL(val);
1887                 if (clk_get_parent(sor->brick_clk) != sor->src_switch_clk)
1888                         clk_set_parent(sor->brick_clk, sor->src_switch_clk);
1889                 clk_set_rate(sor->brick_clk, rate);
1890
1891                 /*
1892                  * Select primary -- HDMI -- DVFS table for SOR clock (if SOR
1893                  * clock has single DVFS table for all modes, nothing changes).
1894                  */
1895                 tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, false);
1896
1897                 /* Select sor clock muxes */
1898                 tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
1899
1900                 tegra_dc_writel(hdmi->dc, PIXEL_CLK_DIVIDER_PCD1 |
1901                         SHIFT_CLK_DIVIDER(tegra_hdmi_get_shift_clk_div(hdmi)),
1902                         DC_DISP_DISP_CLOCK_CONTROL);
1903
1904                 hdmi->clk_type = TEGRA_HDMI_BRICK_CLK;
1905         } else if (clk_type == TEGRA_HDMI_SAFE_CLK) {
1906                 if (!hdmi->dc->initialized) {
1907                         /* Select sor clock muxes */
1908                         tegra_clk_cfg_ex(hdmi->sor->sor_clk,
1909                                 TEGRA_CLK_SOR_CLK_SEL, 0);
1910                         hdmi->clk_type = TEGRA_HDMI_SAFE_CLK;
1911                 }
1912         } else {
1913                 dev_err(&hdmi->dc->ndev->dev, "hdmi: incorrect clk type configured\n");
1914         }
1915 }
1916
1917 /* returns exact pixel clock in Hz */
1918 static long tegra_hdmi_get_pclk(struct tegra_dc_mode *mode)
1919 {
1920         long h_total, v_total;
1921         long refresh, pclk;
1922         h_total = mode->h_active + mode->h_front_porch + mode->h_back_porch +
1923                 mode->h_sync_width;
1924         v_total = mode->v_active + mode->v_front_porch + mode->v_back_porch +
1925                 mode->v_sync_width;
1926         refresh = tegra_dc_calc_refresh(mode);
1927         refresh = DIV_ROUND_CLOSEST(refresh, 1000);
1928
1929         if (mode->vmode & FB_VMODE_1000DIV1001) {
1930                 refresh = refresh * 1000 * 1000 / 1001;
1931                 refresh = DIV_ROUND_CLOSEST(refresh, 10);
1932                 refresh = refresh * 10;
1933                 pclk = h_total * v_total * refresh / 1000;
1934                 pclk = DIV_ROUND_CLOSEST(pclk, 10000) * 10000;
1935         } else {
1936                 pclk = h_total * v_total * refresh;
1937         }
1938
1939         return pclk;
1940 }
1941
1942 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
1943 {
1944 #ifdef CONFIG_TEGRA_NVDISPLAY
1945         struct clk *parent_clk = tegra_disp_clk_get(&dc->ndev->dev,
1946                                 dc->out->parent_clk ? : "plld2");
1947 #else
1948         struct clk *parent_clk = clk_get(NULL,
1949                                 dc->out->parent_clk ? : "pll_d2");
1950 #endif
1951
1952         dc->mode.pclk = tegra_hdmi_get_pclk(&dc->mode);
1953
1954         if (IS_ERR_OR_NULL(parent_clk)) {
1955                 dev_err(&dc->ndev->dev, "hdmi: parent clk get failed\n");
1956                 return 0;
1957         }
1958
1959         if (!tegra_platform_is_silicon())
1960                 return dc->mode.pclk;
1961
1962 #ifdef CONFIG_TEGRA_NVDISPLAY
1963         if (clk_get_parent(clk) != parent_clk)
1964                 clk_set_parent(clk, parent_clk);
1965 #else
1966         if (clk == dc->clk) {
1967                 if (clk_get_parent(clk) != parent_clk) {
1968                         if (clk_set_parent(clk, parent_clk)) {
1969                                 dev_err(&dc->ndev->dev,
1970                                         "hdmi: set dc parent failed\n");
1971                                 return 0;
1972                         }
1973                 }
1974         } else {
1975                 struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1976                 struct tegra_dc_sor_data *sor = hdmi->sor;
1977
1978                 if (clk_get_parent(sor->src_switch_clk) != parent_clk) {
1979                         if (clk_set_parent(sor->src_switch_clk, parent_clk)) {
1980                                 dev_err(&dc->ndev->dev,
1981                                         "hdmi: set src switch parent failed\n");
1982                                 return 0;
1983                         }
1984                 }
1985         }
1986 #endif
1987         if (dc->initialized)
1988                 goto skip_setup;
1989         if (clk_get_rate(parent_clk) != dc->mode.pclk)
1990                 clk_set_rate(parent_clk, dc->mode.pclk);
1991 skip_setup:
1992         /*
1993          * DC clock divider is controlled by DC driver transparently to clock
1994          * framework -- hence, direct call to DVFS with target mode rate. SOR
1995          * clock rate in clock tree is properly updated, and can be used for
1996          * DVFS update.
1997          *
1998          * TODO: tegra_hdmi_controller_enable() procedure 1st configures SOR
1999          * clock via tegra_hdmi_config_clk(), and then calls this function
2000          * that may re-lock parent PLL. That needs to be double-checked:
2001          * in general re-locking PLL while the downstream module is already
2002          * sourced from it is not recommended. If/when the order of enabling
2003          * HDMI controller is changed, we can remove direct DVFS call for SOR
2004          * (but for DC it should be kept, anyway).
2005          */
2006         if (clk == dc->clk)
2007                 tegra_dvfs_set_rate(clk, dc->mode.pclk);
2008         else
2009                 tegra_dvfs_set_rate(clk, clk_get_rate(clk));
2010
2011         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2012 }
2013
2014 static void tegra_dc_hdmi_shutdown(struct tegra_dc *dc)
2015 {
2016         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2017
2018         _tegra_hdmivrr_activate(hdmi, false);
2019         hdmi->device_shutdown = true;
2020         tegra_nvhdcp_shutdown(hdmi->nvhdcp);
2021
2022         return;
2023 }
2024
2025 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2026 {
2027         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2028
2029         _tegra_hdmivrr_activate(hdmi, false);
2030         hdmi->enabled = false;
2031 #ifdef CONFIG_SWITCH
2032         switch_set_state(&hdmi->audio_switch, 0);
2033 #endif
2034
2035         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
2036         tegra_hdmi_controller_disable(hdmi);
2037         tegra_hda_reset_data();
2038         return;
2039 }
2040
2041 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
2042 {
2043         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2044         unsigned long delay = msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS);
2045
2046         if (tegra_platform_is_linsim())
2047                 return true;
2048
2049         if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL)
2050                 delay = 0;
2051
2052         cancel_delayed_work(&hdmi->hpd_worker);
2053         schedule_delayed_work(&hdmi->hpd_worker, delay);
2054
2055         return tegra_dc_hpd(dc);
2056 }
2057
2058 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
2059 {
2060         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2061
2062         _tegra_hdmivrr_activate(hdmi, false);
2063
2064         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
2065                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
2066                 int ret;
2067
2068                 ret = enable_irq_wake(wake_irq);
2069                 if (ret < 0) {
2070                         dev_err(&dc->ndev->dev,
2071                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
2072                         __func__, wake_irq, ret);
2073                 }
2074         }
2075
2076         atomic_set(&hdmi->suspended, 1);
2077 }
2078
2079 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
2080 {
2081         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2082
2083         atomic_set(&hdmi->suspended, 0);
2084
2085         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
2086                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
2087
2088         cancel_delayed_work(&hdmi->hpd_worker);
2089
2090         /* If resume happens with a non-VRR monitor, the HPD
2091            worker will correct the mode based on the new EDID */
2092         _tegra_hdmivrr_activate(hdmi, true);
2093
2094         schedule_delayed_work(&hdmi->hpd_worker,
2095                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS + HDMI_HPD_DROP_TIMEOUT_MS));
2096 }
2097
2098 static int tegra_dc_hdmi_set_hdr(struct tegra_dc *dc)
2099 {
2100         u16 ret = 0;
2101         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2102         ret = tegra_edid_get_ex_hdr_cap(hdmi->edid);
2103         if (ret & FB_CAP_HDR)
2104                 tegra_hdmi_hdr_infoframe(hdmi);
2105         return 0;
2106 }
2107
2108 static int tegra_dc_hdmi_ddc_enable(struct tegra_dc *dc)
2109 {
2110         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2111         _tegra_hdmi_ddc_enable(hdmi);
2112         return 0;
2113 }
2114
2115 static int tegra_dc_hdmi_ddc_disable(struct tegra_dc *dc)
2116 {
2117         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2118         _tegra_hdmi_ddc_disable(hdmi);
2119         return 0;
2120 }
2121
2122 static void tegra_dc_hdmi_modeset_notifier(struct tegra_dc *dc)
2123 {
2124         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2125
2126         tegra_hdmi_get(dc);
2127         tegra_dc_io_start(dc);
2128
2129         /* disable hdmi2.x config on host and monitor */
2130         if (dc->mode.pclk > 340000000) {
2131                 if (tegra_edid_is_scdc_present(dc->edid))
2132                         tegra_hdmi_v2_x_mon_config(hdmi, true);
2133                 tegra_hdmi_v2_x_host_config(hdmi, true);
2134         } else {
2135                 if (tegra_edid_is_scdc_present(dc->edid))
2136                         tegra_hdmi_v2_x_mon_config(hdmi, false);
2137                 tegra_hdmi_v2_x_host_config(hdmi, false);
2138         }
2139
2140         tegra_dc_io_end(dc);
2141         tegra_hdmi_put(dc);
2142 }
2143
2144 #ifdef CONFIG_DEBUG_FS
2145 /* show current hpd state */
2146 static int tegra_hdmi_hotplug_dbg_show(struct seq_file *m, void *unused)
2147 {
2148         struct tegra_hdmi *hdmi = m->private;
2149         struct tegra_dc *dc = hdmi->dc;
2150
2151         if (WARN_ON(!hdmi || !dc || !dc->out))
2152                 return -EINVAL;
2153
2154         rmb();
2155         seq_printf(m, "hdmi hpd state: %d\n", dc->out->hotplug_state);
2156
2157         return 0;
2158 }
2159
2160 int tegra_hdmi_get_hotplug_state(struct tegra_hdmi *hdmi)
2161 {
2162         rmb();
2163         return hdmi->dc->out->hotplug_state;
2164 }
2165
2166 void tegra_hdmi_set_hotplug_state(struct tegra_hdmi *hdmi, int new_hpd_state)
2167 {
2168         struct tegra_dc *dc = hdmi->dc;
2169         int hotplug_state;
2170
2171         rmb();
2172         hotplug_state = dc->out->hotplug_state;
2173
2174         if (hotplug_state == TEGRA_HPD_STATE_NORMAL &&
2175                         new_hpd_state != TEGRA_HPD_STATE_NORMAL &&
2176                         tegra_dc_hotplug_supported(dc)) {
2177                 disable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2178         } else if (hotplug_state != TEGRA_HPD_STATE_NORMAL &&
2179                         new_hpd_state == TEGRA_HPD_STATE_NORMAL &&
2180                         tegra_dc_hotplug_supported(dc)) {
2181                 enable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2182         }
2183
2184         dc->out->hotplug_state = new_hpd_state;
2185         wmb();
2186
2187         /*
2188          * sw controlled plug/unplug.
2189          * wait for any already executing hpd worker thread.
2190          * No debounce delay, schedule immedately
2191          */
2192         cancel_delayed_work_sync(&hdmi->hpd_worker);
2193         schedule_delayed_work(&hdmi->hpd_worker, 0);
2194 }
2195
2196 /*
2197  * sw control for hpd.
2198  * 0 is normal state, hw drives hpd.
2199  * -1 is force deassert, sw drives hpd.
2200  * 1 is force assert, sw drives hpd.
2201  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
2202  */
2203 static ssize_t tegra_hdmi_hotplug_dbg_write(struct file *file,
2204                                         const char __user *addr,
2205                                         size_t len, loff_t *pos)
2206 {
2207         struct seq_file *m = file->private_data;
2208         struct tegra_hdmi *hdmi = m->private;
2209         struct tegra_dc *dc = hdmi->dc;
2210         long new_hpd_state;
2211         int ret;
2212
2213         if (WARN_ON(!hdmi || !dc || !dc->out))
2214                 return -EINVAL;
2215
2216         ret = kstrtol_from_user(addr, len, 10, &new_hpd_state);
2217         if (ret < 0)
2218                 return ret;
2219
2220         tegra_hdmi_set_hotplug_state(hdmi, new_hpd_state);
2221
2222         return len;
2223 }
2224
2225 static int tegra_hdmi_hotplug_dbg_open(struct inode *inode, struct file *file)
2226 {
2227         return single_open(file, tegra_hdmi_hotplug_dbg_show, inode->i_private);
2228 }
2229
2230 static const struct file_operations tegra_hdmi_hotplug_dbg_ops = {
2231         .open = tegra_hdmi_hotplug_dbg_open,
2232         .read = seq_read,
2233         .write = tegra_hdmi_hotplug_dbg_write,
2234         .llseek = seq_lseek,
2235         .release = single_release,
2236 };
2237
2238 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2239 {
2240         struct dentry *dir, *ret;
2241
2242         dir = debugfs_create_dir("tegra_hdmi",  NULL);
2243         if (IS_ERR_OR_NULL(dir))
2244                 return;
2245
2246         ret = debugfs_create_file("hotplug", S_IRUGO, dir,
2247                                 hdmi, &tegra_hdmi_hotplug_dbg_ops);
2248         if (IS_ERR_OR_NULL(ret))
2249                 goto fail;
2250
2251         return;
2252 fail:
2253         debugfs_remove_recursive(dir);
2254         return;
2255 }
2256 #else
2257 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2258 {
2259         return;
2260 }
2261 #endif
2262
2263 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
2264                 struct kobj_attribute *attr, const char *buf, size_t count)
2265 {
2266         int value;
2267         sscanf(buf, "%du", &value);
2268         tegra_hdmi_ddc_power_toggle(value);
2269         return count;
2270 }
2271
2272 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
2273                 struct kobj_attribute *attr, char *buf)
2274 {
2275         return sprintf(buf, "%d\n", dc_hdmi->ddc_refcount);
2276 }
2277
2278 static bool tegra_dc_hdmi_hpd_state(struct tegra_dc *dc)
2279 {
2280         int sense;
2281         int level;
2282         bool hpd;
2283
2284         if (WARN_ON(!dc || !dc->out))
2285                 return false;
2286
2287         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
2288
2289         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
2290
2291         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
2292                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
2293
2294         return hpd;
2295 }
2296
2297 static void tegra_dc_hdmi_vrr_enable(struct tegra_dc *dc, bool enable)
2298 {
2299         struct tegra_vrr *vrr  = dc->out->vrr;
2300
2301         if (!vrr)
2302                 return;
2303
2304         if (!(dc->mode.vmode & FB_VMODE_VRR)) {
2305                 WARN(enable, "VRR enable request in non-VRR mode\n");
2306                 return;
2307         }
2308
2309         vrr->enable = enable;
2310 }
2311
2312 static void tegra_dc_hdmi_postpoweron(struct tegra_dc *dc)
2313 {
2314         _tegra_hdmivrr_activate(tegra_dc_get_outdata(dc), true);
2315 }
2316
2317 struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops = {
2318         .init = tegra_dc_hdmi_init,
2319         .destroy = tegra_dc_hdmi_destroy,
2320         .enable = tegra_dc_hdmi_enable,
2321         .disable = tegra_dc_hdmi_disable,
2322         .setup_clk = tegra_dc_hdmi_setup_clk,
2323         .detect = tegra_dc_hdmi_detect,
2324         .shutdown = tegra_dc_hdmi_shutdown,
2325         .suspend = tegra_dc_hdmi_suspend,
2326         .resume = tegra_dc_hdmi_resume,
2327         .ddc_enable = tegra_dc_hdmi_ddc_enable,
2328         .ddc_disable = tegra_dc_hdmi_ddc_disable,
2329         .modeset_notifier = tegra_dc_hdmi_modeset_notifier,
2330         .mode_filter = tegra_hdmi_fb_mode_filter,
2331         .hpd_state = tegra_dc_hdmi_hpd_state,
2332         .vrr_enable = tegra_dc_hdmi_vrr_enable,
2333         .vrr_update_monspecs = tegra_hdmivrr_update_monspecs,
2334         .set_hdr = tegra_dc_hdmi_set_hdr,
2335         .postpoweron = tegra_dc_hdmi_postpoweron,
2336 };