2 * include/linux/tegra_profiler.h
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef __TEGRA_PROFILER_H
18 #define __TEGRA_PROFILER_H
20 #include <linux/ioctl.h>
22 #define QUADD_SAMPLES_VERSION 33
23 #define QUADD_IO_VERSION 18
25 #define QUADD_IO_VERSION_DYNAMIC_RB 5
26 #define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
27 #define QUADD_IO_VERSION_MOD_STATE_STATUS_FIELD 7
28 #define QUADD_IO_VERSION_BT_KERNEL_CTX 8
29 #define QUADD_IO_VERSION_GET_MMAP 9
30 #define QUADD_IO_VERSION_BT_UNWIND_TABLES 10
31 #define QUADD_IO_VERSION_UNWIND_MIXED 11
32 #define QUADD_IO_VERSION_EXTABLES_MMAP 12
33 #define QUADD_IO_VERSION_ARCH_TIMER_OPT 13
34 #define QUADD_IO_VERSION_DATA_MMAP 14
35 #define QUADD_IO_VERSION_BT_LOWER_BOUND 15
36 #define QUADD_IO_VERSION_STACK_OFFSET 16
37 #define QUADD_IO_VERSION_SECTIONS_INFO 17
38 #define QUADD_IO_VERSION_UNW_METHODS_OPT 18
40 #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
41 #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
42 #define QUADD_SAMPLE_VERSION_THREAD_STATE_FLD 19
43 #define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22
44 #define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23
45 #define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24
46 #define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25
47 #define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE 26
48 #define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER 27
49 #define QUADD_SAMPLE_VERSION_SCHED_SAMPLES 28
50 #define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29
51 #define QUADD_SAMPLE_VERSION_HDR_ARCH_TIMER 30
52 #define QUADD_SAMPLE_VERSION_STACK_OFFSET 31
53 #define QUADD_SAMPLE_VERSION_SCHED_TASK_STATE 32
54 #define QUADD_SAMPLE_VERSION_URCS 33
56 #define QUADD_MMAP_HEADER_VERSION 1
58 #define QUADD_MAX_COUNTERS 32
59 #define QUADD_MAX_PROCESS 64
61 #define QUADD_DEVICE_NAME "quadd"
62 #define QUADD_AUTH_DEVICE_NAME "quadd_auth"
64 #define QUADD_MOD_DEVICE_NAME "quadd_mod"
65 #define QUADD_MOD_AUTH_DEVICE_NAME "quadd_mod_auth"
67 #define QUADD_IOCTL 100
70 * Setup params (profiling frequency, etc.)
72 #define IOCTL_SETUP _IOW(QUADD_IOCTL, 0, struct quadd_parameters)
77 #define IOCTL_START _IO(QUADD_IOCTL, 1)
82 #define IOCTL_STOP _IO(QUADD_IOCTL, 2)
85 * Getting capabilities
87 #define IOCTL_GET_CAP _IOR(QUADD_IOCTL, 3, struct quadd_comm_cap)
90 * Getting state of module
92 #define IOCTL_GET_STATE _IOR(QUADD_IOCTL, 4, struct quadd_module_state)
95 * Getting version of module
97 #define IOCTL_GET_VERSION _IOR(QUADD_IOCTL, 5, struct quadd_module_version)
100 * Send exception-handling tables info
101 * This ioctl is obsolete
103 /*#define IOCTL_SET_EXTAB _IOW(QUADD_IOCTL, 6, struct quadd_extables)*/
106 * Send ring buffer mmap info
108 #define IOCTL_SET_MMAP_RB _IOW(QUADD_IOCTL, 7, struct quadd_mmap_rb_info)
113 #define IOCTL_SET_SECTIONS_INFO _IOW(QUADD_IOCTL, 8, struct quadd_sections)
115 #define QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP (1 << 29) /* LP CPU */
116 #define QUADD_CPUMODE_THUMB (1 << 30) /* thumb mode */
118 enum quadd_events_id {
119 QUADD_EVENT_TYPE_CPU_CYCLES = 0,
121 QUADD_EVENT_TYPE_INSTRUCTIONS,
122 QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS,
123 QUADD_EVENT_TYPE_BRANCH_MISSES,
124 QUADD_EVENT_TYPE_BUS_CYCLES,
126 QUADD_EVENT_TYPE_L1_DCACHE_READ_MISSES,
127 QUADD_EVENT_TYPE_L1_DCACHE_WRITE_MISSES,
128 QUADD_EVENT_TYPE_L1_ICACHE_MISSES,
130 QUADD_EVENT_TYPE_L2_DCACHE_READ_MISSES,
131 QUADD_EVENT_TYPE_L2_DCACHE_WRITE_MISSES,
132 QUADD_EVENT_TYPE_L2_ICACHE_MISSES,
134 QUADD_EVENT_TYPE_MAX,
145 enum quadd_record_type {
146 QUADD_RECORD_TYPE_SAMPLE = 1,
147 QUADD_RECORD_TYPE_MMAP,
148 QUADD_RECORD_TYPE_MA,
149 QUADD_RECORD_TYPE_COMM,
150 QUADD_RECORD_TYPE_DEBUG,
151 QUADD_RECORD_TYPE_HEADER,
152 QUADD_RECORD_TYPE_POWER_RATE,
153 QUADD_RECORD_TYPE_ADDITIONAL_SAMPLE,
154 QUADD_RECORD_TYPE_SCHED,
157 enum quadd_event_source {
158 QUADD_EVENT_SOURCE_PMU = 1,
159 QUADD_EVENT_SOURCE_PL310,
162 enum quadd_cpu_mode {
163 QUADD_CPU_MODE_KERNEL = 1,
168 #pragma pack(push, 1)
170 #define QUADD_SAMPLE_RES_URCS_ENABLED (1 << 0)
172 #define QUADD_SAMPLE_URC_MASK 0xff
174 #define QUADD_SAMPLE_URC_SHIFT_FP 0
175 #define QUADD_SAMPLE_URC_SHIFT_UT (1 * 8)
176 #define QUADD_SAMPLE_URC_SHIFT_DWARF (2 * 8)
179 QUADD_URC_SUCCESS = 0,
181 QUADD_URC_IDX_NOT_FOUND,
182 QUADD_URC_TBL_NOT_EXIST,
184 QUADD_URC_TBL_IS_CORRUPT,
185 QUADD_URC_CANTUNWIND,
186 QUADD_URC_UNHANDLED_INSTRUCTION,
187 QUADD_URC_REFUSE_TO_UNWIND,
188 QUADD_URC_SP_INCORRECT,
189 QUADD_URC_SPARE_ENCODING,
190 QUADD_URC_UNSUPPORTED_PR,
191 QUADD_URC_PC_INCORRECT,
192 QUADD_URC_LEVEL_TOO_DEEP,
193 QUADD_URC_FP_INCORRECT,
195 QUADD_URC_UNWIND_MISMATCH,
196 QUADD_URC_TBL_LINK_INCORRECT,
200 #define QUADD_SED_IP64 (1 << 0)
202 #define QUADD_SED_STACK_OFFSET_SHIFT 1
203 #define QUADD_SED_STACK_OFFSET_MASK (0xffff << QUADD_SED_STACK_OFFSET_SHIFT)
206 QUADD_UNW_TYPE_FP = 0,
208 QUADD_UNW_TYPE_LR_FP,
209 QUADD_UNW_TYPE_LR_UT,
211 QUADD_UNW_TYPE_DWARF_EH,
212 QUADD_UNW_TYPE_DWARF_DF,
215 struct quadd_sample_data {
232 #define QUADD_MMAP_ED_IS_FILE_EXISTS (1 << 0)
234 struct quadd_mmap_data {
244 struct quadd_ma_data {
252 struct quadd_power_rate_data {
261 struct quadd_additional_sample {
269 QUADD_SCHED_IDX_TASK_STATE = 0,
270 QUADD_SCHED_IDX_RESERVED,
273 struct quadd_sched_data {
286 QM_DEBUG_SAMPLE_TYPE_SCHED_IN = 1,
287 QM_DEBUG_SAMPLE_TYPE_SCHED_OUT,
289 QM_DEBUG_SAMPLE_TYPE_TIMER_HANDLE,
290 QM_DEBUG_SAMPLE_TYPE_TIMER_START,
291 QM_DEBUG_SAMPLE_TYPE_TIMER_CANCEL,
292 QM_DEBUG_SAMPLE_TYPE_TIMER_FORWARD,
294 QM_DEBUG_SAMPLE_TYPE_READ_COUNTER,
296 QM_DEBUG_SAMPLE_TYPE_SOURCE_START,
297 QM_DEBUG_SAMPLE_TYPE_SOURCE_STOP,
300 struct quadd_debug_data {
316 #define QUADD_HEADER_MAGIC 0x1122
318 #define QUADD_HDR_BT_FP (1 << 0)
319 #define QUADD_HDR_BT_UT (1 << 1)
320 #define QUADD_HDR_BT_UT_CE (1 << 2)
321 #define QUADD_HDR_USE_ARCH_TIMER (1 << 3)
322 #define QUADD_HDR_STACK_OFFSET (1 << 4)
323 #define QUADD_HDR_BT_DWARF (1 << 5)
325 struct quadd_header_data {
335 reserved:26; /* reserved fields for future extensions */
345 struct quadd_record_data {
348 /* sample: it should be the biggest size */
350 struct quadd_sample_data sample;
351 struct quadd_mmap_data mmap;
352 struct quadd_ma_data ma;
353 struct quadd_debug_data debug;
354 struct quadd_header_data hdr;
355 struct quadd_power_rate_data power_rate;
356 struct quadd_sched_data sched;
357 struct quadd_additional_sample additional_sample;
363 #define QUADD_MAX_PACKAGE_NAME 320
366 QUADD_PARAM_IDX_SIZE_OF_RB = 0,
367 QUADD_PARAM_IDX_EXTRA = 1,
368 QUADD_PARAM_IDX_BT_LOWER_BOUND = 2,
371 #define QUADD_PARAM_EXTRA_GET_MMAP (1 << 0)
372 #define QUADD_PARAM_EXTRA_BT_FP (1 << 1)
373 #define QUADD_PARAM_EXTRA_BT_UT (1 << 2)
374 #define QUADD_PARAM_EXTRA_BT_MIXED (1 << 3)
375 #define QUADD_PARAM_EXTRA_USE_ARCH_TIMER (1 << 4)
376 #define QUADD_PARAM_EXTRA_STACK_OFFSET (1 << 5)
377 #define QUADD_PARAM_EXTRA_BT_UT_CE (1 << 6)
378 #define QUADD_PARAM_EXTRA_BT_DWARF (1 << 7)
380 struct quadd_parameters {
390 u32 pids[QUADD_MAX_PROCESS];
393 u8 package_name[QUADD_MAX_PACKAGE_NAME];
395 u32 events[QUADD_MAX_COUNTERS];
398 u32 reserved[16]; /* reserved fields for future extensions */
401 struct quadd_events_cap {
404 branch_instructions:1,
408 l1_dcache_read_misses:1,
409 l1_dcache_write_misses:1,
412 l2_dcache_read_misses:1,
413 l2_dcache_write_misses:1,
418 QUADD_COMM_CAP_IDX_EXTRA = 0,
421 #define QUADD_COMM_CAP_EXTRA_BT_KERNEL_CTX (1 << 0)
422 #define QUADD_COMM_CAP_EXTRA_GET_MMAP (1 << 1)
423 #define QUADD_COMM_CAP_EXTRA_GROUP_SAMPLES (1 << 2)
424 #define QUADD_COMM_CAP_EXTRA_BT_UNWIND_TABLES (1 << 3)
425 #define QUADD_COMM_CAP_EXTRA_SUPPORT_AARCH64 (1 << 4)
426 #define QUADD_COMM_CAP_EXTRA_SPECIAL_ARCH_MMAP (1 << 5)
427 #define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED (1 << 6)
428 #define QUADD_COMM_CAP_EXTRA_UNW_ENTRY_TYPE (1 << 7)
429 #define QUADD_COMM_CAP_EXTRA_ARCH_TIMER (1 << 8)
430 #define QUADD_COMM_CAP_EXTRA_RB_MMAP_OP (1 << 9)
432 struct quadd_comm_cap {
436 l2_multiple_events:1,
440 struct quadd_events_cap events_cap;
442 u32 reserved[16]; /* reserved fields for future extensions */
446 QUADD_MOD_STATE_IDX_RB_MAX_FILL_COUNT = 0,
447 QUADD_MOD_STATE_IDX_STATUS,
450 #define QUADD_MOD_STATE_STATUS_IS_ACTIVE (1 << 0)
451 #define QUADD_MOD_STATE_STATUS_IS_AUTH_OPEN (1 << 1)
453 struct quadd_module_state {
455 u64 nr_skipped_samples;
458 u32 buffer_fill_size;
460 u32 reserved[16]; /* reserved fields for future extensions */
463 struct quadd_module_version {
470 u32 reserved[4]; /* reserved fields for future extensions */
474 QUADD_SEC_TYPE_EXTAB = 0,
475 QUADD_SEC_TYPE_EXIDX,
477 QUADD_SEC_TYPE_EH_FRAME,
478 QUADD_SEC_TYPE_EH_FRAME_HDR,
480 QUADD_SEC_TYPE_DEBUG_FRAME,
481 QUADD_SEC_TYPE_DEBUG_FRAME_HDR,
486 struct quadd_sec_info {
493 struct quadd_sections {
497 struct quadd_sec_info sec[QUADD_SEC_TYPE_MAX];
501 u64 reserved[4]; /* reserved fields for future extensions */
504 struct quadd_mmap_rb_info {
510 u32 reserved[4]; /* reserved fields for future extensions */
513 #define QUADD_MMAP_HEADER_MAGIC 0x33445566
515 struct quadd_mmap_header {
522 u32 reserved[4]; /* reserved fields for future extensions */
526 QUADD_RB_STATE_NONE = 0,
527 QUADD_RB_STATE_ACTIVE,
528 QUADD_RB_STATE_STOPPED,
531 struct quadd_ring_buffer_hdr {
541 u32 reserved[4]; /* reserved fields for future extensions */
549 struct vm_area_struct;
551 #ifdef CONFIG_TEGRA_PROFILER
552 extern void __quadd_task_sched_in(struct task_struct *prev,
553 struct task_struct *task);
554 extern void __quadd_task_sched_out(struct task_struct *prev,
555 struct task_struct *next);
557 extern void __quadd_event_mmap(struct vm_area_struct *vma);
559 static inline void quadd_task_sched_in(struct task_struct *prev,
560 struct task_struct *task)
562 __quadd_task_sched_in(prev, task);
565 static inline void quadd_task_sched_out(struct task_struct *prev,
566 struct task_struct *next)
568 __quadd_task_sched_out(prev, next);
571 static inline void quadd_event_mmap(struct vm_area_struct *vma)
573 __quadd_event_mmap(vma);
576 #else /* CONFIG_TEGRA_PROFILER */
578 static inline void quadd_task_sched_in(struct task_struct *prev,
579 struct task_struct *task)
583 static inline void quadd_task_sched_out(struct task_struct *prev,
584 struct task_struct *next)
588 static inline void quadd_event_mmap(struct vm_area_struct *vma)
592 #endif /* CONFIG_TEGRA_PROFILER */
594 #endif /* __KERNEL__ */
596 #endif /* __TEGRA_PROFILER_H */