2 * Copyright (C) 2009 Palm, Inc.
3 * Author: Yvonne Yip <y@palm.com>
5 * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef __PLATFORM_DATA_TEGRA_SDHCI_H
18 #define __PLATFORM_DATA_TEGRA_SDHCI_H
20 #include <linux/mmc/host.h>
21 #include <asm/mach/mmc.h>
24 * MMC_OCR_1V8_MASK will be used in board sdhci file
25 * Example for cardhu it will be used in board-cardhu-sdhci.c
26 * for built_in = 0 devices enabling ocr_mask to MMC_OCR_1V8_MASK
27 * sets the voltage to 1.8V
29 #define MMC_OCR_1V8_MASK 0x00000008
30 #define MMC_OCR_2V8_MASK 0x00010000
31 #define MMC_OCR_3V2_MASK 0x00100000
32 #define MMC_OCR_3V3_MASK 0x00200000
34 /* uhs mask can be used to mask any of the UHS modes support */
35 #define MMC_UHS_MASK_SDR12 0x1
36 #define MMC_UHS_MASK_SDR25 0x2
37 #define MMC_UHS_MASK_SDR50 0x4
38 #define MMC_UHS_MASK_DDR50 0x8
39 #define MMC_UHS_MASK_SDR104 0x10
40 #define MMC_MASK_HS200 0x20
41 #define MMC_MASK_HS400 0x40
43 /* runtime power management implementation type */
45 RTPM_TYPE_DELAY_CG = 0,
49 #define IS_MMC_RTPM(type) (type == RTPM_TYPE_MMC)
50 #define IS_RTPM_DELAY_CG(type) (type == RTPM_TYPE_DELAY_CG)
51 #define GET_RTPM_TYPE(type) \
52 (IS_RTPM_DELAY_CG(type) ? "delayed clock gate rtpm" : \
53 "mmc rtpm coupled with clock gate")
55 struct tegra_sdhci_platform_data {
64 int min_vcore_override_mv;
66 unsigned int max_clk_limit;
67 unsigned int ddr_clk_limit;
68 unsigned int tap_delay;
69 bool is_ddr_tap_delay;
70 unsigned int ddr_tap_delay;
71 unsigned int trim_delay;
72 bool is_ddr_trim_delay;
73 unsigned int ddr_trim_delay;
74 unsigned int dqs_trim_delay;
75 unsigned int dqs_trim_delay_hs533;
76 unsigned int uhs_mask;
78 struct mmc_platform_data mmc_data;
81 bool cd_wakeup_incapable;
82 bool en_nominal_vcore_tuning;
83 unsigned int calib_3v3_offsets; /* Format to be filled: 0xXXXXPDPU */
84 unsigned int calib_1v8_offsets; /* Format to be filled: 0xXXXXPDPU */
85 unsigned int compad_vref_3v3;
86 unsigned int compad_vref_1v8;
87 bool disable_clock_gate; /* no clock gate when true */
88 bool update_pinctrl_settings;
90 unsigned int default_drv_type;
91 bool dll_calib_needed;
92 bool pwr_off_during_lp0;
93 bool disable_auto_cal;
94 unsigned int auto_cal_step;
97 bool limit_vddio_max_volt;
98 bool enb_ext_loopback;
99 bool enable_hs533_mode;
100 bool dynamic_dma_pio_switch;
102 bool is_fix_clock_freq;
103 /*Index 0 is fixed for ID mode. Rest according the MMC_TIMINGS modes*/
104 unsigned int fixed_clk_freq_table[MMC_TIMINGS_MAX_MODES + 1];
105 bool enable_autocal_slew_override;
106 unsigned int rtpm_type;
108 bool en_strobe; /* Enable enhance strobe mode for eMMC */
109 bool enb_feedback_clock;
110 bool en_periodic_calib;
111 /* Flag when true disables register dump after KSO sleep mode */
112 bool bcm_sdio_suppress_kso_dump;
114 struct gpio gpios[6];