arch/arm/mach-tegra/devices.c

   1 /*
   2  * Copyright (C) 2010,2011 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@android.com>
   6  *      Erik Gilling <ccross@android.com>
   7  *
   8  * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21
  22 #include <linux/resource.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/fsl_devices.h>
  25 #include <linux/serial_8250.h>
  26 #include <linux/mipi-bif-tegra.h>
  27 #include <linux/platform_data/tegra_usb.h>
  28 #include <linux/tegra_avp.h>
  29 #include <linux/nvhost.h>
  30 #include <linux/clk.h>
  31 #include <linux/tegra-soc.h>
  32 #include <mach/irqs.h>
  33 #include <linux/usb/tegra_usb_phy.h>
  34 #include <mach/tegra_smmu.h>
  35 #include <mach/tegra-swgid.h>
  36 #include <linux/dma-contiguous.h>
  37
  38 #ifdef CONFIG_TEGRA_WAKEUP_MONITOR
  39 #include <mach/tegra_wakeup_monitor.h>
  40 #endif
  41
  42 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
  43 #include <asm/dma-iommu.h>
  44 #endif
  45
  46 #include "gpio-names.h"
  47 #include "iomap.h"
  48 #include "devices.h"
  49 #include "board.h"
  50 #include "tegra_ptm.h"
  51
  52 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
  53 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
  54 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
  55 #define TEGRA_DMA_REQ_SEL_SPI                   11
  56 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
  57
  58 static struct resource emc_resource[] = {
  59         [0] = {
  60                 .start  = TEGRA_EMC_BASE,
  61                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
  62                 .flags  = IORESOURCE_MEM,
  63         }
  64 };
  65
  66 struct platform_device tegra_emc_device = {
  67         .name           = "tegra-emc",
  68         .id             = -1,
  69         .resource       = emc_resource,
  70         .num_resources  = ARRAY_SIZE(emc_resource),
  71 };
  72
  73 static struct resource gpio_resource[] = {
  74         [0] = {
  75                 .start  = TEGRA_GPIO_BASE,
  76                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
  77                 .flags  = IORESOURCE_MEM,
  78         },
  79         [1] = {
  80                 .start  = INT_GPIO1,
  81                 .end    = INT_GPIO1,
  82                 .flags  = IORESOURCE_IRQ,
  83         },
  84         [2] = {
  85                 .start  = INT_GPIO2,
  86                 .end    = INT_GPIO2,
  87                 .flags  = IORESOURCE_IRQ,
  88         },
  89         [3] = {
  90                 .start  = INT_GPIO3,
  91                 .end    = INT_GPIO3,
  92                 .flags  = IORESOURCE_IRQ,
  93         },
  94         [4] = {
  95                 .start  = INT_GPIO4,
  96                 .end    = INT_GPIO4,
  97                 .flags  = IORESOURCE_IRQ,
  98         },
  99         [5] = {
 100                 .start  = INT_GPIO5,
 101                 .end    = INT_GPIO5,
 102                 .flags  = IORESOURCE_IRQ,
 103         },
 104         [6] = {
 105                 .start  = INT_GPIO6,
 106                 .end    = INT_GPIO6,
 107                 .flags  = IORESOURCE_IRQ,
 108         },
 109         [7] = {
 110                 .start  = INT_GPIO7,
 111                 .end    = INT_GPIO7,
 112                 .flags  = IORESOURCE_IRQ,
 113         },
 114 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 115         [8] = {
 116                 .start  = INT_GPIO8,
 117                 .end    = INT_GPIO8,
 118                 .flags  = IORESOURCE_IRQ,
 119         },
 120 #endif
 121 };
 122
 123 struct platform_device tegra_gpio_device = {
 124         .name           = "tegra-gpio",
 125         .id             = -1,
 126         .resource       = gpio_resource,
 127         .num_resources  = ARRAY_SIZE(gpio_resource),
 128 };
 129
 130 static struct resource tegra124_pinctrl_resource[] = {
 131         [0] = {
 132                 /* Drive registers */
 133                 .start  = TEGRA_APB_MISC_BASE + 0x868,
 134                 .end    = TEGRA_APB_MISC_BASE + 0x9c8 + 3,
 135                 .flags  = IORESOURCE_MEM,
 136         },
 137         [1] = {
 138                 /* Mux registers */
 139                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
 140                 .end    = TEGRA_APB_MISC_BASE + 0x3430 + 3,
 141                 .flags  = IORESOURCE_MEM,
 142         },
 143 };
 144
 145 struct platform_device tegra124_pinctrl_device = {
 146         .name           = "tegra124-pinctrl",
 147         .id             = -1,
 148         .resource       = tegra124_pinctrl_resource,
 149         .num_resources  = ARRAY_SIZE(tegra124_pinctrl_resource),
 150 };
 151
 152 static struct resource tegra114_pinctrl_resource[] = {
 153         [0] = {
 154                 /* Drive registers */
 155                 .start  = TEGRA_APB_MISC_BASE + 0x868,
 156                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
 157                 .flags  = IORESOURCE_MEM,
 158         },
 159         [1] = {
 160                 /* Mux registers */
 161                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
 162                 .end    = TEGRA_APB_MISC_BASE + 0x3408 + 3,
 163                 .flags  = IORESOURCE_MEM,
 164         },
 165 };
 166
 167 struct platform_device tegra114_pinctrl_device = {
 168         .name           = "tegra114-pinctrl",
 169         .id             = -1,
 170         .resource       = tegra114_pinctrl_resource,
 171         .num_resources  = ARRAY_SIZE(tegra114_pinctrl_resource),
 172 };
 173
 174 static struct resource apbdma_resource[] = {
 175         [0] = {
 176                 .start  = TEGRA_APB_DMA_BASE,
 177                 .end    = TEGRA_APB_DMA_BASE + TEGRA_APB_DMA_SIZE-1,
 178                 .flags  = IORESOURCE_MEM,
 179         },
 180         [1] = {
 181                 .start  = INT_APB_DMA_CH0,
 182                 .end    = INT_APB_DMA_CH0,
 183                 .flags  = IORESOURCE_IRQ,
 184         },
 185         [2] = {
 186                 .start  = INT_APB_DMA_CH1,
 187                 .end    = INT_APB_DMA_CH1,
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190         [3] = {
 191                 .start  = INT_APB_DMA_CH2,
 192                 .end    = INT_APB_DMA_CH2,
 193                 .flags  = IORESOURCE_IRQ,
 194         },
 195         [4] = {
 196                 .start  = INT_APB_DMA_CH3,
 197                 .end    = INT_APB_DMA_CH3,
 198                 .flags  = IORESOURCE_IRQ,
 199         },
 200         [5] = {
 201                 .start  = INT_APB_DMA_CH4,
 202                 .end    = INT_APB_DMA_CH4,
 203                 .flags  = IORESOURCE_IRQ,
 204         },
 205         [6] = {
 206                 .start  = INT_APB_DMA_CH5,
 207                 .end    = INT_APB_DMA_CH5,
 208                 .flags  = IORESOURCE_IRQ,
 209         },
 210         [7] = {
 211                 .start  = INT_APB_DMA_CH6,
 212                 .end    = INT_APB_DMA_CH6,
 213                 .flags  = IORESOURCE_IRQ,
 214         },
 215         [8] = {
 216                 .start  = INT_APB_DMA_CH7,
 217                 .end    = INT_APB_DMA_CH7,
 218                 .flags  = IORESOURCE_IRQ,
 219         },
 220         [9] = {
 221                 .start  = INT_APB_DMA_CH8,
 222                 .end    = INT_APB_DMA_CH8,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225         [10] = {
 226                 .start  = INT_APB_DMA_CH9,
 227                 .end    = INT_APB_DMA_CH9,
 228                 .flags  = IORESOURCE_IRQ,
 229         },
 230         [11] = {
 231                 .start  = INT_APB_DMA_CH10,
 232                 .end    = INT_APB_DMA_CH10,
 233                 .flags  = IORESOURCE_IRQ,
 234         },
 235         [12] = {
 236                 .start  = INT_APB_DMA_CH11,
 237                 .end    = INT_APB_DMA_CH11,
 238                 .flags  = IORESOURCE_IRQ,
 239         },
 240         [13] = {
 241                 .start  = INT_APB_DMA_CH12,
 242                 .end    = INT_APB_DMA_CH12,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245         [14] = {
 246                 .start  = INT_APB_DMA_CH13,
 247                 .end    = INT_APB_DMA_CH13,
 248                 .flags  = IORESOURCE_IRQ,
 249         },
 250         [15] = {
 251                 .start  = INT_APB_DMA_CH14,
 252                 .end    = INT_APB_DMA_CH14,
 253                 .flags  = IORESOURCE_IRQ,
 254         },
 255         [16] = {
 256                 .start  = INT_APB_DMA_CH15,
 257                 .end    = INT_APB_DMA_CH15,
 258                 .flags  = IORESOURCE_IRQ,
 259         },
 260         [17] = {
 261                 .start  = INT_APB_DMA_CH16,
 262                 .end    = INT_APB_DMA_CH16,
 263                 .flags  = IORESOURCE_IRQ,
 264         },
 265         [18] = {
 266                 .start  = INT_APB_DMA_CH17,
 267                 .end    = INT_APB_DMA_CH17,
 268                 .flags  = IORESOURCE_IRQ,
 269         },
 270         [19] = {
 271                 .start  = INT_APB_DMA_CH18,
 272                 .end    = INT_APB_DMA_CH18,
 273                 .flags  = IORESOURCE_IRQ,
 274         },
 275         [20] = {
 276                 .start  = INT_APB_DMA_CH19,
 277                 .end    = INT_APB_DMA_CH19,
 278                 .flags  = IORESOURCE_IRQ,
 279         },
 280         [21] = {
 281                 .start  = INT_APB_DMA_CH20,
 282                 .end    = INT_APB_DMA_CH20,
 283                 .flags  = IORESOURCE_IRQ,
 284         },
 285         [22] = {
 286                 .start  = INT_APB_DMA_CH21,
 287                 .end    = INT_APB_DMA_CH21,
 288                 .flags  = IORESOURCE_IRQ,
 289         },
 290         [23] = {
 291                 .start  = INT_APB_DMA_CH22,
 292                 .end    = INT_APB_DMA_CH22,
 293                 .flags  = IORESOURCE_IRQ,
 294         },
 295         [24] = {
 296                 .start  = INT_APB_DMA_CH23,
 297                 .end    = INT_APB_DMA_CH23,
 298                 .flags  = IORESOURCE_IRQ,
 299         },
 300         [25] = {
 301                 .start  = INT_APB_DMA_CH24,
 302                 .end    = INT_APB_DMA_CH24,
 303                 .flags  = IORESOURCE_IRQ,
 304         },
 305         [26] = {
 306                 .start  = INT_APB_DMA_CH25,
 307                 .end    = INT_APB_DMA_CH25,
 308                 .flags  = IORESOURCE_IRQ,
 309         },
 310         [27] = {
 311                 .start  = INT_APB_DMA_CH26,
 312                 .end    = INT_APB_DMA_CH26,
 313                 .flags  = IORESOURCE_IRQ,
 314         },
 315         [28] = {
 316                 .start  = INT_APB_DMA_CH27,
 317                 .end    = INT_APB_DMA_CH27,
 318                 .flags  = IORESOURCE_IRQ,
 319         },
 320         [29] = {
 321                 .start  = INT_APB_DMA_CH28,
 322                 .end    = INT_APB_DMA_CH28,
 323                 .flags  = IORESOURCE_IRQ,
 324         },
 325         [30] = {
 326                 .start  = INT_APB_DMA_CH29,
 327                 .end    = INT_APB_DMA_CH29,
 328                 .flags  = IORESOURCE_IRQ,
 329         },
 330         [31] = {
 331                 .start  = INT_APB_DMA_CH30,
 332                 .end    = INT_APB_DMA_CH30,
 333                 .flags  = IORESOURCE_IRQ,
 334         },
 335         [32] = {
 336                 .start  = INT_APB_DMA_CH31,
 337                 .end    = INT_APB_DMA_CH31,
 338                 .flags  = IORESOURCE_IRQ,
 339         },
 340
 341 };
 342
 343 struct platform_device tegra_apbdma = {
 344         .name           = "tegra124-apbdma",
 345         .id             = -1,
 346         .resource       = apbdma_resource,
 347         .num_resources  = ARRAY_SIZE(apbdma_resource),
 348 };
 349
 350 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
 351
 352 static struct tegra_mipi_bif_platform_data mipi_bif_pdata = {
 353         .adapter_nr     = -1,
 354         .tauBIF         = 2,
 355         .bus_clk_rate   = 13,
 356 };
 357
 358 static struct resource mipi_bif_resource[] = {
 359         [0] = {
 360                 .start  = INT_MIPI_BIF,
 361                 .end    = INT_MIPI_BIF,
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364         [1] = {
 365                 .start  = TEGRA_MIPI_BIF_BASE,
 366                 .end    = TEGRA_MIPI_BIF_BASE + TEGRA_MIPI_BIF_SIZE - 1,
 367                 .flags  = IORESOURCE_MEM,
 368         },
 369 };
 370
 371 struct platform_device tegra_mipi_bif_device = {
 372         .name           = "tegra-mipi-bif",
 373         .id             = -1,
 374         .resource       = mipi_bif_resource,
 375         .num_resources  = ARRAY_SIZE(mipi_bif_resource),
 376         .dev = {
 377                 .platform_data = &mipi_bif_pdata,
 378         },
 379 };
 380
 381 #endif
 382
 383 static struct resource spi_resource1[] = {
 384         [0] = {
 385                 .start  = INT_SPI_1,
 386                 .end    = INT_SPI_1,
 387                 .flags  = IORESOURCE_IRQ,
 388         },
 389         [1] = {
 390                 .start  = TEGRA_SPI1_BASE,
 391                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
 392                 .flags  = IORESOURCE_MEM,
 393         },
 394 };
 395
 396 static struct resource spi_resource2[] = {
 397         [0] = {
 398                 .start  = INT_SPI_2,
 399                 .end    = INT_SPI_2,
 400                 .flags  = IORESOURCE_IRQ,
 401         },
 402         [1] = {
 403                 .start  = TEGRA_SPI2_BASE,
 404                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
 405                 .flags  = IORESOURCE_MEM,
 406         },
 407 };
 408
 409 static struct resource spi_resource3[] = {
 410         [0] = {
 411                 .start  = INT_SPI_3,
 412                 .end    = INT_SPI_3,
 413                 .flags  = IORESOURCE_IRQ,
 414         },
 415         [1] = {
 416                 .start  = TEGRA_SPI3_BASE,
 417                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
 418                 .flags  = IORESOURCE_MEM,
 419         },
 420 };
 421
 422 static struct resource spi_resource4[] = {
 423         [0] = {
 424                 .start  = INT_SPI_4,
 425                 .end    = INT_SPI_4,
 426                 .flags  = IORESOURCE_IRQ,
 427         },
 428         [1] = {
 429                 .start  = TEGRA_SPI4_BASE,
 430                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
 431                 .flags  = IORESOURCE_MEM,
 432         },
 433 };
 434 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 435 static struct resource spi_resource5[] = {
 436         [0] = {
 437                 .start  = INT_SPI_5,
 438                 .end    = INT_SPI_5,
 439                 .flags  = IORESOURCE_IRQ,
 440         },
 441         [1] = {
 442                 .start  = TEGRA_SPI5_BASE,
 443                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
 444                 .flags  = IORESOURCE_MEM,
 445         },
 446 };
 447
 448 static struct resource spi_resource6[] = {
 449         [0] = {
 450                 .start  = INT_SPI_6,
 451                 .end    = INT_SPI_6,
 452                 .flags  = IORESOURCE_IRQ,
 453         },
 454         [1] = {
 455                 .start  = TEGRA_SPI6_BASE,
 456                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
 457                 .flags  = IORESOURCE_MEM,
 458         },
 459 };
 460 #endif
 461
 462 struct platform_device tegra_spi_device1 = {
 463         .name           = "spi_tegra",
 464         .id             = 0,
 465         .resource       = spi_resource1,
 466         .num_resources  = ARRAY_SIZE(spi_resource1),
 467         .dev            = {
 468                 .coherent_dma_mask      = 0xffffffff,
 469         },
 470 };
 471
 472 struct platform_device tegra_spi_device2 = {
 473         .name           = "spi_tegra",
 474         .id             = 1,
 475         .resource       = spi_resource2,
 476         .num_resources  = ARRAY_SIZE(spi_resource2),
 477         .dev            = {
 478                 .coherent_dma_mask      = 0xffffffff,
 479         },
 480 };
 481
 482 struct platform_device tegra_spi_device3 = {
 483         .name           = "spi_tegra",
 484         .id             = 2,
 485         .resource       = spi_resource3,
 486         .num_resources  = ARRAY_SIZE(spi_resource3),
 487         .dev            = {
 488                 .coherent_dma_mask      = 0xffffffff,
 489         },
 490 };
 491
 492 struct platform_device tegra_spi_device4 = {
 493         .name           = "spi_tegra",
 494         .id             = 3,
 495         .resource       = spi_resource4,
 496         .num_resources  = ARRAY_SIZE(spi_resource4),
 497         .dev            = {
 498                 .coherent_dma_mask      = 0xffffffff,
 499         },
 500 };
 501 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 502 struct platform_device tegra_spi_device5 = {
 503         .name           = "spi_tegra",
 504         .id             = 4,
 505         .resource       = spi_resource5,
 506         .num_resources  = ARRAY_SIZE(spi_resource5),
 507         .dev  = {
 508                 .coherent_dma_mask      = 0xffffffff,
 509         },
 510 };
 511
 512 struct platform_device tegra_spi_device6 = {
 513         .name           = "spi_tegra",
 514         .id             = 5,
 515         .resource       = spi_resource6,
 516         .num_resources  = ARRAY_SIZE(spi_resource6),
 517         .dev  = {
 518                 .coherent_dma_mask      = 0xffffffff,
 519         },
 520 };
 521 #endif
 522
 523 struct platform_device tegra11_spi_device1 = {
 524         .name           = "spi-tegra114",
 525         .id             = 0,
 526         .resource       = spi_resource1,
 527         .num_resources  = ARRAY_SIZE(spi_resource1),
 528         .dev            = {
 529                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 530         },
 531 };
 532
 533 struct platform_device tegra11_spi_device2 = {
 534         .name           = "spi-tegra114",
 535         .id             = 1,
 536         .resource       = spi_resource2,
 537         .num_resources  = ARRAY_SIZE(spi_resource2),
 538         .dev            = {
 539                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 540         },
 541 };
 542
 543 struct platform_device tegra11_spi_device3 = {
 544         .name           = "spi-tegra114",
 545         .id             = 2,
 546         .resource       = spi_resource3,
 547         .num_resources  = ARRAY_SIZE(spi_resource3),
 548         .dev            = {
 549                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 550         },
 551 };
 552
 553 struct platform_device tegra11_spi_device4 = {
 554         .name           = "spi-tegra114",
 555         .id             = 3,
 556         .resource       = spi_resource4,
 557         .num_resources  = ARRAY_SIZE(spi_resource4),
 558         .dev            = {
 559                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 560         },
 561 };
 562
 563 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 564 struct platform_device tegra11_spi_device5 = {
 565         .name           = "spi-tegra114",
 566         .id             = 4,
 567         .resource       = spi_resource5,
 568         .num_resources  = ARRAY_SIZE(spi_resource5),
 569         .dev  = {
 570                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 571         },
 572 };
 573
 574 struct platform_device tegra11_spi_device6 = {
 575         .name           = "spi-tegra114",
 576         .id             = 5,
 577         .resource       = spi_resource6,
 578         .num_resources  = ARRAY_SIZE(spi_resource6),
 579         .dev  = {
 580                 .coherent_dma_mask      = DMA_BIT_MASK(64),
 581         },
 582 };
 583 #endif
 584
 585 struct platform_device tegra_spi_slave_device1 = {
 586         .name           = "spi_slave_tegra",
 587         .id             = 0,
 588         .resource       = spi_resource1,
 589         .num_resources  = ARRAY_SIZE(spi_resource1),
 590         .dev  = {
 591                 .coherent_dma_mask      = 0xffffffff,
 592         },
 593 };
 594
 595 struct platform_device tegra_spi_slave_device2 = {
 596         .name           = "spi_slave_tegra",
 597         .id             = 1,
 598         .resource       = spi_resource2,
 599         .num_resources  = ARRAY_SIZE(spi_resource2),
 600         .dev  = {
 601                 .coherent_dma_mask      = 0xffffffff,
 602         },
 603 };
 604
 605 struct platform_device tegra_spi_slave_device3 = {
 606         .name           = "spi_slave_tegra",
 607         .id             = 2,
 608         .resource       = spi_resource3,
 609         .num_resources  = ARRAY_SIZE(spi_resource3),
 610         .dev  = {
 611                 .coherent_dma_mask      = 0xffffffff,
 612         },
 613 };
 614
 615 struct platform_device tegra_spi_slave_device4 = {
 616         .name           = "spi_slave_tegra",
 617         .id             = 3,
 618         .resource       = spi_resource4,
 619         .num_resources  = ARRAY_SIZE(spi_resource4),
 620         .dev  = {
 621                 .coherent_dma_mask      = 0xffffffff,
 622         },
 623 };
 624 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 625 struct platform_device tegra_spi_slave_device5 = {
 626         .name           = "spi_slave_tegra",
 627         .id             = 4,
 628         .resource       = spi_resource5,
 629         .num_resources  = ARRAY_SIZE(spi_resource5),
 630         .dev  = {
 631                 .coherent_dma_mask      = 0xffffffff,
 632         },
 633 };
 634
 635 struct platform_device tegra_spi_slave_device6 = {
 636         .name           = "spi_slave_tegra",
 637         .id             = 5,
 638         .resource       = spi_resource6,
 639         .num_resources  = ARRAY_SIZE(spi_resource6),
 640         .dev  = {
 641                 .coherent_dma_mask      = 0xffffffff,
 642         },
 643 };
 644 #endif
 645
 646 struct platform_device tegra11_spi_slave_device1 = {
 647         .name           = "tegra11-spi-slave",
 648         .id             = 0,
 649         .resource       = spi_resource1,
 650         .num_resources  = ARRAY_SIZE(spi_resource1),
 651         .dev  = {
 652                 .coherent_dma_mask      = 0xffffffff,
 653         },
 654 };
 655
 656 struct platform_device tegra11_spi_slave_device2 = {
 657         .name           = "tegra11-spi-slave",
 658         .id             = 1,
 659         .resource       = spi_resource2,
 660         .num_resources  = ARRAY_SIZE(spi_resource2),
 661         .dev  = {
 662                 .coherent_dma_mask      = 0xffffffff,
 663         },
 664 };
 665
 666 struct platform_device tegra11_spi_slave_device3 = {
 667         .name           = "tegra11-spi-slave",
 668         .id             = 2,
 669         .resource       = spi_resource3,
 670         .num_resources  = ARRAY_SIZE(spi_resource3),
 671         .dev  = {
 672                 .coherent_dma_mask      = 0xffffffff,
 673         },
 674 };
 675
 676 struct platform_device tegra11_spi_slave_device4 = {
 677         .name           = "tegra11-spi-slave",
 678         .id             = 3,
 679         .resource       = spi_resource4,
 680         .num_resources  = ARRAY_SIZE(spi_resource4),
 681         .dev  = {
 682                 .coherent_dma_mask      = 0xffffffff,
 683         },
 684 };
 685 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 686 struct platform_device tegra11_spi_slave_device5 = {
 687         .name           = "tegra11-spi-slave",
 688         .id             = 4,
 689         .resource       = spi_resource5,
 690         .num_resources  = ARRAY_SIZE(spi_resource5),
 691         .dev  = {
 692                 .coherent_dma_mask      = 0xffffffff,
 693         },
 694 };
 695
 696 struct platform_device tegra11_spi_slave_device6 = {
 697         .name           = "tegra11-spi-slave",
 698         .id             = 5,
 699         .resource       = spi_resource6,
 700         .num_resources  = ARRAY_SIZE(spi_resource6),
 701         .dev  = {
 702                 .coherent_dma_mask      = 0xffffffff,
 703         },
 704 };
 705 #endif
 706
 707 static struct resource resources_nor[] = {
 708         [0] = {
 709                 .start = INT_SNOR,
 710                 .end = INT_SNOR,
 711                 .flags = IORESOURCE_IRQ,
 712         },
 713         [1] = {
 714                 /* Map SNOR Controller */
 715                 .start = TEGRA_SNOR_BASE,
 716                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
 717                 .flags = IORESOURCE_MEM,
 718         },
 719         [2] = {
 720                 /* Map the size of flash */
 721                 .start = TEGRA_NOR_FLASH_BASE,
 722                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
 723                 .flags = IORESOURCE_MEM,
 724         }
 725 };
 726
 727 struct platform_device tegra_nor_device = {
 728         .name = "tegra-nor",
 729         .id = -1,
 730         .num_resources = ARRAY_SIZE(resources_nor),
 731         .resource = resources_nor,
 732         .dev = {
 733                 .coherent_dma_mask = 0xffffffff,
 734         },
 735 };
 736
 737 static struct resource dtv_resource[] = {
 738         [0] = {
 739                 .start  = TEGRA_DTV_BASE,
 740                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
 741                 .flags  = IORESOURCE_MEM,
 742         },
 743         [1] = {
 744                 .start  = TEGRA_DMA_REQ_SEL_DTV,
 745                 .end    = TEGRA_DMA_REQ_SEL_DTV,
 746                 .flags  = IORESOURCE_DMA
 747         },
 748 };
 749
 750 struct platform_device tegra_dtv_device = {
 751         .name           = "tegra_dtv",
 752         .id             = -1,
 753         .resource       = dtv_resource,
 754         .num_resources  = ARRAY_SIZE(dtv_resource),
 755         .dev = {
 756                 .init_name = "dtv",
 757                 .coherent_dma_mask = 0xffffffff,
 758         },
 759 };
 760
 761 static struct resource sdhci_resource1[] = {
 762         [0] = {
 763                 .start  = INT_SDMMC1,
 764                 .end    = INT_SDMMC1,
 765                 .flags  = IORESOURCE_IRQ,
 766         },
 767         [1] = {
 768                 .start  = TEGRA_SDMMC1_BASE,
 769                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
 770                 .flags  = IORESOURCE_MEM,
 771         },
 772 };
 773
 774 static struct resource sdhci_resource2[] = {
 775         [0] = {
 776                 .start  = INT_SDMMC2,
 777                 .end    = INT_SDMMC2,
 778                 .flags  = IORESOURCE_IRQ,
 779         },
 780         [1] = {
 781                 .start  = TEGRA_SDMMC2_BASE,
 782                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
 783                 .flags  = IORESOURCE_MEM,
 784         },
 785 };
 786
 787 static struct resource sdhci_resource3[] = {
 788         [0] = {
 789                 .start  = INT_SDMMC3,
 790                 .end    = INT_SDMMC3,
 791                 .flags  = IORESOURCE_IRQ,
 792         },
 793         [1] = {
 794                 .start  = TEGRA_SDMMC3_BASE,
 795                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
 796                 .flags  = IORESOURCE_MEM,
 797         },
 798 };
 799
 800 static struct resource sdhci_resource4[] = {
 801         [0] = {
 802                 .start  = INT_SDMMC4,
 803                 .end    = INT_SDMMC4,
 804                 .flags  = IORESOURCE_IRQ,
 805         },
 806         [1] = {
 807                 .start  = TEGRA_SDMMC4_BASE,
 808                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
 809                 .flags  = IORESOURCE_MEM,
 810         },
 811 };
 812
 813 struct platform_device tegra_pci_device = {
 814         .name           = "tegra-pcie",
 815         .id             = 0,
 816         .resource       = 0,
 817         .num_resources  = 0,
 818         .dev = {
 819                 .platform_data = 0,
 820         },
 821 };
 822
 823 /* board files should fill in platform_data register the devices themselvs.
 824  * See board-harmony.c for an example
 825  */
 826 struct platform_device tegra_sdhci_device1 = {
 827         .name           = "sdhci-tegra",
 828         .id             = 0,
 829         .resource       = sdhci_resource1,
 830         .num_resources  = ARRAY_SIZE(sdhci_resource1),
 831 };
 832
 833 struct platform_device tegra_sdhci_device2 = {
 834         .name           = "sdhci-tegra",
 835         .id             = 1,
 836         .resource       = sdhci_resource2,
 837         .num_resources  = ARRAY_SIZE(sdhci_resource2),
 838 };
 839
 840 struct platform_device tegra_sdhci_device3 = {
 841         .name           = "sdhci-tegra",
 842         .id             = 2,
 843         .resource       = sdhci_resource3,
 844         .num_resources  = ARRAY_SIZE(sdhci_resource3),
 845 };
 846
 847 struct platform_device tegra_sdhci_device4 = {
 848         .name           = "sdhci-tegra",
 849         .id             = 3,
 850         .resource       = sdhci_resource4,
 851         .num_resources  = ARRAY_SIZE(sdhci_resource4),
 852 };
 853
 854 static struct resource tegra_usb1_resources[] = {
 855         [0] = {
 856                 .start  = TEGRA_USB_BASE,
 857                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
 858                 .flags  = IORESOURCE_MEM,
 859         },
 860         [1] = {
 861                 .start  = INT_USB,
 862                 .end    = INT_USB,
 863                 .flags  = IORESOURCE_IRQ,
 864         },
 865 };
 866
 867 static struct resource tegra_usb2_resources[] = {
 868         [0] = {
 869                 .start  = TEGRA_USB2_BASE,
 870                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
 871                 .flags  = IORESOURCE_MEM,
 872         },
 873         [1] = {
 874                 .start  = INT_USB2,
 875                 .end    = INT_USB2,
 876                 .flags  = IORESOURCE_IRQ,
 877         },
 878 };
 879
 880 static struct resource tegra_usb3_resources[] = {
 881         [0] = {
 882                 .start  = TEGRA_USB3_BASE,
 883                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
 884                 .flags  = IORESOURCE_MEM,
 885         },
 886         [1] = {
 887                 .start  = INT_USB3,
 888                 .end    = INT_USB3,
 889                 .flags  = IORESOURCE_IRQ,
 890         },
 891 };
 892
 893 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
 894 static struct resource tegra_xusb_resources[] = {
 895         [0] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_HOST_BASE, TEGRA_XUSB_HOST_SIZE,
 896                         "host"),
 897         [1] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_FPCI_BASE, TEGRA_XUSB_FPCI_SIZE,
 898                         "fpci"),
 899         [2] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_IPFS_BASE, TEGRA_XUSB_IPFS_SIZE,
 900                         "ipfs"),
 901         [3] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_PADCTL_BASE,
 902                         TEGRA_XUSB_PADCTL_SIZE, "padctl"),
 903         [4] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_INT, "host"),
 904         [5] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_SMI, "host-smi"),
 905         [6] = DEFINE_RES_IRQ_NAMED(INT_XUSB_PADCTL, "padctl"),
 906         [7] = DEFINE_RES_IRQ_NAMED(INT_USB3, "usb3"),
 907         [8] = DEFINE_RES_IRQ_NAMED(INT_USB2, "usb2"),
 908 };
 909
 910 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
 911
 912 struct platform_device tegra_xhci_device = {
 913         .name = "tegra-xhci",
 914         .id = -1,
 915         .dev = {
 916                 .dma_mask = &tegra_xusb_dmamask,
 917                 .coherent_dma_mask = DMA_BIT_MASK(64),
 918         },
 919         .resource = tegra_xusb_resources,
 920         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
 921 };
 922 #endif
 923
 924 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(64);
 925
 926 struct platform_device tegra_ehci1_device = {
 927         .name   = "tegra-ehci",
 928         .id     = 0,
 929         .dev    = {
 930                 .dma_mask       = &tegra_ehci_dmamask,
 931                 .coherent_dma_mask = DMA_BIT_MASK(64),
 932         },
 933         .resource = tegra_usb1_resources,
 934         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
 935 };
 936
 937 struct platform_device tegra_ehci2_device = {
 938         .name   = "tegra-ehci",
 939         .id     = 1,
 940         .dev    = {
 941                 .dma_mask       = &tegra_ehci_dmamask,
 942                 .coherent_dma_mask = DMA_BIT_MASK(64),
 943         },
 944         .resource = tegra_usb2_resources,
 945         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
 946 };
 947
 948 struct platform_device tegra_ehci3_device = {
 949         .name   = "tegra-ehci",
 950         .id     = 2,
 951         .dev    = {
 952                 .dma_mask       = &tegra_ehci_dmamask,
 953                 .coherent_dma_mask = DMA_BIT_MASK(64),
 954         },
 955         .resource = tegra_usb3_resources,
 956         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
 957 };
 958
 959 static struct resource tegra_pmu_resources[] = {
 960         [0] = {
 961                 .start  = INT_CPU0_PMU_INTR,
 962                 .end    = INT_CPU0_PMU_INTR,
 963                 .flags  = IORESOURCE_IRQ,
 964         },
 965         [1] = {
 966                 .start  = INT_CPU1_PMU_INTR,
 967                 .end    = INT_CPU1_PMU_INTR,
 968                 .flags  = IORESOURCE_IRQ,
 969         },
 970 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 971         [2] = {
 972                 .start  = INT_CPU2_PMU_INTR,
 973                 .end    = INT_CPU2_PMU_INTR,
 974                 .flags  = IORESOURCE_IRQ,
 975         },
 976         [3] = {
 977                 .start  = INT_CPU3_PMU_INTR,
 978                 .end    = INT_CPU3_PMU_INTR,
 979                 .flags  = IORESOURCE_IRQ,
 980         },
 981 #endif
 982 };
 983
 984 struct platform_device tegra_pmu_device = {
 985         .name           = "arm-pmu",
 986         .id             = -1,
 987         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
 988         .resource       = tegra_pmu_resources,
 989 };
 990
 991 static struct resource tegra_uarta_resources[] = {
 992         [0] = {
 993                 .start  = TEGRA_UARTA_BASE,
 994                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
 995                 .flags  = IORESOURCE_MEM,
 996         },
 997         [1] = {
 998                 .start  = INT_UARTA,
 999                 .end    = INT_UARTA,
1000                 .flags  = IORESOURCE_IRQ,
1001         },
1002 };
1003
1004 static struct resource tegra_uartb_resources[] = {
1005         [0] = {
1006                 .start  = TEGRA_UARTB_BASE,
1007                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1008                 .flags  = IORESOURCE_MEM,
1009         },
1010         [1] = {
1011                 .start  = INT_UARTB,
1012                 .end    = INT_UARTB,
1013                 .flags  = IORESOURCE_IRQ,
1014         },
1015 };
1016
1017 static struct resource tegra_uartc_resources[] = {
1018         [0] = {
1019                 .start  = TEGRA_UARTC_BASE,
1020                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1021                 .flags  = IORESOURCE_MEM,
1022         },
1023         [1] = {
1024                 .start  = INT_UARTC,
1025                 .end    = INT_UARTC,
1026                 .flags  = IORESOURCE_IRQ,
1027         },
1028 };
1029
1030 static struct resource tegra_uartd_resources[] = {
1031         [0] = {
1032                 .start  = TEGRA_UARTD_BASE,
1033                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1034                 .flags  = IORESOURCE_MEM,
1035         },
1036         [1] = {
1037                 .start  = INT_UARTD,
1038                 .end    = INT_UARTD,
1039                 .flags  = IORESOURCE_IRQ,
1040         },
1041 };
1042
1043 static struct resource tegra_uarte_resources[] = {
1044         [0] = {
1045                 .start  = TEGRA_UARTE_BASE,
1046                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1047                 .flags  = IORESOURCE_MEM,
1048         },
1049         [1] = {
1050                 .start  = INT_UARTE,
1051                 .end    = INT_UARTE,
1052                 .flags  = IORESOURCE_IRQ,
1053         },
1054 };
1055
1056 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
1057 #define UART_DMA_BIT_MASK DMA_BIT_MASK(64)
1058 #else
1059 #define UART_DMA_BIT_MASK DMA_BIT_MASK(32)
1060 #endif
1061
1062 struct platform_device tegra_uarta_device = {
1063         .name   = "serial-tegra",
1064         .id     = 0,
1065         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1066         .resource       = tegra_uarta_resources,
1067         .dev    = {
1068                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1069         },
1070 };
1071
1072 struct platform_device tegra_uartb_device = {
1073         .name   = "serial-tegra",
1074         .id     = 1,
1075         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1076         .resource       = tegra_uartb_resources,
1077         .dev    = {
1078                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1079         },
1080 };
1081
1082 struct platform_device tegra_uartc_device = {
1083         .name   = "serial-tegra",
1084         .id     = 2,
1085         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1086         .resource       = tegra_uartc_resources,
1087         .dev    = {
1088                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1089         },
1090 };
1091
1092 struct platform_device tegra_uartd_device = {
1093         .name   = "serial-tegra",
1094         .id     = 3,
1095         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1096         .resource       = tegra_uartd_resources,
1097         .dev    = {
1098                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1099         },
1100 };
1101
1102 struct platform_device tegra_uarte_device = {
1103         .name   = "serial-tegra",
1104         .id     = 4,
1105         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1106         .resource       = tegra_uarte_resources,
1107         .dev    = {
1108                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1109         },
1110 };
1111
1112 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1113         {
1114                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1115                 .mapbase        = TEGRA_UARTA_BASE,
1116                 .irq            = INT_UARTA,
1117                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1118                 .type           = PORT_TEGRA,
1119                 .iotype         = UPIO_MEM,
1120                 .regshift       = 2,
1121         },
1122         {
1123                 .flags          = 0,
1124         },
1125 };
1126
1127 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1128         {
1129                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1130                 .mapbase        = TEGRA_UARTB_BASE,
1131                 .irq            = INT_UARTB,
1132                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1133                 .type           = PORT_TEGRA,
1134                 .iotype         = UPIO_MEM,
1135                 .regshift       = 2,
1136         },
1137         {
1138                 .flags          = 0,
1139         },
1140 };
1141
1142 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1143         {
1144                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1145                 .mapbase        = TEGRA_UARTC_BASE,
1146                 .irq            = INT_UARTC,
1147                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1148                 .type           = PORT_TEGRA,
1149                 .iotype         = UPIO_MEM,
1150                 .regshift       = 2,
1151         },
1152         {
1153                 .flags          = 0,
1154         },
1155 };
1156
1157 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1158         {
1159                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1160                 .mapbase        = TEGRA_UARTD_BASE,
1161                 .irq            = INT_UARTD,
1162                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1163                 .type           = PORT_TEGRA,
1164                 .iotype         = UPIO_MEM,
1165                 .regshift       = 2,
1166         },
1167         {
1168                 .flags          = 0,
1169         },
1170 };
1171
1172 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1173 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1174         {
1175                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1176                 .mapbase        = TEGRA_UARTE_BASE,
1177                 .irq            = INT_UARTE,
1178                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1179                 .type           = PORT_TEGRA,
1180                 .iotype         = UPIO_MEM,
1181                 .regshift       = 2,
1182         },
1183         {
1184                 .flags          = 0,
1185         },
1186 };
1187 #endif
1188
1189 struct platform_device debug_uarta_device = {
1190         .name = "serial8250",
1191         .id = PLAT8250_DEV_PLATFORM,
1192         .dev = {
1193                 .platform_data = debug_uarta_platform_data,
1194         },
1195 };
1196
1197 struct platform_device debug_uartb_device = {
1198         .name = "serial8250",
1199         .id = PLAT8250_DEV_PLATFORM,
1200         .dev = {
1201                 .platform_data = debug_uartb_platform_data,
1202         },
1203 };
1204
1205 struct platform_device debug_uartc_device = {
1206         .name = "serial8250",
1207         .id = PLAT8250_DEV_PLATFORM,
1208         .dev = {
1209                 .platform_data = debug_uartc_platform_data,
1210         },
1211 };
1212
1213 struct platform_device debug_uartd_device = {
1214         .name = "serial8250",
1215         .id = PLAT8250_DEV_PLATFORM,
1216         .dev = {
1217                 .platform_data = debug_uartd_platform_data,
1218         },
1219 };
1220
1221 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1222 struct platform_device debug_uarte_device = {
1223         .name = "serial8250",
1224         .id = PLAT8250_DEV_PLATFORM,
1225         .dev = {
1226                 .platform_data = debug_uarte_platform_data,
1227         },
1228 };
1229 #endif
1230
1231 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1232 static struct resource i2s_resource1[] = {
1233         [0] = {
1234                 .start  = INT_I2S1,
1235                 .end    = INT_I2S1,
1236                 .flags  = IORESOURCE_IRQ
1237         },
1238         [1] = {
1239                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1240                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1241                 .flags  = IORESOURCE_DMA
1242         },
1243         [2] = {
1244                 .start  = TEGRA_I2S1_BASE,
1245                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1246                 .flags  = IORESOURCE_MEM
1247         }
1248 };
1249
1250 struct platform_device tegra_i2s_device1 = {
1251         .name           = "tegra20-i2s",
1252         .id             = 0,
1253         .resource       = i2s_resource1,
1254         .num_resources  = ARRAY_SIZE(i2s_resource1),
1255 };
1256
1257 static struct resource i2s_resource2[] = {
1258         [0] = {
1259                 .start  = INT_I2S2,
1260                 .end    = INT_I2S2,
1261                 .flags  = IORESOURCE_IRQ
1262         },
1263         [1] = {
1264                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1265                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1266                 .flags  = IORESOURCE_DMA
1267         },
1268         [2] = {
1269                 .start  = TEGRA_I2S2_BASE,
1270                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1271                 .flags  = IORESOURCE_MEM
1272         }
1273 };
1274
1275 struct platform_device tegra_i2s_device2 = {
1276         .name           = "tegra20-i2s",
1277         .id             = 1,
1278         .resource       = i2s_resource2,
1279         .num_resources  = ARRAY_SIZE(i2s_resource2),
1280 };
1281 #else
1282 static struct resource i2s_resource0[] = {
1283         [0] = {
1284                 .start  = TEGRA_I2S0_BASE,
1285                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1286                 .flags  = IORESOURCE_MEM
1287         }
1288 };
1289
1290 struct platform_device tegra_i2s_device0 = {
1291         .name           = "tegra30-i2s",
1292         .id             = 0,
1293         .resource       = i2s_resource0,
1294         .num_resources  = ARRAY_SIZE(i2s_resource0),
1295 };
1296
1297 static struct resource i2s_resource1[] = {
1298         [0] = {
1299                 .start  = TEGRA_I2S1_BASE,
1300                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1301                 .flags  = IORESOURCE_MEM
1302         }
1303 };
1304
1305 struct platform_device tegra_i2s_device1 = {
1306         .name           = "tegra30-i2s",
1307         .id             = 1,
1308         .resource       = i2s_resource1,
1309         .num_resources  = ARRAY_SIZE(i2s_resource1),
1310 };
1311
1312 static struct resource i2s_resource2[] = {
1313         [0] = {
1314                 .start  = TEGRA_I2S2_BASE,
1315                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1316                 .flags  = IORESOURCE_MEM
1317         }
1318 };
1319
1320 struct platform_device tegra_i2s_device2 = {
1321         .name           = "tegra30-i2s",
1322         .id             = 2,
1323         .resource       = i2s_resource2,
1324         .num_resources  = ARRAY_SIZE(i2s_resource2),
1325 };
1326
1327 static struct resource i2s_resource3[] = {
1328         [0] = {
1329                 .start  = TEGRA_I2S3_BASE,
1330                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1331                 .flags  = IORESOURCE_MEM
1332         }
1333 };
1334
1335 struct platform_device tegra_i2s_device3 = {
1336         .name           = "tegra30-i2s",
1337         .id             = 3,
1338         .resource       = i2s_resource3,
1339         .num_resources  = ARRAY_SIZE(i2s_resource3),
1340 };
1341
1342 static struct resource i2s_resource4[] = {
1343         [0] = {
1344                 .start  = TEGRA_I2S4_BASE,
1345                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1346                 .flags  = IORESOURCE_MEM
1347         }
1348 };
1349
1350 struct platform_device tegra_i2s_device4 = {
1351         .name           = "tegra30-i2s",
1352         .id             = 4,
1353         .resource       = i2s_resource4,
1354         .num_resources  = ARRAY_SIZE(i2s_resource4),
1355 };
1356 #endif
1357
1358 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1359 static struct resource spdif_resource[] = {
1360         [0] = {
1361                 .start  = INT_SPDIF,
1362                 .end    = INT_SPDIF,
1363                 .flags  = IORESOURCE_IRQ
1364         },
1365         [1] = {
1366                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1367                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1368                 .flags  = IORESOURCE_DMA
1369         },
1370         [2] = {
1371                 .start  = TEGRA_SPDIF_BASE,
1372                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1373                 .flags  = IORESOURCE_MEM
1374         }
1375 };
1376
1377 struct platform_device tegra_spdif_device = {
1378         .name           = "tegra20-spdif",
1379         .id             = -1,
1380         .resource       = spdif_resource,
1381         .num_resources  = ARRAY_SIZE(spdif_resource),
1382 };
1383 #else
1384 static struct resource spdif_resource[] = {
1385         [0] = {
1386                 .start  = TEGRA_SPDIF_BASE,
1387                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1388                 .flags  = IORESOURCE_MEM
1389         }
1390 };
1391
1392 struct platform_device tegra_spdif_device = {
1393         .name           = "tegra30-spdif",
1394         .id             = -1,
1395         .resource       = spdif_resource,
1396         .num_resources  = ARRAY_SIZE(spdif_resource),
1397 };
1398 #endif
1399
1400 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1401 static struct resource ahub_resource[] = {
1402         [0] = {
1403                 .start  = TEGRA_APBIF0_BASE,
1404                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1405                 .flags  = IORESOURCE_MEM
1406         },
1407         [1] = {
1408                 .start  = TEGRA_AHUB_BASE,
1409                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1410                 .flags  = IORESOURCE_MEM
1411         }
1412 };
1413
1414 struct platform_device tegra_ahub_device = {
1415         .name   = "tegra30-ahub",
1416         .id     = -1,
1417         .resource       = ahub_resource,
1418         .num_resources  = ARRAY_SIZE(ahub_resource),
1419 };
1420
1421 static struct resource dam_resource0[] = {
1422         [0] = {
1423                 .start = TEGRA_DAM0_BASE,
1424                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1425                 .flags = IORESOURCE_MEM
1426         }
1427 };
1428
1429 struct platform_device tegra_dam_device0 = {
1430         .name = "tegra30-dam",
1431         .id = 0,
1432         .resource      = dam_resource0,
1433         .num_resources = ARRAY_SIZE(dam_resource0),
1434 };
1435
1436 static struct resource dam_resource1[] = {
1437         [0] = {
1438                 .start = TEGRA_DAM1_BASE,
1439                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1440                 .flags = IORESOURCE_MEM
1441         }
1442 };
1443
1444 struct platform_device tegra_dam_device1 = {
1445         .name = "tegra30-dam",
1446         .id = 1,
1447         .resource      = dam_resource1,
1448         .num_resources = ARRAY_SIZE(dam_resource1),
1449 };
1450
1451 static struct resource dam_resource2[] = {
1452         [0] = {
1453                 .start = TEGRA_DAM2_BASE,
1454                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1455                 .flags = IORESOURCE_MEM
1456         }
1457 };
1458
1459 struct platform_device tegra_dam_device2 = {
1460         .name = "tegra30-dam",
1461         .id = 2,
1462         .resource      = dam_resource2,
1463         .num_resources = ARRAY_SIZE(dam_resource2),
1464 };
1465
1466 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1467 static struct resource hda_platform_resources[] = {
1468         [0] = {
1469                 .start  = TEGRA_HDA_BASE,
1470                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1471                 .flags  = IORESOURCE_MEM
1472         },
1473         [1] = {
1474                 .start  = INT_HDA,
1475                 .end    = INT_HDA,
1476                 .flags  = IORESOURCE_IRQ
1477         },
1478 };
1479
1480 struct platform_device tegra_hda_device = {
1481         .name           = "tegra30-hda",
1482         .id             = -1,
1483         .dev = {
1484                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1485                 .dma_mask               = &tegra_hda_dma_mask,
1486         },
1487         .resource       = hda_platform_resources,
1488         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1489 };
1490 #endif
1491
1492 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1493 static struct resource dmic_resource0[] = {
1494         [0] = {
1495                 .start = TEGRA_DMIC0_BASE,
1496                 .end   = TEGRA_DMIC0_BASE + TEGRA_DMIC0_SIZE - 1,
1497                 .flags = IORESOURCE_MEM
1498         }
1499 };
1500
1501 struct platform_device tegra_dmic_device0 = {
1502         .name = "tegra-dmic",
1503         .id = 0,
1504         .resource      = dmic_resource0,
1505         .num_resources = ARRAY_SIZE(dmic_resource0),
1506 };
1507
1508 static struct resource dmic_resource1[] = {
1509         [0] = {
1510                 .start = TEGRA_DMIC1_BASE,
1511                 .end   = TEGRA_DMIC1_BASE + TEGRA_DMIC1_SIZE - 1,
1512                 .flags = IORESOURCE_MEM
1513         }
1514 };
1515
1516 struct platform_device tegra_dmic_device1 = {
1517         .name = "tegra-dmic",
1518         .id = 1,
1519         .resource      = dmic_resource1,
1520         .num_resources = ARRAY_SIZE(dmic_resource1),
1521 };
1522 #endif
1523
1524 struct platform_device spdif_dit_device = {
1525         .name = "spdif-dit",
1526         .id = 0,
1527 };
1528
1529 struct platform_device bluetooth_dit_device = {
1530         .name = "spdif-dit",
1531         .id = 1,
1532 };
1533
1534 struct platform_device baseband_dit_device = {
1535         .name = "spdif-dit",
1536         .id = 2,
1537 };
1538
1539 struct platform_device tegra_pcm_device = {
1540         .name = "tegra-pcm-audio",
1541         .id = -1,
1542 };
1543
1544 struct platform_device tegra_tdm_pcm_device = {
1545         .name = "tegra-tdm-pcm-audio",
1546         .id = -1,
1547 };
1548
1549 struct platform_device tegra_offload_device = {
1550         .name = "tegra-offload",
1551         .id = -1,
1552 };
1553
1554 struct platform_device tegra30_avp_audio_device = {
1555         .name = "tegra30-avp-audio",
1556         .id = -1,
1557 };
1558
1559 static struct resource w1_resources[] = {
1560         [0] = {
1561                 .start = INT_OWR,
1562                 .end   = INT_OWR,
1563                 .flags = IORESOURCE_IRQ
1564         },
1565         [1] = {
1566                 .start = TEGRA_OWR_BASE,
1567                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1568                 .flags = IORESOURCE_MEM
1569         }
1570 };
1571
1572 struct platform_device tegra_w1_device = {
1573         .name          = "tegra_w1",
1574         .id            = -1,
1575         .resource      = w1_resources,
1576         .num_resources = ARRAY_SIZE(w1_resources),
1577 };
1578
1579 static struct resource tegra_udc_resources[] = {
1580         [0] = {
1581                 .start  = TEGRA_USB_BASE,
1582                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1583                 .flags  = IORESOURCE_MEM,
1584         },
1585         [1] = {
1586                 .start  = INT_USB,
1587                 .end    = INT_USB,
1588                 .flags  = IORESOURCE_IRQ,
1589         },
1590 };
1591
1592 static u64 tegra_udc_dmamask = DMA_BIT_MASK(64);
1593
1594 struct platform_device tegra_udc_device = {
1595         .name   = "tegra-udc",
1596         .id     = 0,
1597         .dev    = {
1598                 .dma_mask       = &tegra_udc_dmamask,
1599                 .coherent_dma_mask = DMA_BIT_MASK(64),
1600         },
1601         .resource = tegra_udc_resources,
1602         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1603 };
1604
1605 static struct resource tegra_otg_resources[] = {
1606         [0] = {
1607                 .start  = TEGRA_USB_BASE,
1608                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1609                 .flags  = IORESOURCE_MEM,
1610         },
1611         [1] = {
1612                 .start  = INT_USB,
1613                 .end    = INT_USB,
1614                 .flags  = IORESOURCE_IRQ,
1615         },
1616 };
1617
1618 struct platform_device tegra_otg_device = {
1619         .name           = "tegra-otg",
1620         .id             = -1,
1621         .resource       = tegra_otg_resources,
1622         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1623 };
1624
1625 #ifdef CONFIG_SATA_AHCI_TEGRA
1626 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(64);
1627
1628 static struct resource tegra_sata_resources[] = {
1629         [0] = {
1630                 .start = TEGRA_SATA_BAR5_BASE,
1631                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1632                 .flags = IORESOURCE_MEM,
1633         },
1634         [1] = {
1635                 .start = TEGRA_SATA_CONFIG_BASE,
1636                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1637                 .flags = IORESOURCE_MEM,
1638         },
1639         [2] = {
1640                 .start = INT_SATA_CTL,
1641                 .end = INT_SATA_CTL,
1642                 .flags = IORESOURCE_IRQ,
1643         },
1644 };
1645
1646 struct platform_device tegra_sata_device = {
1647         .name   = "tegra-sata",
1648         .id     = 0,
1649         .dev    = {
1650                 .coherent_dma_mask = DMA_BIT_MASK(64),
1651                 .dma_mask = &tegra_sata_dma_mask,
1652         },
1653         .resource = tegra_sata_resources,
1654         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1655 };
1656 #endif
1657
1658 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1659 static struct resource das_resource[] = {
1660         [0] = {
1661                 .start  = TEGRA_APB_MISC_DAS_BASE,
1662                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1663                 .flags  = IORESOURCE_MEM
1664         }
1665 };
1666
1667 struct platform_device tegra_das_device = {
1668         .name           = "tegra20-das",
1669         .id             = -1,
1670         .resource       = das_resource,
1671         .num_resources  = ARRAY_SIZE(das_resource),
1672 };
1673 #endif
1674
1675 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1676 static struct resource tegra_gart_resources[] = {
1677         [0] = {
1678                 .name   = "mc",
1679                 .flags  = IORESOURCE_MEM,
1680                 .start  = TEGRA_MC_BASE,
1681                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1682         },
1683         [1] = {
1684                 .name   = "gart",
1685                 .flags  = IORESOURCE_MEM,
1686                 .start  = TEGRA_GART_BASE,
1687                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1688         }
1689 };
1690
1691 struct platform_device tegra_gart_device = {
1692         .name           = "tegra_gart",
1693         .id             = -1,
1694         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1695         .resource       = tegra_gart_resources
1696 };
1697 #endif
1698
1699 #if defined(CONFIG_TEGRA_IOMMU_SMMU)
1700 static struct resource tegra_smmu_resources[] = {
1701         {
1702                 .name   = "mc",
1703                 .flags  = IORESOURCE_MEM,
1704                 .start  = TEGRA_MC_BASE,
1705                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1706         },
1707         {
1708                 .name   = "ahbarb",
1709                 .flags  = IORESOURCE_MEM,
1710                 .start  = TEGRA_AHB_ARB_BASE,
1711                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1712         },
1713 };
1714
1715 struct platform_device tegra_smmu_device = {
1716         .name           = "tegra_smmu",
1717         .id             = -1,
1718         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1719         .resource       = tegra_smmu_resources
1720 };
1721
1722 static struct resource tegra_smmu[] = {
1723         [0] = {
1724                 .start  = TEGRA_SMMU_BASE,
1725                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1726         },
1727 };
1728
1729 struct resource *tegra_smmu_window(int wnum)
1730 {
1731         return &tegra_smmu[wnum];
1732 }
1733
1734 int tegra_smmu_window_count(void)
1735 {
1736         return ARRAY_SIZE(tegra_smmu);
1737 }
1738
1739 static struct iommu_linear_map tegra_fb_linear_map[16]; /* Terminated with 0 */
1740
1741 #define LINEAR_MAP_ADD(n) \
1742 do { \
1743         if (n##_start && n##_size) { \
1744                 map[i].start = n##_start; \
1745                 map[i++].size = n##_size; \
1746         } \
1747 } while (0)
1748
1749 void tegra_fb_linear_set(struct iommu_linear_map *map)
1750 {
1751         int i = 0;
1752
1753         map = tegra_fb_linear_map;
1754
1755         LINEAR_MAP_ADD(tegra_fb);
1756         LINEAR_MAP_ADD(tegra_fb2);
1757         LINEAR_MAP_ADD(tegra_bootloader_fb);
1758         LINEAR_MAP_ADD(tegra_bootloader_fb2);
1759 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1760         LINEAR_MAP_ADD(tegra_vpr);
1761         LINEAR_MAP_ADD(tegra_carveout);
1762 #endif
1763 }
1764
1765 #ifdef CONFIG_CMA
1766 void carveout_linear_set(struct device *cma_dev)
1767 {
1768         struct dma_contiguous_stats stats;
1769         struct iommu_linear_map *map = &tegra_fb_linear_map[0];
1770
1771         if (dma_get_contiguous_stats(cma_dev, &stats))
1772                 return;
1773
1774         /* get the free slot at end and add carveout entry */
1775         while (map && map->size)
1776                 map++;
1777         map->start = stats.base;
1778         map->size = stats.size;
1779 }
1780 #endif
1781
1782 struct swgid_fixup {
1783         const char * const name;
1784         u64 swgids;
1785         struct iommu_linear_map *linear_map;
1786 };
1787
1788 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1789 #define DUMMY_DEV_NAME "dummy_dev"
1790 #define DUMMY_DEV_MAX_NAME_SIZE 100
1791 static char dummy_name[DUMMY_DEV_MAX_NAME_SIZE] = DUMMY_DEV_NAME;
1792 #endif
1793
1794 /*
1795  * FIXME: They should have a DT entry with swgroup IDs.
1796  */
1797 struct swgid_fixup tegra_swgid_fixup[] = {
1798         { .name = "540c0000.epp",       .swgids = SWGID(EPP), },
1799         { .name = "epp",        .swgids = SWGID(EPP), },
1800         { .name = "54200000.dc",        .swgids = SWGID(DC),
1801           .linear_map = tegra_fb_linear_map, },
1802         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
1803         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
1804         { .name = "gr2d",       .swgids = SWGID(G2), },
1805         { .name = "gr3d",       .swgids = SWGID(NV) | SWGID(NV2), },
1806         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |      \
1807           SWGID(EPP) | SWGID(HDA), },
1808         { .name = "isp",        .swgids = SWGID(ISP), },
1809         { .name = "max77660",   .swgids = SWGID(PPCS), },
1810         { .name = "max8831",    .swgids = SWGID(PPCS), },
1811         { .name = "msenc",      .swgids = SWGID(MSENC), },
1812         { .name = "mpe",        .swgids = SWGID(MPE), },
1813         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
1814         { .name = "nvavp",      .swgids = SWGID(AVPC), },
1815         { .name = "sdhci-tegra.0",      .swgids = SWGID(PPCS1) },
1816         { .name = "sdhci-tegra.1",      .swgids = SWGID(PPCS1) },
1817         { .name = "sdhci-tegra.2",      .swgids = SWGID(PPCS1) },
1818         { .name = "sdhci-tegra.3",      .swgids = SWGID(PPCS1) },
1819         { .name = "serial8250", .swgids = SWGID(PPCS), },
1820         { .name = "serial-tegra",      .swgids = SWGID(PPCS), },
1821         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
1822         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
1823         { .name = "tegra11-se", .swgids = SWGID(PPCS), },
1824         { .name = "tegra11-spi",        .swgids = SWGID(PPCS), },
1825         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
1826         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
1827         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
1828         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
1829         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
1830         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
1831         { .name = "tegra30-avp-audio",  .swgids = SWGID(AVPC), },
1832         { .name = "tegradc.0", .swgids = SWGID(DC),
1833           .linear_map = tegra_fb_linear_map},
1834         { .name = "tegradc.1", .swgids = SWGID(DCB), },
1835         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
1836         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
1837         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
1838         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
1839         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
1840         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
1841         { .name = "tegra-otg",  .swgids = SWGID(PPCS), },
1842         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
1843         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
1844         { .name = "tegra-sata", .swgids = SWGID(SATA), },
1845         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
1846         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
1847         { .name = "tegra-tzram",        .swgids = SWGID(VDE), },
1848         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
1849         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
1850         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
1851         { .name = "tsec",       .swgids = SWGID(TSEC), },
1852         { .name = "vi", .swgids = SWGID(VI), },
1853         { .name = "therm_est",  .swgids = SWGID(PPCS), },
1854         { .name = "tegra-xhci", .swgids = SWGID(XUSB_HOST), },
1855 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1856         { .name = dummy_name,   .swgids = SWGID(PPCS) },
1857 #endif
1858         {},
1859 };
1860
1861 struct swgid_fixup tegra_swgid_fixup_t124[] = {
1862         { .name = "54200000.dc",        .swgids = SWGID(DC), },
1863         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
1864         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
1865         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |
1866           SWGID(EPP) | SWGID(HDA), },
1867         { .name = "isp",        .swgids = SWGID(ISP2) | SWGID(ISP2B), },
1868         { .name = "max77660",   .swgids = SWGID(PPCS), },
1869         { .name = "max8831",    .swgids = SWGID(PPCS), },
1870         { .name = "msenc",      .swgids = SWGID(MSENC), },
1871         { .name = "mpe",        .swgids = SWGID(MPE), },
1872         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
1873         { .name = "nvavp",      .swgids = SWGID(AVPC) | SWGID(A9AVP), },
1874         { .name = "serial8250", .swgids = SWGID(PPCS), },
1875         { .name = "serial-tegra",       .swgids = SWGID(PPCS), },
1876         { .name = "dtv",        .swgids = SWGID(PPCS), },
1877         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
1878         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
1879         { .name = "tegra12-se", .swgids = SWGID(PPCS), },
1880         { .name = "spi-tegra114",       .swgids = SWGID(PPCS), },
1881         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
1882         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
1883         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
1884         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
1885         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
1886         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
1887         { .name = "tegra30-avp-audio",  .swgids = SWGID(AVPC) | SWGID(A9AVP), },
1888         { .name = "tegradc.0", .swgids = SWGID(DC) | SWGID(DC12),
1889           .linear_map = tegra_fb_linear_map, },
1890         { .name = "tegradc.1", .swgids = SWGID(DCB),
1891           .linear_map = tegra_fb_linear_map, },
1892         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
1893         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
1894         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
1895         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
1896         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
1897         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
1898         /*
1899          * PPCS1 selection for USB2 needs AHB_ARBC register program
1900          * in warm boot and cold boot paths in BL as it needs
1901          * secure write.
1902          */
1903         { .name = "tegra-otg",  .swgids = SWGID(PPCS1), },
1904         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
1905         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
1906         { .name = "tegra-sata", .swgids = SWGID(SATA2), },
1907         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
1908         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
1909         { .name = "tegra-tzram",        .swgids = SWGID(PPCS), },
1910         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
1911         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
1912         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
1913         { .name = "tsec",       .swgids = SWGID(TSEC), },
1914         /* vic must be before vi to prevent incorrect matching */
1915         { .name = "vic",        .swgids = SWGID(VIC), },
1916         { .name = "vi", .swgids = SWGID(VI), },
1917         { .name = "therm_est",  .swgids = SWGID(PPCS), },
1918         { .name = "gk20a",      .swgids = SWGID(GPU) | SWGID(GPUB), },
1919         { .name = "tegra124-apbdma",    .swgids = SWGID(PPCS), },
1920         { .name = "tegra-nor",  .swgids = SWGID(PPCS), },
1921 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1922         { .name = dummy_name,   .swgids = SWGID(PPCS) },
1923 #endif
1924         { .name = "tegra-xhci", .swgids = SWGID(XUSB_HOST), },
1925         {},
1926 };
1927
1928 u64 tegra_smmu_fixup_swgids(struct device *dev, struct iommu_linear_map **map)
1929 {
1930         const char *s;
1931         struct swgid_fixup *table;
1932
1933         if (!dev)
1934                 return 0;
1935
1936         switch (tegra_get_chipid()) {
1937         case TEGRA_CHIPID_TEGRA12:
1938         case TEGRA_CHIPID_TEGRA13:
1939                 table = tegra_swgid_fixup_t124;
1940                 break;
1941         default:
1942                 table = tegra_swgid_fixup;
1943                 break;
1944         }
1945
1946         while ((s = table->name) != NULL) {
1947                 if (!strncmp(s, dev_name(dev), strlen(s))) {
1948                         if (map)
1949                                 *map = table->linear_map;
1950
1951                         return table->swgids;
1952                 }
1953                 table++;
1954         }
1955
1956         return 0;
1957 }
1958
1959 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1960
1961 struct tegra_iommu_mapping {
1962         dma_addr_t base;
1963         size_t size;
1964         struct dma_iommu_mapping *map;
1965 };
1966
1967 static struct tegra_iommu_mapping smmu_default_map[] = {
1968         [SYSTEM_DEFAULT] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1969         [SYSTEM_PROTECTED] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1970         [PPCS1_ASID] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1971         [SYSTEM_DC] = {0x10000, (u32)~0},
1972         [SYSTEM_DCB] = {0x10000, (u32)~0},
1973         /* Non-zero base to account for gk20a driver's assumptions */
1974         [SYSTEM_GK20A] = {0x100000, (u32)~0},
1975         [SDMMC1A_ASID] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1976         [SDMMC2A_ASID] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1977         [SDMMC3A_ASID] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1978         [SDMMC4A_ASID] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
1979 };
1980
1981 static void tegra_smmu_map_init(struct platform_device *pdev)
1982 {
1983         int i;
1984
1985         for (i = 0; i < ARRAY_SIZE(smmu_default_map); i++) {
1986                 struct tegra_iommu_mapping *m = &smmu_default_map[i];
1987                 struct dma_iommu_mapping *map;
1988                 int order = 0;
1989
1990                 if (IS_ENABLED(CONFIG_TEGRA_ERRATA_1053704))
1991                         order = get_order(SZ_16K);
1992
1993                 map = arm_iommu_create_mapping(&platform_bus_type,
1994                                                m->base, m->size, 0);
1995
1996                 if (IS_ERR(map))
1997                         dev_err(&pdev->dev,
1998                                 "Failed create IOVA map for ASID[%d]\n", i);
1999
2000                 m->map = map;
2001         }
2002 }
2003
2004 void tegra_smmu_map_misc_device(struct device *dev)
2005 {
2006         struct dma_iommu_mapping *map = smmu_default_map[SYSTEM_PROTECTED].map;
2007         if (!strncmp(dummy_name, DUMMY_DEV_NAME, strlen(dummy_name))) {
2008                 strncpy(dummy_name, dev_name(dev),
2009                         DUMMY_DEV_MAX_NAME_SIZE);
2010                 arm_iommu_attach_device(dev, map);
2011                 dev_info(dev, "Mapped the misc device\n");
2012                 return;
2013         }
2014         dev_err(dev, "Can't Map device\n");
2015 }
2016 EXPORT_SYMBOL(tegra_smmu_map_misc_device);
2017
2018 void tegra_smmu_unmap_misc_device(struct device *dev)
2019 {
2020         if (!strncmp(dummy_name, dev_name(dev), strlen(dummy_name))) {
2021                 arm_iommu_detach_device(dev);
2022                 strncpy(dummy_name, DUMMY_DEV_NAME,
2023                         DUMMY_DEV_MAX_NAME_SIZE);
2024                 dev_info(dev, "Un-mapped the misc device\n");
2025                 return;
2026         }
2027         dev_err(dev, "Can't Unmap device\n");
2028 }
2029 EXPORT_SYMBOL(tegra_smmu_unmap_misc_device);
2030
2031 static int _tegra_smmu_get_asid(u64 swgids)
2032 {
2033         if (swgids & SWGID(PPCS))
2034                 return SYSTEM_PROTECTED;
2035 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || \
2036         defined(CONFIG_ARCH_TEGRA_11x_SOC)
2037         if (swgids & SWGID(PPCS1))
2038                 return PPCS1_ASID;
2039 #else
2040         if (swgids & SWGID(PPCS1))
2041                 return SYSTEM_PROTECTED;
2042 #endif
2043
2044         if (swgids & SWGID(GPUB))
2045                 return SYSTEM_GK20A;
2046
2047 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2048         if (swgids & SWGID(DC) ||
2049             swgids & SWGID(DCB))
2050                 return SYSTEM_DC;
2051 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2052         if (swgids & SWGID(DC) ||
2053             swgids & SWGID(DC12))
2054                 return SYSTEM_DC;
2055         if (swgids & SWGID(DCB))
2056                 return SYSTEM_DCB;
2057         if (swgids & SWGID(SDMMC1A))
2058                 return SDMMC1A_ASID;
2059         if (swgids & SWGID(SDMMC2A))
2060                 return SDMMC2A_ASID;
2061         if (swgids & SWGID(SDMMC3A))
2062                 return SDMMC3A_ASID;
2063         if (swgids & SWGID(SDMMC4A))
2064                 return SDMMC4A_ASID;
2065 #endif
2066
2067         return SYSTEM_DEFAULT;
2068 }
2069
2070 int tegra_smmu_get_asid(struct device *dev)
2071 {
2072         u64 swgids = tegra_smmu_fixup_swgids(dev, NULL);
2073         return _tegra_smmu_get_asid(swgids);
2074 }
2075
2076 struct dma_iommu_mapping *tegra_smmu_get_map(struct device *dev, u64 swgids)
2077 {
2078         if (!swgids)
2079                 swgids = tegra_smmu_fixup_swgids(dev, NULL);
2080
2081         if (!swgids)
2082                 return NULL;
2083
2084         return smmu_default_map[_tegra_smmu_get_asid(swgids)].map;
2085 }
2086 #else
2087 static inline void tegra_smmu_map_init(struct platform_device *pdev)
2088 {
2089 }
2090 #endif
2091
2092 static int __init tegra_smmu_init(void)
2093 {
2094         platform_device_register(&tegra_smmu_device);
2095         tegra_smmu_map_init(&tegra_smmu_device);
2096         return 0;
2097 }
2098 postcore_initcall(tegra_smmu_init);
2099 #endif
2100
2101 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2102 #define CLK_RESET_RST_SOURCE    0x0
2103 static struct resource tegra_wdt_resources[] = {
2104         [0] = {
2105                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
2106                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
2107                 .flags  = IORESOURCE_MEM,
2108         },
2109         [1] = {
2110                 .start  = TEGRA_TMR1_BASE,
2111                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
2112                 .flags  = IORESOURCE_MEM,
2113         },
2114         [2] = {
2115                 .start  = TEGRA_PMC_BASE,
2116                 .end    = TEGRA_PMC_BASE + TEGRA_PMC_SIZE - 1,
2117                 .flags  = IORESOURCE_MEM,
2118         },
2119         [3] = {
2120                 .start  = INT_TMR1,
2121                 .end    = INT_TMR1,
2122                 .flags  = IORESOURCE_IRQ,
2123         },
2124 };
2125
2126 struct platform_device tegra_wdt_device = {
2127         .name           = "tegra_wdt",
2128         .id             = -1,
2129         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
2130         .resource       = tegra_wdt_resources,
2131 };
2132 #else
2133 static struct resource tegra_wdt0_resources[] = {
2134         [0] = {
2135                 .start  = TEGRA_WDT0_BASE,
2136                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
2137                 .flags  = IORESOURCE_MEM,
2138         },
2139         [1] = {
2140                 .start  = TEGRA_TMR7_BASE,
2141                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
2142                 .flags  = IORESOURCE_MEM,
2143         },
2144         [2] = {
2145                 .start  = TEGRA_PMC_BASE,
2146                 .end    = TEGRA_PMC_BASE + TEGRA_PMC_SIZE - 1,
2147                 .flags  = IORESOURCE_MEM,
2148         },
2149         [3] = {
2150                 .start  = INT_WDT_CPU,
2151                 .end    = INT_WDT_CPU,
2152                 .flags  = IORESOURCE_IRQ,
2153         },
2154 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
2155         [4] = {
2156                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
2157                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
2158                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
2159                 .flags  = IORESOURCE_MEM,
2160         },
2161 #endif
2162 #if defined(CONFIG_TRUSTED_LITTLE_KERNEL) && \
2163         defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
2164         [5] = {
2165                 .start  = TEGRA_WDT4_BASE,
2166                 .end    = TEGRA_WDT4_BASE + TEGRA_WDT4_SIZE - 1,
2167                 .flags  = IORESOURCE_MEM,
2168         },
2169         [6] = {
2170                 .start  = INT_WDT_AVP,
2171                 .end    = INT_WDT_AVP,
2172                 .flags  = IORESOURCE_IRQ,
2173         },
2174 #endif
2175 #if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \
2176         defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
2177         [5] = {
2178                 .start  = TEGRA_WDT4_BASE,
2179                 .end    = TEGRA_WDT4_BASE + TEGRA_WDT4_SIZE - 1,
2180                 .flags  = IORESOURCE_MEM,
2181         },
2182         [6] = {
2183                 .start  = INT_WDT_AVP,
2184                 .end    = INT_WDT_AVP,
2185                 .flags  = IORESOURCE_IRQ,
2186         },
2187 #endif
2188 };
2189
2190 struct platform_device tegra_wdt0_device = {
2191         .name           = "tegra_wdt",
2192         .id             = 0,
2193         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
2194         .resource       = tegra_wdt0_resources,
2195 };
2196
2197 #endif
2198
2199 static struct tegra_avp_platform_data tegra_avp_pdata = {
2200 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2201         .emc_clk_rate = ULONG_MAX,
2202 #else
2203         .emc_clk_rate = 200000000,
2204 #endif
2205 };
2206
2207 struct resource tegra_nvavp_resources[] = {
2208         [0] = {
2209                 .start  = INT_SHR_SEM_INBOX_IBF,
2210                 .end    = INT_SHR_SEM_INBOX_IBF,
2211                 .flags  = IORESOURCE_IRQ,
2212                 .name   = "mbox_from_nvavp_pending",
2213         },
2214 };
2215
2216 struct platform_device nvavp_device = {
2217         .name           = "nvavp",
2218         .id             = -1,
2219         .resource       = tegra_nvavp_resources,
2220         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
2221         .dev  = {
2222                 .coherent_dma_mask      = 0xffffffffULL,
2223                 .platform_data          = &tegra_avp_pdata,
2224         },
2225 };
2226
2227 static struct resource tegra_avp_resources[] = {
2228         [0] = {
2229                 .start  = INT_SHR_SEM_INBOX_IBF,
2230                 .end    = INT_SHR_SEM_INBOX_IBF,
2231                 .flags  = IORESOURCE_IRQ,
2232                 .name   = "mbox_from_avp_pending",
2233         },
2234 };
2235
2236 struct platform_device tegra_avp_device = {
2237         .name           = "tegra-avp",
2238         .id             = -1,
2239         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
2240         .resource       = tegra_avp_resources,
2241         .dev  = {
2242                 .coherent_dma_mask      = 0xffffffffULL,
2243                 .platform_data          = &tegra_avp_pdata,
2244         },
2245 };
2246
2247 static struct resource tegra_aes_resources[] = {
2248         {
2249                 .start  = TEGRA_VDE_BASE,
2250                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
2251                 .flags  = IORESOURCE_MEM,
2252         },
2253         {
2254                 .start  = TEGRA_BSEA_BASE,
2255                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
2256                 .flags  = IORESOURCE_MEM,
2257         },
2258         {
2259                 .start  = INT_VDE_BSE_V,
2260                 .end    = INT_VDE_BSE_V,
2261                 .flags  = IORESOURCE_IRQ,
2262         },
2263         {
2264                 .start  = INT_VDE_BSE_A,
2265                 .end    = INT_VDE_BSE_A,
2266                 .flags  = IORESOURCE_IRQ,
2267         },
2268 };
2269
2270 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
2271
2272 struct platform_device tegra_aes_device = {
2273         .name           = "tegra-aes",
2274         .id             = -1,
2275         .resource       = tegra_aes_resources,
2276         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
2277         .dev    = {
2278                 .dma_mask = &tegra_aes_dma_mask,
2279                 .coherent_dma_mask = DMA_BIT_MASK(32),
2280         },
2281 };
2282
2283 static struct resource tegra_kbc_resources[] = {
2284         [0] = {
2285                 .start = TEGRA_KBC_BASE,
2286                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
2287                 .flags = IORESOURCE_MEM,
2288         },
2289         [1] = {
2290                 .start = INT_KBC,
2291                 .end   = INT_KBC,
2292                 .flags = IORESOURCE_IRQ,
2293         },
2294 };
2295
2296 struct platform_device tegra_kbc_device = {
2297         .name = "tegra-kbc",
2298         .id = -1,
2299         .resource = tegra_kbc_resources,
2300         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
2301         .dev = {
2302                 .platform_data = 0,
2303         },
2304 };
2305
2306 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
2307 struct platform_device tegra_skin_therm_est_device = {
2308         .name   = "therm_est",
2309         .id     = -1,
2310         .num_resources  = 0,
2311         .dev = {
2312                 .platform_data = 0,
2313         },
2314 };
2315 #endif
2316
2317 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
2318 static struct resource tegra_tsensor_resources[]= {
2319         {
2320                 .start  = TEGRA_TSENSOR_BASE,
2321                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
2322                 .flags  = IORESOURCE_MEM,
2323         },
2324         {
2325                 .start  = INT_TSENSOR,
2326                 .end    = INT_TSENSOR,
2327                 .flags  = IORESOURCE_IRQ,
2328         },
2329         {
2330                 .start  = TEGRA_PMC_BASE + 0x1B0,
2331                 /* 2 pmc registers mapped */
2332                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
2333                 .flags  = IORESOURCE_MEM,
2334         },
2335 };
2336
2337 struct platform_device tegra_tsensor_device = {
2338         .name   = "tegra-tsensor",
2339         .id     = -1,
2340         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
2341         .resource       = tegra_tsensor_resources,
2342         .dev = {
2343                 .platform_data = 0,
2344         },
2345 };
2346 #endif
2347
2348 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2349 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
2350 static u64 tegra12_se_dma_mask = DMA_BIT_MASK(64);
2351
2352 struct resource tegra_se_resources[] = {
2353         [0] = {
2354                 .start = TEGRA_SE_BASE,
2355                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2356                 .flags = IORESOURCE_MEM,
2357         },
2358         [1] = {
2359                 .start  = TEGRA_PMC_BASE,
2360                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2361                 .flags  = IORESOURCE_MEM,
2362         },
2363         [2] = {
2364                 .start = INT_SE,
2365                 .end = INT_SE,
2366                 .flags = IORESOURCE_IRQ,
2367         },
2368 };
2369
2370 struct platform_device tegra_se_device = {
2371         .name = "tegra-se",
2372         .id = -1,
2373         .dev = {
2374                 .coherent_dma_mask = DMA_BIT_MASK(32),
2375                 .dma_mask = &tegra_se_dma_mask,
2376         },
2377         .resource = tegra_se_resources,
2378         .num_resources = ARRAY_SIZE(tegra_se_resources),
2379 };
2380
2381 struct platform_device tegra11_se_device = {
2382         .name = "tegra11-se",
2383         .id = -1,
2384         .dev = {
2385                 .coherent_dma_mask = DMA_BIT_MASK(32),
2386                 .dma_mask = &tegra_se_dma_mask,
2387         },
2388         .resource = tegra_se_resources,
2389         .num_resources = ARRAY_SIZE(tegra_se_resources),
2390 };
2391
2392 struct platform_device tegra12_se_device = {
2393         .name = "tegra12-se",
2394         .id = -1,
2395         .dev = {
2396                 .coherent_dma_mask = DMA_BIT_MASK(64),
2397                 .dma_mask = &tegra12_se_dma_mask,
2398         },
2399         .resource = tegra_se_resources,
2400         .num_resources = ARRAY_SIZE(tegra_se_resources),
2401 };
2402 #endif
2403
2404 static struct resource tegra_disp1_resources[] = {
2405         {
2406                 .name   = "irq",
2407                 .start  = INT_DISPLAY_GENERAL,
2408                 .end    = INT_DISPLAY_GENERAL,
2409                 .flags  = IORESOURCE_IRQ,
2410         },
2411         {
2412                 .name   = "regs",
2413                 .start  = TEGRA_DISPLAY_BASE,
2414                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2415                 .flags  = IORESOURCE_MEM,
2416         },
2417         {
2418                 .name   = "fbmem",
2419                 .start  = 0,
2420                 .end    = 0,
2421                 .flags  = IORESOURCE_MEM,
2422         },
2423         {
2424                 .name   = "dsi_regs",
2425                 .start  = TEGRA_DSI_BASE,
2426                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2427                 .flags  = IORESOURCE_MEM,
2428         },
2429 };
2430
2431 struct platform_device tegra_disp1_device = {
2432         .name           = "tegradc",
2433         .id             = 0,
2434         .resource       = tegra_disp1_resources,
2435         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2436 };
2437
2438 static struct resource tegra_disp2_resources[] = {
2439         {
2440                 .name   = "irq",
2441                 .start  = INT_DISPLAY_B_GENERAL,
2442                 .end    = INT_DISPLAY_B_GENERAL,
2443                 .flags  = IORESOURCE_IRQ,
2444         },
2445         {
2446                 .name   = "regs",
2447                 .start  = TEGRA_DISPLAY2_BASE,
2448                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2449                 .flags  = IORESOURCE_MEM,
2450         },
2451         {
2452                 .name   = "fbmem",
2453                 .flags  = IORESOURCE_MEM,
2454                 .start  = 0,
2455                 .end    = 0,
2456         },
2457         {
2458                 .name   = "hdmi_regs",
2459                 .start  = TEGRA_HDMI_BASE,
2460                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2461                 .flags  = IORESOURCE_MEM,
2462         },
2463 };
2464
2465 struct platform_device tegra_disp2_device = {
2466         .name           = "tegradc",
2467         .id             = 1,
2468         .resource       = tegra_disp2_resources,
2469         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2470         .dev = {
2471                 .platform_data = 0,
2472         },
2473 };
2474
2475 struct platform_device tegra_nvmap_device = {
2476         .name   = "tegra-nvmap",
2477         .id     = -1,
2478 };
2479
2480 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2481 static struct resource tegra_cec_resources[] = {
2482         [0] = {
2483                 .start = TEGRA_CEC_BASE,
2484                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2485                 .flags = IORESOURCE_MEM,
2486         },
2487         [1] = {
2488                 .start = INT_CEC,
2489                 .end = INT_CEC,
2490                 .flags = IORESOURCE_IRQ,
2491         },
2492 };
2493
2494 struct platform_device tegra_cec_device = {
2495         .name = "tegra_cec",
2496         .id   = -1,
2497         .resource = tegra_cec_resources,
2498         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2499 };
2500 #endif
2501
2502 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2503 static struct resource cl_dvfs_resource[] = {
2504 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
2505         [0] = {
2506                 .start  = TEGRA_CL_DVFS_BASE,
2507                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2508                 .flags  = IORESOURCE_MEM,
2509         },
2510 #else
2511         [0] = {
2512                 .start  = TEGRA_CLK13_RESET_BASE + 0x84,
2513                 .end    = TEGRA_CLK13_RESET_BASE + 0x84 + TEGRA_CL_DVFS_SIZE-1,
2514                 .flags  = IORESOURCE_MEM,
2515         },
2516         [1] = {
2517                 .start  = TEGRA_CL_DVFS_BASE,
2518                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2519                 .flags  = IORESOURCE_MEM,
2520         },
2521 #endif
2522 };
2523
2524 struct platform_device tegra_cl_dvfs_device = {
2525         .name           = "tegra_cl_dvfs",
2526         .id             = -1,
2527         .resource       = cl_dvfs_resource,
2528         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2529 };
2530 #endif
2531
2532 struct platform_device tegra_fuse_device = {
2533         .name   = "tegra-fuse",
2534         .id     = -1,
2535 };
2536
2537 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
2538 static struct tegra_wakeup_monitor_platform_data
2539                         tegratab_tegra_wakeup_monitor_pdata = {
2540         .wifi_wakeup_source     = 6,
2541         .rtc_wakeup_source      = 18,
2542 };
2543
2544 struct platform_device tegratab_tegra_wakeup_monitor_device = {
2545         .name = "tegra_wakeup_monitor",
2546         .id   = -1,
2547         .dev  = {
2548                 .platform_data = &tegratab_tegra_wakeup_monitor_pdata,
2549         },
2550 };
2551 #endif
2552
2553 static struct resource ptm_resources[] = {
2554         {
2555                 .name  = "ptm",
2556                 .start = PTM0_BASE,
2557                 .end   = PTM0_BASE + SZ_4K - 1,
2558                 .flags = IORESOURCE_MEM,
2559         },
2560         {
2561                 .name  = "ptm",
2562                 .start = PTM1_BASE,
2563                 .end   = PTM1_BASE + SZ_4K - 1,
2564                 .flags = IORESOURCE_MEM,
2565         },
2566         {
2567                 .name  = "ptm",
2568                 .start = PTM2_BASE,
2569                 .end   = PTM2_BASE + SZ_4K - 1,
2570                 .flags = IORESOURCE_MEM,
2571         },
2572         {
2573                 .name  = "ptm",
2574                 .start = PTM3_BASE,
2575                 .end   = PTM3_BASE + SZ_4K - 1,
2576                 .flags = IORESOURCE_MEM,
2577         },
2578         {
2579                 .name  = "etb",
2580                 .start = ETB_BASE,
2581                 .end   = ETB_BASE + SZ_4K - 1,
2582                 .flags = IORESOURCE_MEM,
2583         },
2584         {
2585                 .name  = "funnel",
2586                 .start = FUNNEL_BASE,
2587                 .end   = FUNNEL_BASE + SZ_4K - 1,
2588                 .flags = IORESOURCE_MEM,
2589         },
2590         {
2591                 .name  = "tpiu",
2592                 .start = TPIU_BASE,
2593                 .end   = TPIU_BASE + SZ_4K - 1,
2594                 .flags = IORESOURCE_MEM,
2595         },
2596 };
2597
2598 struct platform_device tegra_ptm_device = {
2599         .name          = "ptm",
2600         .id            = -1,
2601         .num_resources = ARRAY_SIZE(ptm_resources),
2602         .resource      = ptm_resources,
2603 };
2604
2605 void __init tegra_init_debug_uart_rate(void)
2606 {
2607         unsigned int uartclk;
2608         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2609
2610         BUG_ON(IS_ERR(debug_uart_parent));
2611         uartclk = clk_get_rate(debug_uart_parent);
2612
2613         debug_uarta_platform_data[0].uartclk = uartclk;
2614         debug_uartb_platform_data[0].uartclk = uartclk;
2615         debug_uartc_platform_data[0].uartclk = uartclk;
2616         debug_uartd_platform_data[0].uartclk = uartclk;
2617 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2618         debug_uarte_platform_data[0].uartclk = uartclk;
2619 #endif
2620 }
2621
2622 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2623 static struct resource tegra_hier_ictlr_resource[] = {
2624         [0] = {
2625                 .start  = TEGRA_HIER2_ICTLR1_BASE,
2626                 .end    = TEGRA_HIER2_ICTLR1_BASE + TEGRA_HIER2_ICTLR1_SIZE - 1,
2627                 .flags  = IORESOURCE_MEM,
2628         },
2629         [1] = {
2630                 .start  = TEGRA_MSELECT_BASE,
2631                 .end    = TEGRA_MSELECT_BASE + TEGRA_MSELECT_SIZE - 1,
2632                 .flags  = IORESOURCE_MEM,
2633         },
2634         [2] = {
2635                 .start  = INT_HIER_GROUP1_CPU,
2636                 .end    = INT_HIER_GROUP1_CPU,
2637                 .flags  = IORESOURCE_IRQ,
2638         },
2639 };
2640
2641 struct platform_device tegra_hier_ictlr_device = {
2642         .name           = "tegra-hier-ictlr",
2643         .id             = -1,
2644         .resource       = tegra_hier_ictlr_resource,
2645         .num_resources  = ARRAY_SIZE(tegra_hier_ictlr_resource),
2646 };
2647 #endif