arch/arm/mach-tegra/board-ardbeg.c

   1 /*
   2  * arch/arm/mach-tegra/board-ardbeg.c
   3  *
   4  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/ctype.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/i2c-hid.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/delay.h>
  31 #include <linux/i2c-tegra.h>
  32 #include <linux/gpio.h>
  33 #include <linux/input.h>
  34 #include <linux/platform_data/tegra_usb.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/rm31080a_ts.h>
  37 #include <linux/maxim_sti.h>
  38 #include <linux/memblock.h>
  39 #include <linux/spi/spi-tegra.h>
  40 #include <linux/nfc/pn544.h>
  41 #include <linux/rfkill-gpio.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/ti_wilink_st.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/smb349-charger.h>
  46 #include <linux/max17048_battery.h>
  47 #include <linux/leds.h>
  48 #include <linux/i2c/at24.h>
  49 #include <linux/of_platform.h>
  50 #include <linux/i2c.h>
  51 #include <linux/i2c-tegra.h>
  52 #include <linux/platform_data/serial-tegra.h>
  53 #include <linux/edp.h>
  54 #include <linux/usb/tegra_usb_phy.h>
  55 #include <linux/mfd/palmas.h>
  56 #include <linux/clk/tegra.h>
  57 #include <media/tegra_dtv.h>
  58 #include <linux/clocksource.h>
  59 #include <linux/irqchip.h>
  60 #include <linux/irqchip/tegra.h>
  61 #include <linux/tegra-soc.h>
  62 #include <linux/tegra_fiq_debugger.h>
  63 #include <linux/platform_data/tegra_usb_modem_power.h>
  64 #include <linux/platform_data/tegra_ahci.h>
  65 #include <linux/irqchip/tegra.h>
  66 #include <sound/max98090.h>
  67
  68 #include <mach/irqs.h>
  69 #include <mach/pinmux.h>
  70 #include <mach/pinmux-t12.h>
  71 #include <mach/io_dpd.h>
  72 #include <mach/i2s.h>
  73 #include <mach/isomgr.h>
  74 #include <mach/tegra_asoc_pdata.h>
  75 #include <mach/dc.h>
  76 #include <mach/tegra_usb_pad_ctrl.h>
  77
  78 #include <asm/mach-types.h>
  79 #include <asm/mach/arch.h>
  80 #include <mach/gpio-tegra.h>
  81 #include <mach/xusb.h>
  82
  83 #include "board.h"
  84 #include "board-ardbeg.h"
  85 #include "board-common.h"
  86 #include "board-touch-raydium.h"
  87 #include "board-touch-maxim_sti.h"
  88 #include "clock.h"
  89 #include "common.h"
  90 #include "devices.h"
  91 #include "gpio-names.h"
  92 #include "iomap.h"
  93 #include "pm.h"
  94 #include "tegra-board-id.h"
  95 #include "tegra-of-dev-auxdata.h"
  96
  97 static struct board_info board_info, display_board_info;
  98
  99 static struct resource ardbeg_bluedroid_pm_resources[] = {
 100         [0] = {
 101                 .name   = "shutdown_gpio",
 102                 .start  = TEGRA_GPIO_PR1,
 103                 .end    = TEGRA_GPIO_PR1,
 104                 .flags  = IORESOURCE_IO,
 105         },
 106         [1] = {
 107                 .name = "host_wake",
 108                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 109         },
 110         [2] = {
 111                 .name = "gpio_ext_wake",
 112                 .start  = TEGRA_GPIO_PEE1,
 113                 .end    = TEGRA_GPIO_PEE1,
 114                 .flags  = IORESOURCE_IO,
 115         },
 116         [3] = {
 117                 .name = "gpio_host_wake",
 118                 .start  = TEGRA_GPIO_PU6,
 119                 .end    = TEGRA_GPIO_PU6,
 120                 .flags  = IORESOURCE_IO,
 121         },
 122         [4] = {
 123                 .name = "reset_gpio",
 124                 .start  = TEGRA_GPIO_PX1,
 125                 .end    = TEGRA_GPIO_PX1,
 126                 .flags  = IORESOURCE_IO,
 127         },
 128 };
 129
 130 static struct platform_device ardbeg_bluedroid_pm_device = {
 131         .name = "bluedroid_pm",
 132         .id             = 0,
 133         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
 134         .resource       = ardbeg_bluedroid_pm_resources,
 135 };
 136
 137 static noinline void __init ardbeg_setup_bluedroid_pm(void)
 138 {
 139         ardbeg_bluedroid_pm_resources[1].start =
 140                 ardbeg_bluedroid_pm_resources[1].end =
 141                                 gpio_to_irq(TEGRA_GPIO_PU6);
 142         platform_device_register(&ardbeg_bluedroid_pm_device);
 143 }
 144
 145 static struct i2c_board_info __initdata rt5639_board_info = {
 146         I2C_BOARD_INFO("rt5639", 0x1c),
 147 };
 148
 149 static struct max98090_eq_cfg max98090_eq_cfg[] = {
 150 };
 151
 152 static struct max98090_pdata norrin_max98090_pdata = {
 153         /* Equalizer Configuration */
 154         .eq_cfg = max98090_eq_cfg,
 155         .eq_cfgcnt = ARRAY_SIZE(max98090_eq_cfg),
 156
 157         /* Microphone Configuration */
 158         .digmic_left_mode = 1,
 159         .digmic_right_mode = 1,
 160 };
 161
 162 static struct i2c_board_info __initdata max98090_board_info = {
 163         I2C_BOARD_INFO("max98090", 0x10),
 164         .platform_data  = &norrin_max98090_pdata,
 165 };
 166
 167 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
 168         /* name         parent          rate            enabled */
 169         { "pll_m",      NULL,           0,              false},
 170         { "hda",        "pll_p",        108000000,      false},
 171         { "hda2codec_2x", "pll_p",      48000000,       false},
 172         { "pwm",        "pll_p",        48000000,       false},
 173         { "pll_a",      "pll_p_out1",   282240000,      false},
 174         { "pll_a_out0", "pll_a",        12288000,       false},
 175         { "i2s1",       "pll_a_out0",   0,              false},
 176         { "i2s3",       "pll_a_out0",   0,              false},
 177         { "i2s4",       "pll_a_out0",   0,              false},
 178         { "spdif_out",  "pll_a_out0",   0,              false},
 179         { "d_audio",    "pll_a_out0",   12288000,       false},
 180         { "dam0",       "clk_m",        12000000,       false},
 181         { "dam1",       "clk_m",        12000000,       false},
 182         { "dam2",       "clk_m",        12000000,       false},
 183         { "audio1",     "i2s1_sync",    0,              false},
 184         { "audio3",     "i2s3_sync",    0,              false},
 185         { "vi_sensor",  "pll_p",        150000000,      false},
 186         { "vi_sensor2", "pll_p",        150000000,      false},
 187         { "cilab",      "pll_p",        150000000,      false},
 188         { "cilcd",      "pll_p",        150000000,      false},
 189         { "cile",       "pll_p",        150000000,      false},
 190         { "i2c1",       "pll_p",        3200000,        false},
 191         { "i2c2",       "pll_p",        3200000,        false},
 192         { "i2c3",       "pll_p",        3200000,        false},
 193         { "i2c4",       "pll_p",        3200000,        false},
 194         { "i2c5",       "pll_p",        3200000,        false},
 195         { "sbc1",       "pll_p",        25000000,       false},
 196         { "sbc2",       "pll_p",        25000000,       false},
 197         { "sbc3",       "pll_p",        25000000,       false},
 198         { "sbc4",       "pll_p",        25000000,       false},
 199         { "sbc5",       "pll_p",        25000000,       false},
 200         { "sbc6",       "pll_p",        25000000,       false},
 201         { "uarta",      "pll_p",        408000000,      false},
 202         { "uartb",      "pll_p",        408000000,      false},
 203         { "uartc",      "pll_p",        408000000,      false},
 204         { "uartd",      "pll_p",        408000000,      false},
 205         { NULL,         NULL,           0,              0},
 206 };
 207
 208 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
 209         .hid_descriptor_address = 0x0,
 210 };
 211
 212 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
 213         I2C_BOARD_INFO("hid", 0x3B),
 214         .platform_data  = &i2c_keyboard_pdata,
 215 };
 216
 217 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
 218         .hid_descriptor_address = 0x20,
 219 };
 220
 221 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
 222         I2C_BOARD_INFO("hid", 0x2C),
 223         .platform_data  = &i2c_touchpad_pdata,
 224 };
 225
 226 static void ardbeg_i2c_init(void)
 227 {
 228         struct board_info board_info;
 229         tegra_get_board_info(&board_info);
 230
 231         if (board_info.board_id == BOARD_PM374) {
 232                 i2c_register_board_info(0, &max98090_board_info, 1);
 233         } else if (board_info.board_id != BOARD_PM359)
 234                 i2c_register_board_info(0, &rt5639_board_info, 1);
 235
 236         if (board_info.board_id == BOARD_PM359 ||
 237                 board_info.board_id == BOARD_PM358 ||
 238                 board_info.board_id == BOARD_PM363 ||
 239                 board_info.board_id == BOARD_PM374) {
 240                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
 241                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
 242
 243                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
 244                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
 245         }
 246 }
 247
 248 #ifndef CONFIG_USE_OF
 249 static struct platform_device *ardbeg_uart_devices[] __initdata = {
 250         &tegra_uarta_device,
 251         &tegra_uartb_device,
 252         &tegra_uartc_device,
 253 };
 254
 255 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
 256         .dma_req_selector = 8,
 257         .modem_interrupt = false,
 258 };
 259
 260 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
 261         .dma_req_selector = 9,
 262         .modem_interrupt = false,
 263 };
 264
 265 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
 266         .dma_req_selector = 10,
 267         .modem_interrupt = false,
 268 };
 269 #endif
 270
 271 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
 272         .dma_req_selector = 19,
 273         .modem_interrupt = false,
 274 };
 275
 276 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
 277         .gpio_hp_det = TEGRA_GPIO_HP_DET,
 278         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
 279         .gpio_spkr_en = -1,
 280         .gpio_int_mic_en = -1,
 281         .gpio_ext_mic_en = -1,
 282         .gpio_hp_mute = -1,
 283         .gpio_codec1 = -1,
 284         .gpio_codec2 = -1,
 285         .gpio_codec3 = -1,
 286         .i2s_param[HIFI_CODEC]       = {
 287                 .audio_port_id = 1,
 288                 .is_i2s_master = 1,
 289                 .i2s_mode = TEGRA_DAIFMT_I2S,
 290                 .sample_size    = 16,
 291                 .channels       = 2,
 292                 .bit_clk        = 1536000,
 293         },
 294         .i2s_param[BT_SCO] = {
 295                 .audio_port_id = 3,
 296                 .is_i2s_master = 1,
 297                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
 298         },
 299         .i2s_param[BASEBAND]    = {
 300                 .audio_port_id  = 0,
 301                 .is_i2s_master  = 1,
 302                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 303                 .sample_size    = 16,
 304                 .rate           = 16000,
 305                 .channels       = 2,
 306                 .bit_clk        = 1024000,
 307         },
 308 };
 309
 310 static struct tegra_asoc_platform_data norrin_audio_pdata_max98090 = {
 311         .gpio_hp_det            = NORRIN_GPIO_HP_DET,
 312         .gpio_ext_mic_en        = TEGRA_GPIO_HP_DET,
 313         .gpio_hp_mute           = -1,
 314         .edp_support            = true,
 315         .edp_states             = {1080, 842, 0},
 316         .i2s_param[HIFI_CODEC]  = {
 317                 .audio_port_id  = 1,
 318                 .is_i2s_master  = 1,
 319                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 320                 .sample_size    = 16,
 321                 .channels       = 2,
 322                 .bit_clk        = 1536000,
 323         },
 324         .i2s_param[BT_SCO]      = {
 325                 .audio_port_id  = 3,
 326                 .is_i2s_master  = 1,
 327                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 328                 .sample_size    = 16,
 329                 .channels       = 1,
 330                 .bit_clk        = 512000,
 331         },
 332 };
 333
 334 static void ardbeg_audio_init(void)
 335 {
 336         struct board_info board_info;
 337         tegra_get_board_info(&board_info);
 338         if (board_info.board_id == BOARD_PM359 ||
 339                         board_info.board_id == BOARD_PM358 ||
 340                         board_info.board_id == BOARD_PM370 ||
 341                         board_info.board_id == BOARD_PM374 ||
 342                         board_info.board_id == BOARD_PM375 ||
 343                         board_info.board_id == BOARD_PM377 ||
 344                         board_info.board_id == BOARD_PM363) {
 345                 /*Laguna*/
 346                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_HP_DET;
 347                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 1;
 348                 if (board_info.board_id != BOARD_PM363)
 349                         ardbeg_audio_pdata_rt5639.gpio_ldo1_en = -1;
 350         } else {
 351                 /*Ardbeg*/
 352
 353                 if (board_info.board_id == BOARD_E1762 ||
 354                         board_info.board_id == BOARD_P1761 ||
 355                         board_info.board_id == BOARD_E1922) {
 356                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 357                                 TEGRA_GPIO_CDC_IRQ;
 358                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 359                 } else {
 360                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 361                                 TEGRA_GPIO_HP_DET;
 362                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = false;
 363                 }
 364                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 365                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 366         }
 367
 368         if (board_info.board_id == BOARD_E1971) {
 369                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_CDC_IRQ;
 370                 ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 371                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 372                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 373         }
 374
 375         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
 376         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
 377
 378         norrin_audio_pdata_max98090.codec_name = "max98090.0-0010";
 379         norrin_audio_pdata_max98090.codec_dai_name = "HiFi";
 380 }
 381
 382 static struct platform_device ardbeg_audio_device_rt5639 = {
 383         .name = "tegra-snd-rt5639",
 384         .id = 0,
 385         .dev = {
 386                 .platform_data = &ardbeg_audio_pdata_rt5639,
 387         },
 388 };
 389
 390 static struct platform_device norrin_audio_device_max98090 = {
 391         .name   = "tegra-snd-max98090",
 392         .id     = 0,
 393         .dev    = {
 394                 .platform_data = &norrin_audio_pdata_max98090,
 395         },
 396 };
 397
 398 static void __init ardbeg_uart_init(void)
 399 {
 400
 401 #ifndef CONFIG_USE_OF
 402         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
 403         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
 404         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
 405         platform_add_devices(ardbeg_uart_devices,
 406                         ARRAY_SIZE(ardbeg_uart_devices));
 407 #endif
 408         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 409         if (!is_tegra_debug_uartport_hs()) {
 410                 int debug_port_id = uart_console_debug_init(3);
 411                 if (debug_port_id < 0)
 412                         return;
 413
 414 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
 415 #if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \
 416         defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
 417         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_AVP, NULL, -1, -1);
 418 #else
 419         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
 420 #endif
 421 #else
 422                 platform_device_register(uart_console_debug_device);
 423 #endif
 424         } else {
 425                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 426                 platform_device_register(&tegra_uartd_device);
 427         }
 428 }
 429
 430 static struct resource tegra_rtc_resources[] = {
 431         [0] = {
 432                 .start = TEGRA_RTC_BASE,
 433                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
 434                 .flags = IORESOURCE_MEM,
 435         },
 436         [1] = {
 437                 .start = INT_RTC,
 438                 .end = INT_RTC,
 439                 .flags = IORESOURCE_IRQ,
 440         },
 441 };
 442
 443 static struct platform_device tegra_rtc_device = {
 444         .name = "tegra_rtc",
 445         .id   = -1,
 446         .resource = tegra_rtc_resources,
 447         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
 448 };
 449
 450 static struct platform_device *ardbeg_devices[] __initdata = {
 451         &tegra_pmu_device,
 452         &tegra_rtc_device,
 453 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
 454         &tegratab_tegra_wakeup_monitor_device,
 455 #endif
 456         &tegra_udc_device,
 457 #if defined(CONFIG_TEGRA_WATCHDOG)
 458         &tegra_wdt0_device,
 459 #endif
 460 #if defined(CONFIG_TEGRA_AVP)
 461         &tegra_avp_device,
 462 #endif
 463 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
 464         &tegra12_se_device,
 465 #endif
 466         &tegra_ahub_device,
 467         &tegra_dam_device0,
 468         &tegra_dam_device1,
 469         &tegra_dam_device2,
 470         &tegra_i2s_device0,
 471         &tegra_i2s_device1,
 472         &tegra_i2s_device3,
 473         &tegra_i2s_device4,
 474         &tegra_spdif_device,
 475         &spdif_dit_device,
 476         &bluetooth_dit_device,
 477         &baseband_dit_device,
 478         &tegra_hda_device,
 479         &tegra_offload_device,
 480         &tegra30_avp_audio_device,
 481 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
 482         &tegra_aes_device,
 483 #endif
 484         &tegra_hier_ictlr_device,
 485 };
 486
 487 static struct tegra_usb_platform_data tegra_udc_pdata = {
 488         .port_otg = true,
 489         .has_hostpc = true,
 490         .unaligned_dma_buf_supported = false,
 491         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 492         .op_mode = TEGRA_USB_OPMODE_DEVICE,
 493         .u_data.dev = {
 494                 .vbus_pmu_irq = 0,
 495                 .vbus_gpio = -1,
 496                 .charging_supported = true,
 497                 .remote_wakeup_supported = false,
 498         },
 499         .u_cfg.utmi = {
 500                 .hssync_start_delay = 0,
 501                 .elastic_limit = 16,
 502                 .idle_wait_delay = 17,
 503                 .term_range_adj = 6,
 504                 .xcvr_setup = 8,
 505                 .xcvr_lsfslew = 2,
 506                 .xcvr_lsrslew = 2,
 507                 .xcvr_setup_offset = 0,
 508                 .xcvr_use_fuses = 1,
 509         },
 510 };
 511
 512 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
 513         .port_otg = true,
 514         .has_hostpc = true,
 515         .unaligned_dma_buf_supported = false,
 516         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 517         .op_mode = TEGRA_USB_OPMODE_HOST,
 518         .u_data.host = {
 519                 .vbus_gpio = -1,
 520                 .hot_plug = false,
 521                 .remote_wakeup_supported = true,
 522                 .power_off_on_suspend = true,
 523         },
 524         .u_cfg.utmi = {
 525                 .hssync_start_delay = 0,
 526                 .elastic_limit = 16,
 527                 .idle_wait_delay = 17,
 528                 .term_range_adj = 6,
 529                 .xcvr_setup = 15,
 530                 .xcvr_lsfslew = 0,
 531                 .xcvr_lsrslew = 3,
 532                 .xcvr_setup_offset = 0,
 533                 .xcvr_use_fuses = 1,
 534                 .vbus_oc_map = 0x4,
 535                 .xcvr_hsslew_lsb = 2,
 536         },
 537 };
 538
 539 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
 540         .port_otg = false,
 541         .has_hostpc = true,
 542         .unaligned_dma_buf_supported = false,
 543         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 544         .op_mode = TEGRA_USB_OPMODE_HOST,
 545         .u_data.host = {
 546                 .vbus_gpio = -1,
 547                 .hot_plug = false,
 548                 .remote_wakeup_supported = true,
 549                 .power_off_on_suspend = true,
 550         },
 551         .u_cfg.utmi = {
 552                 .hssync_start_delay = 0,
 553                 .elastic_limit = 16,
 554                 .idle_wait_delay = 17,
 555                 .term_range_adj = 6,
 556                 .xcvr_setup = 8,
 557                 .xcvr_lsfslew = 2,
 558                 .xcvr_lsrslew = 2,
 559                 .xcvr_setup_offset = 0,
 560                 .xcvr_use_fuses = 1,
 561                 .vbus_oc_map = 0x5,
 562         },
 563 };
 564
 565 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
 566         .port_otg = false,
 567         .has_hostpc = true,
 568         .unaligned_dma_buf_supported = false,
 569         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 570         .op_mode = TEGRA_USB_OPMODE_HOST,
 571         .u_data.host = {
 572                 .vbus_gpio = -1,
 573                 .hot_plug = false,
 574                 .remote_wakeup_supported = true,
 575                 .power_off_on_suspend = true,
 576         },
 577         .u_cfg.utmi = {
 578         .hssync_start_delay = 0,
 579                 .elastic_limit = 16,
 580                 .idle_wait_delay = 17,
 581                 .term_range_adj = 6,
 582                 .xcvr_setup = 8,
 583                 .xcvr_lsfslew = 2,
 584                 .xcvr_lsrslew = 2,
 585                 .xcvr_setup_offset = 0,
 586                 .xcvr_use_fuses = 1,
 587                 .vbus_oc_map = 0x5,
 588         },
 589 };
 590
 591 static struct gpio modem_gpios[] = { /* Bruce modem */
 592         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
 593         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
 594         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
 595 };
 596
 597 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
 598         .port_otg = false,
 599         .has_hostpc = true,
 600         .unaligned_dma_buf_supported = false,
 601         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 602         .op_mode = TEGRA_USB_OPMODE_HOST,
 603         .u_data.host = {
 604                 .vbus_gpio = -1,
 605                 .hot_plug = false,
 606                 .remote_wakeup_supported = true,
 607                 .power_off_on_suspend = true,
 608         },
 609 };
 610
 611 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
 612         .port_otg = false,
 613         .has_hostpc = true,
 614         .unaligned_dma_buf_supported = false,
 615         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 616         .op_mode        = TEGRA_USB_OPMODE_HOST,
 617         .u_data.host = {
 618                 .vbus_gpio = -1,
 619                 .hot_plug = false,
 620                 .remote_wakeup_supported = true,
 621                 .power_off_on_suspend = true,
 622         },
 623 };
 624
 625
 626 static struct tegra_usb_otg_data tegra_otg_pdata = {
 627         .ehci_device = &tegra_ehci1_device,
 628         .ehci_pdata = &tegra_ehci1_utmi_pdata,
 629 };
 630
 631 static void ardbeg_usb_init(void)
 632 {
 633         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 634         int modem_id = tegra_get_modem_id();
 635         struct board_info bi;
 636         tegra_get_pmu_board_info(&bi);
 637
 638         if (board_info.sku == 1100 || board_info.board_id == BOARD_P1761 ||
 639                                         board_info.board_id == BOARD_E1784)
 640                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
 641
 642         if (board_info.board_id == BOARD_PM359 ||
 643                         board_info.board_id == BOARD_PM358 ||
 644                         board_info.board_id == BOARD_PM370 ||
 645                         board_info.board_id == BOARD_PM374 ||
 646                         board_info.board_id == BOARD_PM375 ||
 647                         board_info.board_id == BOARD_PM377 ||
 648                         board_info.board_id == BOARD_PM363) {
 649                 /* Laguna */
 650                 /* Host cable is detected through AMS PMU Interrupt */
 651                 if (board_info.major_revision >= 'A' &&
 652                         board_info.major_revision <= 'D' &&
 653                         board_info.board_id == BOARD_PM375) {
 654                         tegra_udc_pdata.id_det_type = TEGRA_USB_VIRTUAL_ID;
 655                         tegra_ehci1_utmi_pdata.id_det_type =
 656                                                 TEGRA_USB_VIRTUAL_ID;
 657                 } else {
 658                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 659                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 660                 }
 661                 tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
 662         } else {
 663                 /* Ardbeg and TN8 */
 664
 665                 /*
 666                  * TN8 supports vbus changing and it can handle
 667                  * vbus voltages larger then 5V.  Enable this.
 668                  */
 669                 if (board_info.board_id == BOARD_P1761 ||
 670                         board_info.board_id == BOARD_E1784 ||
 671                         board_info.board_id == BOARD_E1780) {
 672
 673                         /*
 674                          * Set the maximum voltage that can be supplied
 675                          * over USB vbus that the board supports if we use
 676                          * a quick charge 2 wall charger.
 677                          */
 678                         tegra_udc_pdata.qc2_voltage = TEGRA_USB_QC2_9V;
 679                         tegra_udc_pdata.u_data.dev.qc2_current_limit_ma = 1200;
 680
 681                         /* charger needs to be set to 2A - h/w will do 1.8A */
 682                         tegra_udc_pdata.u_data.dev.dcp_current_limit_ma = 2000;
 683                 }
 684
 685                 switch (bi.board_id) {
 686                 case BOARD_E1733:
 687                         /* Host cable is detected through PMU Interrupt */
 688                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 689                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 690                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 691                                                          "as3722-extcon";
 692                         break;
 693                 case BOARD_E1736:
 694                 case BOARD_E1769:
 695                 case BOARD_E1735:
 696                 case BOARD_E1936:
 697                 case BOARD_P1761:
 698                         /* Device cable is detected through PMU Interrupt */
 699                         tegra_udc_pdata.support_pmu_vbus = true;
 700                         tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
 701                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
 702                         tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
 703                                                          "palmas-extcon";
 704                         /* Host cable is detected through PMU Interrupt */
 705                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 706                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 707                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 708                                                          "palmas-extcon";
 709                 }
 710
 711                 /* Enable Y-Cable support */
 712                 if (bi.board_id == BOARD_P1761)
 713                         tegra_ehci1_utmi_pdata.u_data.host.support_y_cable =
 714                                                         true;
 715         }
 716
 717         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
 718                 tegra_otg_pdata.is_xhci = false;
 719                 tegra_udc_pdata.u_data.dev.is_xhci = false;
 720         } else {
 721                 tegra_otg_pdata.is_xhci = true;
 722                 tegra_udc_pdata.u_data.dev.is_xhci = true;
 723         }
 724         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
 725         platform_device_register(&tegra_otg_device);
 726         /* Setup the udc platform data */
 727         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
 728
 729         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 730                 if (!modem_id) {
 731                         if ((bi.board_id != BOARD_P1761) &&
 732                             (bi.board_id != BOARD_E1922) &&
 733                             (bi.board_id != BOARD_E1784)) {
 734                                 tegra_ehci2_device.dev.platform_data =
 735                                         &tegra_ehci2_utmi_pdata;
 736                                 platform_device_register(&tegra_ehci2_device);
 737                         }
 738                 }
 739         }
 740
 741         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 742                 if ((bi.board_id != BOARD_P1761) &&
 743                     (bi.board_id != BOARD_E1922) &&
 744                     (bi.board_id != BOARD_E1784)) {
 745                         tegra_ehci3_device.dev.platform_data =
 746                                 &tegra_ehci3_utmi_pdata;
 747                         platform_device_register(&tegra_ehci3_device);
 748                 }
 749         }
 750
 751 }
 752
 753 static struct tegra_xusb_platform_data xusb_pdata = {
 754         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
 755                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
 756 };
 757
 758 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
 759 static void ardbeg_xusb_init(void)
 760 {
 761         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 762
 763         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
 764
 765         if (board_info.board_id == BOARD_PM359 ||
 766                         board_info.board_id == BOARD_PM358 ||
 767                         board_info.board_id == BOARD_PM374 ||
 768                         board_info.board_id == BOARD_PM370 ||
 769                         board_info.board_id == BOARD_PM363) {
 770                 if (board_info.board_id == BOARD_PM374 ||
 771                         board_info.board_id == BOARD_PM370)
 772                         pr_info("Norrin. 0x%x\n", board_info.board_id);
 773                 else
 774                         pr_info("Laguna. 0x%x\n", board_info.board_id);
 775
 776                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 777                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 778                                 TEGRA_XUSB_SS_P0);
 779
 780                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 781                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 782                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
 783
 784                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 785         } else if (board_info.board_id == BOARD_PM375) {
 786                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 787                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 788                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 789                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
 790                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0);
 791                 xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);
 792         } else {
 793                 /* Ardbeg */
 794                 if (board_info.board_id == BOARD_E1781) {
 795                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
 796                         /* Shield ERS-S */
 797                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 798                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 799
 800                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 801                                 xusb_pdata.portmap &= ~(
 802                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
 803                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 804                 } else {
 805                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
 806                         /* Shield ERS */
 807                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 808                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 809                                         TEGRA_XUSB_SS_P0);
 810
 811                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 812                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 813                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 814                 }
 815                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 816         }
 817
 818         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
 819                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
 820
 821         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
 822                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
 823 }
 824 #endif
 825
 826 static int baseband_init(void)
 827 {
 828         int ret;
 829
 830         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
 831         if (ret) {
 832                 pr_warn("%s:gpio request failed\n", __func__);
 833                 return ret;
 834         }
 835
 836         /* enable pull-down for MDM_COLD_BOOT */
 837         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
 838                                     TEGRA_PUPD_PULL_DOWN);
 839
 840         /* Release modem reset to start boot */
 841         gpio_set_value(MDM_RST, 1);
 842
 843         /* export GPIO for user space access through sysfs */
 844         gpio_export(MDM_RST, false);
 845         gpio_export(MDM_SAR0, false);
 846
 847         return 0;
 848 }
 849
 850 static const struct tegra_modem_operations baseband_operations = {
 851         .init = baseband_init,
 852 };
 853
 854 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
 855         .ops = &baseband_operations,
 856         .regulator_name = "vdd_wwan_mdm",
 857         .wake_gpio = -1,
 858         .boot_gpio = MDM_COLDBOOT,
 859         .boot_irq_flags = IRQF_TRIGGER_RISING |
 860                                     IRQF_TRIGGER_FALLING |
 861                                     IRQF_ONESHOT,
 862         .autosuspend_delay = 2000,
 863         .short_autosuspend_delay = 50,
 864         .tegra_ehci_device = &tegra_ehci2_device,
 865         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
 866         .mdm_power_report_gpio = MDM_POWER_REPORT,
 867         .mdm_power_irq_flags = IRQF_TRIGGER_RISING |
 868                                 IRQF_TRIGGER_FALLING |
 869                                 IRQF_ONESHOT,
 870 };
 871
 872 static struct platform_device icera_bruce_device = {
 873         .name = "tegra_usb_modem_power",
 874         .id = -1,
 875         .dev = {
 876                 .platform_data = &baseband_pdata,
 877         },
 878 };
 879
 880 static void ardbeg_modem_init(void)
 881 {
 882         int modem_id = tegra_get_modem_id();
 883         struct board_info board_info;
 884         struct board_info pmu_board_info;
 885         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 886
 887         tegra_get_board_info(&board_info);
 888         tegra_get_pmu_board_info(&pmu_board_info);
 889         pr_info("%s: modem_id = %d\n", __func__, modem_id);
 890
 891         switch (modem_id) {
 892         case TEGRA_BB_BRUCE:
 893                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 894                         /* Set specific USB wake source for Ardbeg */
 895                         if (board_info.board_id == BOARD_E1780)
 896                                 tegra_set_wake_source(42, INT_USB2);
 897                         if (pmu_board_info.board_id == BOARD_E1736 ||
 898                                 pmu_board_info.board_id == BOARD_E1769 ||
 899                                 pmu_board_info.board_id == BOARD_E1936)
 900                                 baseband_pdata.regulator_name = NULL;
 901                         platform_device_register(&icera_bruce_device);
 902                 }
 903                 break;
 904         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
 905                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 906                         tegra_ehci2_device.dev.platform_data =
 907                                 &tegra_ehci2_hsic_smsc_hub_pdata;
 908                         /* Set specific USB wake source for Ardbeg */
 909                         if (board_info.board_id == BOARD_E1780)
 910                                 tegra_set_wake_source(42, INT_USB2);
 911                         platform_device_register(&tegra_ehci2_device);
 912                 } else
 913                         xusb_pdata.pretend_connect_0 = true;
 914                 break;
 915         default:
 916                 return;
 917         }
 918 }
 919
 920 #ifdef CONFIG_USE_OF
 921 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
 922         T124_SPI_OF_DEV_AUXDATA,
 923         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
 924                                 NULL),
 925         OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
 926         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
 927                 NULL),
 928         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
 929                 "gk20a.0", NULL),
 930 #ifdef CONFIG_ARCH_TEGRA_VIC
 931         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
 932 #endif
 933         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
 934                 NULL),
 935         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
 936         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
 937         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
 938         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
 939         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
 940                                 NULL),
 941         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
 942                                 NULL),
 943         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
 944                                 NULL),
 945         T124_I2C_OF_DEV_AUXDATA,
 946         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
 947                                 &xusb_pdata),
 948         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
 949                 NULL),
 950         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
 951                 NULL),
 952         OF_DEV_AUXDATA("nvidia,tegra124-nvavp", 0x60001000, "nvavp",
 953                                 NULL),
 954         OF_DEV_AUXDATA("nvidia,tegra124-pwm", 0x7000a000, "tegra-pwm", NULL),
 955         OF_DEV_AUXDATA("nvidia,tegra124-dfll", 0x70110000, "tegra_cl_dvfs",
 956                 NULL),
 957         OF_DEV_AUXDATA("nvidia,tegra132-dfll", 0x70040084, "tegra_cl_dvfs",
 958                 NULL),
 959         OF_DEV_AUXDATA("nvidia,tegra124-efuse", TEGRA_FUSE_BASE, "tegra-fuse",
 960                 NULL),
 961         OF_DEV_AUXDATA("nvidia,tegra124-camera", 0, "pcl-generic",
 962                                 NULL),
 963         OF_DEV_AUXDATA("nvidia,tegra114-ahci-sata", 0x70027000, "tegra-sata.0",
 964                 NULL),
 965         {}
 966 };
 967 #endif
 968
 969 struct maxim_sti_pdata maxim_sti_pdata = {
 970         .touch_fusion         = "/vendor/bin/touch_fusion",
 971         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 972         .fw_name              = "maxim_fp35.bin",
 973         .nl_family            = TF_FAMILY_NAME,
 974         .nl_mc_groups         = 5,
 975         .chip_access_method   = 2,
 976         .default_reset_state  = 0,
 977         .tx_buf_size          = 4100,
 978         .rx_buf_size          = 4100,
 979         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 980         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 981 };
 982
 983 struct maxim_sti_pdata maxim_sti_pdata_rd = {
 984         .touch_fusion         = "/vendor/bin/touch_fusion_rd",
 985         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 986         .fw_name              = "maxim_fp35.bin",
 987         .nl_family            = TF_FAMILY_NAME,
 988         .nl_mc_groups         = 5,
 989         .chip_access_method   = 2,
 990         .default_reset_state  = 0,
 991         .tx_buf_size          = 4100,
 992         .rx_buf_size          = 4100,
 993         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 994         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 995 };
 996
 997 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
 998         .rx_clk_tap_delay = 0,
 999         .is_hw_based_cs = true,
1000         .tx_clk_tap_delay = 0,
1001 };
1002
1003 struct spi_board_info maxim_sti_spi_board = {
1004         .modalias = MAXIM_STI_NAME,
1005         .bus_num = TOUCH_SPI_ID,
1006         .chip_select = TOUCH_SPI_CS,
1007         .max_speed_hz = 12 * 1000 * 1000,
1008         .mode = SPI_MODE_0,
1009         .platform_data = &maxim_sti_pdata,
1010         .controller_data = &maxim_dev_cdata,
1011 };
1012
1013 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
1014         /* name         parent          rate            enabled */
1015         { "extern2",    "pll_p",        41000000,       false},
1016         { "clk_out_2",  "extern2",      40800000,       false},
1017         { NULL,         NULL,           0,              0},
1018 };
1019
1020 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
1021         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1022         .config = 0,
1023         .platform_id = RM_PLATFORM_A010,
1024         .name_of_clock = "clk_out_2",
1025         .name_of_clock_con = "extern2",
1026 };
1027
1028 static struct rm_spi_ts_platform_data rm31080ts_tn8_data = {
1029         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1030         .config = 0,
1031         .platform_id = RM_PLATFORM_T008,
1032         .name_of_clock = "clk_out_2",
1033         .name_of_clock_con = "extern2",
1034 };
1035
1036 static struct rm_spi_ts_platform_data rm31080ts_tn8_p1765_data = {
1037         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1038         .config = 0,
1039         .platform_id = RM_PLATFORM_T008_2,
1040         .name_of_clock = "clk_out_2",
1041         .name_of_clock_con = "extern2",
1042 };
1043
1044 static struct rm_spi_ts_platform_data rm31080ts_norrin_data = {
1045         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1046         .config = 0,
1047         .platform_id = RM_PLATFORM_P140,
1048         .name_of_clock = "clk_out_2",
1049         .name_of_clock_con = "extern2",
1050 };
1051
1052 struct rm_spi_ts_platform_data rm31080ts_t132loki_data = {
1053         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1054         .config = 0,
1055         .platform_id = RM_PLATFORM_L005,
1056         .name_of_clock = "clk_out_2",
1057         .name_of_clock_con = "extern2",
1058 };
1059
1060 struct rm_spi_ts_platform_data rm31080ts_t132loki_data_jdi_5 = {
1061         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1062         .config = 0,
1063         .platform_id = RM_PLATFORM_L005,
1064         .name_of_clock = "clk_out_2",
1065         .name_of_clock_con = "extern2",
1066         .gpio_sensor_select0 = false,
1067         .gpio_sensor_select1 = true,
1068 };
1069 static struct tegra_spi_device_controller_data dev_cdata = {
1070         .rx_clk_tap_delay = 0,
1071         .tx_clk_tap_delay = 16,
1072 };
1073
1074 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1075         {
1076                 .modalias = "rm_ts_spidev",
1077                 .bus_num = TOUCH_SPI_ID,
1078                 .chip_select = TOUCH_SPI_CS,
1079                 .max_speed_hz = 12 * 1000 * 1000,
1080                 .mode = SPI_MODE_0,
1081                 .controller_data = &dev_cdata,
1082                 .platform_data = &rm31080ts_ardbeg_data,
1083         },
1084 };
1085
1086 static struct spi_board_info rm31080a_tn8_spi_board[1] = {
1087         {
1088                 .modalias = "rm_ts_spidev",
1089                 .bus_num = TOUCH_SPI_ID,
1090                 .chip_select = TOUCH_SPI_CS,
1091                 .max_speed_hz = 18 * 1000 * 1000,
1092                 .mode = SPI_MODE_0,
1093                 .controller_data = &dev_cdata,
1094                 .platform_data = &rm31080ts_tn8_data,
1095         },
1096 };
1097
1098 static struct spi_board_info rm31080a_tn8_p1765_spi_board[1] = {
1099         {
1100                 .modalias = "rm_ts_spidev",
1101                 .bus_num = TOUCH_SPI_ID,
1102                 .chip_select = TOUCH_SPI_CS,
1103                 .max_speed_hz = 18 * 1000 * 1000,
1104                 .mode = SPI_MODE_0,
1105                 .controller_data = &dev_cdata,
1106                 .platform_data = &rm31080ts_tn8_p1765_data,
1107         },
1108 };
1109
1110 static struct spi_board_info rm31080a_norrin_spi_board[1] = {
1111         {
1112                 .modalias = "rm_ts_spidev",
1113                 .bus_num = NORRIN_TOUCH_SPI_ID,
1114                 .chip_select = NORRIN_TOUCH_SPI_CS,
1115                 .max_speed_hz = 12 * 1000 * 1000,
1116                 .mode = SPI_MODE_0,
1117                 .controller_data = &dev_cdata,
1118                 .platform_data = &rm31080ts_norrin_data,
1119         },
1120 };
1121
1122 static int __init ardbeg_touch_init(void)
1123 {
1124         tegra_get_board_info(&board_info);
1125
1126         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1127                 pr_info("%s init maxim touch\n", __func__);
1128 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1129         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1130                 if (tegra_get_touch_panel_id() == TOUCHPANEL_TN7)
1131                         maxim_sti_spi_board.platform_data = &maxim_sti_pdata_rd;
1132                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1133 #endif
1134         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1135                 pr_info("%s init raydium touch\n", __func__);
1136                 tegra_clk_init_from_table(touch_clk_init_table);
1137                 if (board_info.board_id == BOARD_PM374) {
1138                         rm31080a_norrin_spi_board[0].irq =
1139                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1140                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1141                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1142                                         &rm31080ts_norrin_data,
1143                                         &rm31080a_norrin_spi_board[0],
1144                                         ARRAY_SIZE(rm31080a_norrin_spi_board));
1145                 } else if ((board_info.board_id == BOARD_P2530) ||
1146                         (board_info.board_id == BOARD_E2548)) {
1147                         if (board_info.sku == BOARD_SKU_FOSTER)
1148                                 return 0;
1149                         if (tegra_get_touch_panel_id() == TOUCHPANEL_LOKI_JDI5)
1150                                 rm31080a_ardbeg_spi_board[0].platform_data =
1151                                         &rm31080ts_t132loki_data_jdi_5;
1152                         else
1153                                 rm31080a_ardbeg_spi_board[0].platform_data =
1154                                         &rm31080ts_t132loki_data;
1155                         if (board_info.fab >= 0xa3) {
1156                                 rm31080ts_t132loki_data.name_of_clock = NULL;
1157                                 rm31080ts_t132loki_data.name_of_clock_con = NULL;
1158                         } else
1159                                 tegra_clk_init_from_table(touch_clk_init_table);
1160                                 rm31080a_ardbeg_spi_board[0].irq =
1161                                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1162                                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1163                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1164                                         &rm31080ts_t132loki_data,
1165                                         &rm31080a_ardbeg_spi_board[0],
1166                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1167                 } else if (board_info.board_id == BOARD_P1761) {
1168                         rm31080a_tn8_spi_board[0].irq =
1169                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1170                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1171                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1172                                 &rm31080ts_tn8_data,
1173                                 &rm31080a_tn8_spi_board[0],
1174                                 ARRAY_SIZE(rm31080a_tn8_spi_board));
1175                 } else if (board_info.board_id == BOARD_P1765) {
1176                         rm31080a_tn8_p1765_spi_board[0].irq =
1177                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1178                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1179                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1180                                 &rm31080ts_tn8_p1765_data,
1181                                 &rm31080a_tn8_p1765_spi_board[0],
1182                                 ARRAY_SIZE(rm31080a_tn8_p1765_spi_board));
1183                 } else {
1184                         rm31080a_ardbeg_spi_board[0].irq =
1185                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1186                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1187                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1188                                         &rm31080ts_ardbeg_data,
1189                                         &rm31080a_ardbeg_spi_board[0],
1190                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1191                 }
1192         }
1193         return 0;
1194 }
1195
1196 static void __init ardbeg_sysedp_init(void)
1197 {
1198         struct board_info bi;
1199
1200         tegra_get_board_info(&bi);
1201
1202         switch (bi.board_id) {
1203         case BOARD_E1780:
1204                 if (bi.sku == 1100) {
1205                         tn8_new_sysedp_init();
1206                 }
1207                 else
1208                         shield_new_sysedp_init();
1209                 break;
1210         case BOARD_E1971:
1211         case BOARD_E1922:
1212         case BOARD_E1784:
1213         case BOARD_P1761:
1214         case BOARD_P1765:
1215                 tn8_new_sysedp_init();
1216                 break;
1217         case BOARD_PM358:
1218         case BOARD_PM359:
1219         case BOARD_PM375:
1220         case BOARD_PM377:
1221         default:
1222                 break;
1223         }
1224 }
1225
1226 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1227 {
1228         struct board_info bi;
1229
1230         tegra_get_board_info(&bi);
1231
1232         switch (bi.board_id) {
1233         case BOARD_E1780:
1234                 if (bi.sku == 1100)
1235                         tn8_sysedp_dynamic_capping_init();
1236                 else
1237                         shield_sysedp_dynamic_capping_init();
1238                 break;
1239         case BOARD_E1971:
1240         case BOARD_E1922:
1241         case BOARD_E1784:
1242         case BOARD_P1761:
1243         case BOARD_P1765:
1244                 tn8_sysedp_dynamic_capping_init();
1245                 break;
1246         case BOARD_PM358:
1247         case BOARD_PM359:
1248         case BOARD_PM375:
1249         case BOARD_PM377:
1250         default:
1251                 break;
1252         }
1253 }
1254
1255 static void __init ardbeg_sysedp_batmon_init(void)
1256 {
1257         struct board_info bi;
1258
1259         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1260                 return;
1261
1262         tegra_get_board_info(&bi);
1263
1264         switch (bi.board_id) {
1265         case BOARD_E1780:
1266                 if (bi.sku != 1100)
1267                         shield_sysedp_batmon_init();
1268                 break;
1269         case BOARD_PM358:
1270         case BOARD_PM359:
1271         case BOARD_PM375:
1272         case BOARD_PM377:
1273         default:
1274                 break;
1275         }
1276 }
1277
1278
1279
1280 static void __init edp_init(void)
1281 {
1282         struct board_info bi;
1283
1284         tegra_get_board_info(&bi);
1285
1286         switch (bi.board_id) {
1287         case BOARD_E1780:
1288                 if (bi.sku == 1100)
1289                         tn8_edp_init();
1290                 else
1291                         ardbeg_edp_init();
1292                 break;
1293         case BOARD_P1761:
1294                         tn8_edp_init();
1295                         break;
1296         case BOARD_PM358:
1297         case BOARD_PM359:
1298         case BOARD_PM377:
1299                         laguna_edp_init();
1300                         break;
1301         case BOARD_P2530:
1302         case BOARD_E2548:
1303                         loki_edp_init();
1304                         break;
1305         case BOARD_PM375:
1306         default:
1307                         ardbeg_edp_init();
1308                         break;
1309         }
1310 }
1311
1312 static void __init tegra_ardbeg_early_init(void)
1313 {
1314         ardbeg_sysedp_init();
1315         tegra_clk_init_from_table(ardbeg_clk_init_table);
1316         tegra_clk_verify_parents();
1317         if (of_machine_is_compatible("nvidia,jetson-tk1"))
1318                 tegra_soc_device_init("jetson-tk1");
1319         else if (of_machine_is_compatible("nvidia,laguna"))
1320                 tegra_soc_device_init("laguna");
1321         else if (of_machine_is_compatible("nvidia,tn8"))
1322                 tegra_soc_device_init("tn8");
1323         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1324                 tegra_soc_device_init("ardbeg_sata");
1325         else if (of_machine_is_compatible("nvidia,norrin"))
1326                 tegra_soc_device_init("norrin");
1327         else if (of_machine_is_compatible("nvidia,bowmore"))
1328                 tegra_soc_device_init("bowmore");
1329         else if (of_machine_is_compatible("nvidia,t132loki"))
1330                 tegra_soc_device_init("t132loki");
1331         else
1332                 tegra_soc_device_init("ardbeg");
1333 }
1334
1335 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1336         .dma_req_selector = 11,
1337 };
1338
1339 static void __init ardbeg_dtv_init(void)
1340 {
1341         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1342         platform_device_register(&tegra_dtv_device);
1343 }
1344
1345 static struct tegra_io_dpd pexbias_io = {
1346         .name                   = "PEX_BIAS",
1347         .io_dpd_reg_index       = 0,
1348         .io_dpd_bit             = 4,
1349 };
1350 static struct tegra_io_dpd pexclk1_io = {
1351         .name                   = "PEX_CLK1",
1352         .io_dpd_reg_index       = 0,
1353         .io_dpd_bit             = 5,
1354 };
1355 static struct tegra_io_dpd pexclk2_io = {
1356         .name                   = "PEX_CLK2",
1357         .io_dpd_reg_index       = 0,
1358         .io_dpd_bit             = 6,
1359 };
1360
1361 #ifdef CONFIG_NV_SENSORHUB
1362 static int __init tegra_jetson_sensorhub_init(void)
1363 {
1364
1365         if (gpio_request(SENSOR_HUB_RST, "sensor_hub_rst"))
1366                 pr_warn("%s:%d: gpio_request failed", __func__, __LINE__);
1367
1368         if (gpio_request(SENSOR_HUB_BOOT0, "sensor_hub_boot0"))
1369                 pr_warn("%s:%d: gpio_request failed", __func__, __LINE__);
1370
1371         if (gpio_direction_output(SENSOR_HUB_BOOT0, 0))
1372                 pr_warn("%s:%d: gpio_direction_output failed",
1373                         __func__, __LINE__);
1374
1375         if (gpio_direction_output(SENSOR_HUB_RST, 0))
1376                 pr_warn("%s:%d: gpio_direction_output failed",
1377                         __func__, __LINE__);
1378
1379         /* SENSOR_HUB_RESET */
1380         gpio_set_value(SENSOR_HUB_RST, 0);
1381         /* Boot0 is useless in Kalamos HW00 board  - Drive low */
1382         gpio_set_value(SENSOR_HUB_BOOT0, 0);
1383         msleep(1000);
1384         gpio_set_value(SENSOR_HUB_RST, 1);
1385
1386         if (gpio_export(SENSOR_HUB_RST, 1))
1387                 pr_warn("%s:%d: gpio_export failed", __func__, __LINE__);
1388
1389         if (gpio_export(SENSOR_HUB_BOOT0, 1))
1390                 pr_warn("%s:%d: gpio_export failed", __func__, __LINE__);
1391
1392         pr_info("%s: MCU init done\n", __func__);
1393
1394         return 0;
1395
1396 }
1397
1398 late_initcall(tegra_jetson_sensorhub_init);
1399 #endif
1400
1401 static void __init tegra_ardbeg_late_init(void)
1402 {
1403         struct board_info board_info;
1404         tegra_get_board_info(&board_info);
1405         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1406                 board_info.board_id, board_info.sku,
1407                 board_info.fab, board_info.major_revision,
1408                 board_info.minor_revision);
1409
1410         if (board_info.board_id == BOARD_E2548 ||
1411                         board_info.board_id == BOARD_P2530)
1412                 loki_pinmux_init();
1413 #ifndef CONFIG_MACH_EXUMA
1414         ardbeg_display_init();
1415 #endif
1416         ardbeg_uart_init();
1417         ardbeg_usb_init();
1418         ardbeg_modem_init();
1419 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
1420         ardbeg_xusb_init();
1421 #endif
1422         ardbeg_i2c_init();
1423         ardbeg_audio_init();
1424         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1425         if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
1426                 platform_device_register(&norrin_audio_device_max98090);
1427         else if (board_info.board_id != BOARD_PM359)
1428                 platform_device_register(&ardbeg_audio_device_rt5639);
1429         tegra_io_dpd_init();
1430         if (board_info.board_id == BOARD_E2548 ||
1431                         board_info.board_id == BOARD_P2530)
1432                 loki_sdhci_init();
1433         else
1434                 ardbeg_sdhci_init();
1435
1436         if (board_info.board_id == BOARD_PM359 ||
1437                         board_info.board_id == BOARD_PM358 ||
1438                         board_info.board_id == BOARD_PM370 ||
1439                         board_info.board_id == BOARD_PM375 ||
1440                         board_info.board_id == BOARD_PM377 ||
1441                         board_info.board_id == BOARD_PM363)
1442                 laguna_regulator_init();
1443         else if (board_info.board_id == BOARD_PM374)
1444                 norrin_regulator_init();
1445         else if (board_info.board_id == BOARD_E2548 ||
1446                         board_info.board_id == BOARD_P2530)
1447                 loki_regulator_init();
1448         else
1449                 ardbeg_regulator_init();
1450         ardbeg_dtv_init();
1451         ardbeg_suspend_init();
1452
1453         if ((board_info.board_id == BOARD_PM374) ||
1454                 (board_info.board_id == BOARD_E1971) ||
1455                 (board_info.board_id == BOARD_E1973))
1456                 norrin_emc_init();
1457         else if (board_info.board_id == BOARD_E2548 ||
1458                         board_info.board_id == BOARD_P2530)
1459                 loki_emc_init();
1460         else
1461                 ardbeg_emc_init();
1462
1463         edp_init();
1464         isomgr_init();
1465         ardbeg_touch_init();
1466         if (board_info.board_id == BOARD_E2548 ||
1467                         board_info.board_id == BOARD_P2530)
1468                 loki_panel_init();
1469         else
1470                 ardbeg_panel_init();
1471
1472                 /* put PEX pads into DPD mode to save additional power */
1473                 tegra_io_dpd_enable(&pexbias_io);
1474                 tegra_io_dpd_enable(&pexclk1_io);
1475                 tegra_io_dpd_enable(&pexclk2_io);
1476
1477         if (board_info.board_id == BOARD_E2548 ||
1478                         board_info.board_id == BOARD_P2530)
1479                 loki_kbc_init();
1480
1481 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1482         tegra_wdt_recovery_init();
1483 #endif
1484
1485
1486         if (board_info.board_id == BOARD_PM374 ||
1487                 board_info.board_id == BOARD_PM359 ||
1488                 board_info.board_id == BOARD_PM358 ||
1489                 board_info.board_id == BOARD_PM370 ||
1490                 board_info.board_id == BOARD_PM375 ||
1491                 board_info.board_id == BOARD_PM377 ||
1492                 board_info.board_id == BOARD_PM363) {
1493                 ardbeg_sensors_init();
1494                 norrin_soctherm_init();
1495         }       else if (board_info.board_id == BOARD_E2548 ||
1496                         board_info.board_id == BOARD_P2530) {
1497                 loki_sensors_init();
1498                 loki_fan_init();
1499                 loki_soctherm_init();
1500         }       else {
1501                 ardbeg_sensors_init();
1502                 ardbeg_soctherm_init();
1503         }
1504
1505         ardbeg_setup_bluedroid_pm();
1506         ardbeg_sysedp_dynamic_capping_init();
1507         ardbeg_sysedp_batmon_init();
1508 }
1509
1510 static void __init tegra_ardbeg_init_early(void)
1511 {
1512         tegra_get_board_info(&board_info);
1513         if (board_info.board_id == BOARD_E2548 ||
1514                         board_info.board_id == BOARD_P2530)
1515                 loki_rail_alignment_init();
1516         else
1517                 ardbeg_rail_alignment_init();
1518         tegra12x_init_early();
1519 }
1520
1521 static void __init tegra_ardbeg_dt_init(void)
1522 {
1523         tegra_get_board_info(&board_info);
1524         tegra_get_display_board_info(&display_board_info);
1525
1526         tegra_ardbeg_early_init();
1527 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1528         carveout_linear_set(&tegra_generic_cma_dev);
1529         carveout_linear_set(&tegra_vpr_cma_dev);
1530 #endif
1531 #ifdef CONFIG_USE_OF
1532         ardbeg_camera_auxdata(ardbeg_auxdata_lookup);
1533         of_platform_populate(NULL,
1534                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1535                 &platform_bus);
1536 #endif
1537         tegra_get_board_info(&board_info);
1538         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1539                 board_info.board_id, board_info.sku,
1540                 board_info.fab, board_info.major_revision,
1541                 board_info.minor_revision);
1542
1543         tegra_ardbeg_late_init();
1544 }
1545
1546 static void __init tegra_ardbeg_reserve(void)
1547 {
1548 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1549         ulong tmp;
1550 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1551
1552 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1553                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1554         ulong carveout_size = 0;
1555         ulong fb2_size = SZ_16M;
1556 #else
1557         ulong carveout_size = SZ_1G;
1558         ulong fb2_size = SZ_4M;
1559 #endif
1560         ulong fb1_size = SZ_16M + SZ_2M;
1561         ulong vpr_size = 186 * SZ_1M;
1562
1563 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
1564         /* support FBcon on 4K monitors */
1565         fb2_size = SZ_64M + SZ_8M;      /* 4096*2160*4*2 = 70778880 bytes */
1566 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
1567
1568 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1569         tmp = fb1_size;
1570         fb1_size = fb2_size;
1571         fb2_size = tmp;
1572 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1573
1574         tegra_reserve4(carveout_size, fb1_size, fb2_size, vpr_size);
1575 }
1576
1577 static const char * const ardbeg_dt_board_compat[] = {
1578         "nvidia,ardbeg",
1579         NULL
1580 };
1581
1582 static const char * const laguna_dt_board_compat[] = {
1583         "nvidia,laguna",
1584         NULL
1585 };
1586
1587 static const char * const tn8_dt_board_compat[] = {
1588         "nvidia,tn8",
1589         NULL
1590 };
1591
1592 static const char * const ardbeg_sata_dt_board_compat[] = {
1593         "nvidia,ardbeg_sata",
1594         NULL
1595 };
1596
1597 static const char * const norrin_dt_board_compat[] = {
1598         "nvidia,norrin",
1599         NULL
1600 };
1601
1602 static const char * const bowmore_dt_board_compat[] = {
1603         "nvidia,bowmore",
1604         NULL
1605 };
1606
1607 static const char * const loki_dt_board_compat[] = {
1608         "nvidia,t132loki",
1609         NULL
1610 };
1611
1612 static const char * const jetson_dt_board_compat[] = {
1613         "nvidia,jetson-tk1",
1614         NULL
1615 };
1616
1617 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1618 DT_MACHINE_START(LOKI, "t132loki")
1619         .atag_offset    = 0x100,
1620         .smp            = smp_ops(tegra_smp_ops),
1621         .map_io         = tegra_map_common_io,
1622         .reserve        = tegra_ardbeg_reserve,
1623         .init_early     = tegra_ardbeg_init_early,
1624         .init_irq       = irqchip_init,
1625         .init_time      = clocksource_of_init,
1626         .init_machine   = tegra_ardbeg_dt_init,
1627         .restart        = tegra_assert_system_reset,
1628         .dt_compat      = loki_dt_board_compat,
1629         .init_late      = tegra_init_late
1630 MACHINE_END
1631 #endif
1632
1633 DT_MACHINE_START(LAGUNA, "laguna")
1634         .atag_offset    = 0x100,
1635         .smp            = smp_ops(tegra_smp_ops),
1636         .map_io         = tegra_map_common_io,
1637         .reserve        = tegra_ardbeg_reserve,
1638         .init_early     = tegra_ardbeg_init_early,
1639         .init_irq       = irqchip_init,
1640         .init_time      = clocksource_of_init,
1641         .init_machine   = tegra_ardbeg_dt_init,
1642         .restart        = tegra_assert_system_reset,
1643         .dt_compat      = laguna_dt_board_compat,
1644         .init_late      = tegra_init_late
1645 MACHINE_END
1646
1647 DT_MACHINE_START(TN8, "tn8")
1648         .atag_offset    = 0x100,
1649         .smp            = smp_ops(tegra_smp_ops),
1650         .map_io         = tegra_map_common_io,
1651         .reserve        = tegra_ardbeg_reserve,
1652         .init_early     = tegra_ardbeg_init_early,
1653         .init_irq       = irqchip_init,
1654         .init_time      = clocksource_of_init,
1655         .init_machine   = tegra_ardbeg_dt_init,
1656         .restart        = tegra_assert_system_reset,
1657         .dt_compat      = tn8_dt_board_compat,
1658         .init_late      = tegra_init_late
1659 MACHINE_END
1660
1661 DT_MACHINE_START(NORRIN, "norrin")
1662         .atag_offset    = 0x100,
1663         .smp            = smp_ops(tegra_smp_ops),
1664         .map_io         = tegra_map_common_io,
1665         .reserve        = tegra_ardbeg_reserve,
1666         .init_early     = tegra_ardbeg_init_early,
1667         .init_irq       = irqchip_init,
1668         .init_time      = clocksource_of_init,
1669         .init_machine   = tegra_ardbeg_dt_init,
1670         .restart        = tegra_assert_system_reset,
1671         .dt_compat      = norrin_dt_board_compat,
1672         .init_late      = tegra_init_late
1673 MACHINE_END
1674
1675 DT_MACHINE_START(BOWMORE, "bowmore")
1676         .atag_offset    = 0x100,
1677         .smp            = smp_ops(tegra_smp_ops),
1678         .map_io         = tegra_map_common_io,
1679         .reserve        = tegra_ardbeg_reserve,
1680         .init_early     = tegra_ardbeg_init_early,
1681         .init_irq       = irqchip_init,
1682         .init_time      = clocksource_of_init,
1683         .init_machine   = tegra_ardbeg_dt_init,
1684         .restart        = tegra_assert_system_reset,
1685         .dt_compat      = bowmore_dt_board_compat,
1686         .init_late      = tegra_init_late
1687 MACHINE_END
1688
1689 DT_MACHINE_START(ARDBEG, "ardbeg")
1690         .atag_offset    = 0x100,
1691         .smp            = smp_ops(tegra_smp_ops),
1692         .map_io         = tegra_map_common_io,
1693         .reserve        = tegra_ardbeg_reserve,
1694         .init_early     = tegra_ardbeg_init_early,
1695         .init_irq       = irqchip_init,
1696         .init_time      = clocksource_of_init,
1697         .init_machine   = tegra_ardbeg_dt_init,
1698         .restart        = tegra_assert_system_reset,
1699         .dt_compat      = ardbeg_dt_board_compat,
1700         .init_late      = tegra_init_late
1701 MACHINE_END
1702
1703 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1704         .atag_offset    = 0x100,
1705         .smp            = smp_ops(tegra_smp_ops),
1706         .map_io         = tegra_map_common_io,
1707         .reserve        = tegra_ardbeg_reserve,
1708         .init_early     = tegra_ardbeg_init_early,
1709         .init_irq       = irqchip_init,
1710         .init_time      = clocksource_of_init,
1711         .init_machine   = tegra_ardbeg_dt_init,
1712         .restart        = tegra_assert_system_reset,
1713         .dt_compat      = ardbeg_sata_dt_board_compat,
1714         .init_late      = tegra_init_late
1715
1716 MACHINE_END
1717
1718 DT_MACHINE_START(JETSON_TK1, "jetson-tk1")
1719         .atag_offset    = 0x100,
1720         .smp            = smp_ops(tegra_smp_ops),
1721         .map_io         = tegra_map_common_io,
1722         .reserve        = tegra_ardbeg_reserve,
1723         .init_early     = tegra_ardbeg_init_early,
1724         .init_irq       = irqchip_init,
1725         .init_time      = clocksource_of_init,
1726         .init_machine   = tegra_ardbeg_dt_init,
1727         .restart        = tegra_assert_system_reset,
1728         .dt_compat      = jetson_dt_board_compat,
1729         .init_late      = tegra_init_late
1730 MACHINE_END