2 * drivers/video/tegra/dc/dc.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * Copyright (c) 2010-2014, NVIDIA CORPORATION, All rights reserved.
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <linux/clk/tegra.h>
41 #include <video/tegrafb.h>
42 #include <drm/drm_fixed.h>
44 #include <linux/switch.h>
46 #include <linux/of_irq.h>
47 #include <linux/of_address.h>
48 #include <linux/tegra_pm_domains.h>
50 #define CREATE_TRACE_POINTS
51 #include <trace/events/display.h>
56 #include <linux/nvhost.h>
57 #include <linux/nvhost_ioctl.h>
58 #include <mach/latency_allowance.h>
61 #include "dc_config.h"
64 #include "nvhost_sync.h"
69 #ifdef CONFIG_ADF_TEGRA
70 #include "tegra_adf.h"
73 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
75 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
77 /* HACK! This needs to come from DT */
78 #include "../../../../arch/arm/mach-tegra/iomap.h"
80 #define TEGRA_CRC_LATCHED_DELAY 34
82 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL 0x01000000
83 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL 0x0
85 static struct fb_videomode tegra_dc_vga_mode = {
89 .pixclock = KHZ2PICOS(25200),
90 .hsync_len = 96, /* h_sync_width */
91 .vsync_len = 2, /* v_sync_width */
92 .left_margin = 48, /* h_back_porch */
93 .upper_margin = 33, /* v_back_porch */
94 .right_margin = 16, /* h_front_porch */
95 .lower_margin = 10, /* v_front_porch */
100 static struct tegra_dc_mode override_disp_mode[3];
102 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
103 static void tegra_dc_disable_nosync(struct tegra_dc *dc);
104 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
106 DEFINE_MUTEX(tegra_dc_lock);
107 DEFINE_MUTEX(shared_lock);
109 static struct device_dma_parameters tegra_dc_dma_parameters = {
110 .max_segment_size = UINT_MAX,
113 static const struct {
117 /* Window A has no filtering */
119 /* Window B has both H and V filtering */
121 /* Window C has only H filtering */
125 #ifdef CONFIG_TEGRA_DC_CMU
126 static struct tegra_dc_cmu default_cmu = {
127 /* lut1 maps sRGB to linear space. */
129 0, 1, 2, 4, 5, 6, 7, 9,
130 10, 11, 12, 14, 15, 16, 18, 20,
131 21, 23, 25, 27, 29, 31, 33, 35,
132 37, 40, 42, 45, 48, 50, 53, 56,
133 59, 62, 66, 69, 72, 76, 79, 83,
134 87, 91, 95, 99, 103, 107, 112, 116,
135 121, 126, 131, 136, 141, 146, 151, 156,
136 162, 168, 173, 179, 185, 191, 197, 204,
137 210, 216, 223, 230, 237, 244, 251, 258,
138 265, 273, 280, 288, 296, 304, 312, 320,
139 329, 337, 346, 354, 363, 372, 381, 390,
140 400, 409, 419, 428, 438, 448, 458, 469,
141 479, 490, 500, 511, 522, 533, 544, 555,
142 567, 578, 590, 602, 614, 626, 639, 651,
143 664, 676, 689, 702, 715, 728, 742, 755,
144 769, 783, 797, 811, 825, 840, 854, 869,
145 884, 899, 914, 929, 945, 960, 976, 992,
146 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
147 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
148 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
149 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
150 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
151 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
152 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
153 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
154 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
155 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
156 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
157 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
158 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
159 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
160 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
168 /* lut2 maps linear space to sRGB*/
170 0, 1, 2, 2, 3, 4, 5, 6,
171 6, 7, 8, 9, 10, 10, 11, 12,
172 13, 13, 14, 15, 15, 16, 16, 17,
173 18, 18, 19, 19, 20, 20, 21, 21,
174 22, 22, 23, 23, 23, 24, 24, 25,
175 25, 25, 26, 26, 27, 27, 27, 28,
176 28, 29, 29, 29, 30, 30, 30, 31,
177 31, 31, 32, 32, 32, 33, 33, 33,
178 34, 34, 34, 34, 35, 35, 35, 36,
179 36, 36, 37, 37, 37, 37, 38, 38,
180 38, 38, 39, 39, 39, 40, 40, 40,
181 40, 41, 41, 41, 41, 42, 42, 42,
182 42, 43, 43, 43, 43, 43, 44, 44,
183 44, 44, 45, 45, 45, 45, 46, 46,
184 46, 46, 46, 47, 47, 47, 47, 48,
185 48, 48, 48, 48, 49, 49, 49, 49,
186 49, 50, 50, 50, 50, 50, 51, 51,
187 51, 51, 51, 52, 52, 52, 52, 52,
188 53, 53, 53, 53, 53, 54, 54, 54,
189 54, 54, 55, 55, 55, 55, 55, 55,
190 56, 56, 56, 56, 56, 57, 57, 57,
191 57, 57, 57, 58, 58, 58, 58, 58,
192 58, 59, 59, 59, 59, 59, 59, 60,
193 60, 60, 60, 60, 60, 61, 61, 61,
194 61, 61, 61, 62, 62, 62, 62, 62,
195 62, 63, 63, 63, 63, 63, 63, 64,
196 64, 64, 64, 64, 64, 64, 65, 65,
197 65, 65, 65, 65, 66, 66, 66, 66,
198 66, 66, 66, 67, 67, 67, 67, 67,
199 67, 67, 68, 68, 68, 68, 68, 68,
200 68, 69, 69, 69, 69, 69, 69, 69,
201 70, 70, 70, 70, 70, 70, 70, 71,
202 71, 71, 71, 71, 71, 71, 72, 72,
203 72, 72, 72, 72, 72, 72, 73, 73,
204 73, 73, 73, 73, 73, 74, 74, 74,
205 74, 74, 74, 74, 74, 75, 75, 75,
206 75, 75, 75, 75, 75, 76, 76, 76,
207 76, 76, 76, 76, 77, 77, 77, 77,
208 77, 77, 77, 77, 78, 78, 78, 78,
209 78, 78, 78, 78, 78, 79, 79, 79,
210 79, 79, 79, 79, 79, 80, 80, 80,
211 80, 80, 80, 80, 80, 81, 81, 81,
212 81, 81, 81, 81, 81, 81, 82, 82,
213 82, 82, 82, 82, 82, 82, 83, 83,
214 83, 83, 83, 83, 83, 83, 83, 84,
215 84, 84, 84, 84, 84, 84, 84, 84,
216 85, 85, 85, 85, 85, 85, 85, 85,
217 85, 86, 86, 86, 86, 86, 86, 86,
218 86, 86, 87, 87, 87, 87, 87, 87,
219 87, 87, 87, 88, 88, 88, 88, 88,
220 88, 88, 88, 88, 88, 89, 89, 89,
221 89, 89, 89, 89, 89, 89, 90, 90,
222 90, 90, 90, 90, 90, 90, 90, 90,
223 91, 91, 91, 91, 91, 91, 91, 91,
224 91, 91, 92, 92, 92, 92, 92, 92,
225 92, 92, 92, 92, 93, 93, 93, 93,
226 93, 93, 93, 93, 93, 93, 94, 94,
227 94, 94, 94, 94, 94, 94, 94, 94,
228 95, 95, 95, 95, 95, 95, 95, 95,
229 95, 95, 96, 96, 96, 96, 96, 96,
230 96, 96, 96, 96, 96, 97, 97, 97,
231 97, 97, 97, 97, 97, 97, 97, 98,
232 98, 98, 98, 98, 98, 98, 98, 98,
233 98, 98, 99, 99, 99, 99, 99, 99,
234 99, 100, 101, 101, 102, 103, 103, 104,
235 105, 105, 106, 107, 107, 108, 109, 109,
236 110, 111, 111, 112, 113, 113, 114, 115,
237 115, 116, 116, 117, 118, 118, 119, 119,
238 120, 120, 121, 122, 122, 123, 123, 124,
239 124, 125, 126, 126, 127, 127, 128, 128,
240 129, 129, 130, 130, 131, 131, 132, 132,
241 133, 133, 134, 134, 135, 135, 136, 136,
242 137, 137, 138, 138, 139, 139, 140, 140,
243 141, 141, 142, 142, 143, 143, 144, 144,
244 145, 145, 145, 146, 146, 147, 147, 148,
245 148, 149, 149, 150, 150, 150, 151, 151,
246 152, 152, 153, 153, 153, 154, 154, 155,
247 155, 156, 156, 156, 157, 157, 158, 158,
248 158, 159, 159, 160, 160, 160, 161, 161,
249 162, 162, 162, 163, 163, 164, 164, 164,
250 165, 165, 166, 166, 166, 167, 167, 167,
251 168, 168, 169, 169, 169, 170, 170, 170,
252 171, 171, 172, 172, 172, 173, 173, 173,
253 174, 174, 174, 175, 175, 176, 176, 176,
254 177, 177, 177, 178, 178, 178, 179, 179,
255 179, 180, 180, 180, 181, 181, 182, 182,
256 182, 183, 183, 183, 184, 184, 184, 185,
257 185, 185, 186, 186, 186, 187, 187, 187,
258 188, 188, 188, 189, 189, 189, 189, 190,
259 190, 190, 191, 191, 191, 192, 192, 192,
260 193, 193, 193, 194, 194, 194, 195, 195,
261 195, 196, 196, 196, 196, 197, 197, 197,
262 198, 198, 198, 199, 199, 199, 200, 200,
263 200, 200, 201, 201, 201, 202, 202, 202,
264 202, 203, 203, 203, 204, 204, 204, 205,
265 205, 205, 205, 206, 206, 206, 207, 207,
266 207, 207, 208, 208, 208, 209, 209, 209,
267 209, 210, 210, 210, 211, 211, 211, 211,
268 212, 212, 212, 213, 213, 213, 213, 214,
269 214, 214, 214, 215, 215, 215, 216, 216,
270 216, 216, 217, 217, 217, 217, 218, 218,
271 218, 219, 219, 219, 219, 220, 220, 220,
272 220, 221, 221, 221, 221, 222, 222, 222,
273 223, 223, 223, 223, 224, 224, 224, 224,
274 225, 225, 225, 225, 226, 226, 226, 226,
275 227, 227, 227, 227, 228, 228, 228, 228,
276 229, 229, 229, 229, 230, 230, 230, 230,
277 231, 231, 231, 231, 232, 232, 232, 232,
278 233, 233, 233, 233, 234, 234, 234, 234,
279 235, 235, 235, 235, 236, 236, 236, 236,
280 237, 237, 237, 237, 238, 238, 238, 238,
281 239, 239, 239, 239, 240, 240, 240, 240,
282 240, 241, 241, 241, 241, 242, 242, 242,
283 242, 243, 243, 243, 243, 244, 244, 244,
284 244, 244, 245, 245, 245, 245, 246, 246,
285 246, 246, 247, 247, 247, 247, 247, 248,
286 248, 248, 248, 249, 249, 249, 249, 249,
287 250, 250, 250, 250, 251, 251, 251, 251,
288 251, 252, 252, 252, 252, 253, 253, 253,
289 253, 253, 254, 254, 254, 254, 255, 255,
293 static struct tegra_dc_cmu default_limited_cmu = {
294 /* lut1 maps sRGB to linear space. */
296 0, 1, 2, 4, 5, 6, 7, 9,
297 10, 11, 12, 14, 15, 16, 18, 20,
298 21, 23, 25, 27, 29, 31, 33, 35,
299 37, 40, 42, 45, 48, 50, 53, 56,
300 59, 62, 66, 69, 72, 76, 79, 83,
301 87, 91, 95, 99, 103, 107, 112, 116,
302 121, 126, 131, 136, 141, 146, 151, 156,
303 162, 168, 173, 179, 185, 191, 197, 204,
304 210, 216, 223, 230, 237, 244, 251, 258,
305 265, 273, 280, 288, 296, 304, 312, 320,
306 329, 337, 346, 354, 363, 372, 381, 390,
307 400, 409, 419, 428, 438, 448, 458, 469,
308 479, 490, 500, 511, 522, 533, 544, 555,
309 567, 578, 590, 602, 614, 626, 639, 651,
310 664, 676, 689, 702, 715, 728, 742, 755,
311 769, 783, 797, 811, 825, 840, 854, 869,
312 884, 899, 914, 929, 945, 960, 976, 992,
313 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
314 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
315 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
316 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
317 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
318 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
319 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
320 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
321 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
322 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
323 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
324 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
325 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
326 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
327 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
336 * lut2 maps linear space back to sRGB, where
337 * the output range is [16...235] (limited).
340 16, 17, 17, 18, 19, 19, 20, 21,
341 22, 22, 23, 24, 24, 25, 26, 26,
342 27, 27, 28, 29, 29, 30, 30, 31,
343 31, 32, 32, 32, 33, 33, 34, 34,
344 35, 35, 35, 36, 36, 36, 37, 37,
345 38, 38, 38, 39, 39, 39, 40, 40,
346 40, 41, 41, 41, 41, 42, 42, 42,
347 43, 43, 43, 43, 44, 44, 44, 45,
348 45, 45, 45, 46, 46, 46, 46, 47,
349 47, 47, 47, 48, 48, 48, 48, 49,
350 49, 49, 49, 49, 50, 50, 50, 50,
351 51, 51, 51, 51, 51, 52, 52, 52,
352 52, 53, 53, 53, 53, 53, 54, 54,
353 54, 54, 54, 55, 55, 55, 55, 55,
354 56, 56, 56, 56, 56, 56, 57, 57,
355 57, 57, 57, 58, 58, 58, 58, 58,
356 58, 59, 59, 59, 59, 59, 60, 60,
357 60, 60, 60, 60, 61, 61, 61, 61,
358 61, 61, 62, 62, 62, 62, 62, 62,
359 63, 63, 63, 63, 63, 63, 63, 64,
360 64, 64, 64, 64, 64, 65, 65, 65,
361 65, 65, 65, 65, 66, 66, 66, 66,
362 66, 66, 67, 67, 67, 67, 67, 67,
363 67, 68, 68, 68, 68, 68, 68, 68,
364 69, 69, 69, 69, 69, 69, 69, 69,
365 70, 70, 70, 70, 70, 70, 70, 71,
366 71, 71, 71, 71, 71, 71, 72, 72,
367 72, 72, 72, 72, 72, 72, 73, 73,
368 73, 73, 73, 73, 73, 73, 74, 74,
369 74, 74, 74, 74, 74, 74, 75, 75,
370 75, 75, 75, 75, 75, 75, 76, 76,
371 76, 76, 76, 76, 76, 76, 76, 77,
372 77, 77, 77, 77, 77, 77, 77, 78,
373 78, 78, 78, 78, 78, 78, 78, 78,
374 79, 79, 79, 79, 79, 79, 79, 79,
375 80, 80, 80, 80, 80, 80, 80, 80,
376 80, 81, 81, 81, 81, 81, 81, 81,
377 81, 81, 81, 82, 82, 82, 82, 82,
378 82, 82, 82, 82, 83, 83, 83, 83,
379 83, 83, 83, 83, 83, 84, 84, 84,
380 84, 84, 84, 84, 84, 84, 84, 85,
381 85, 85, 85, 85, 85, 85, 85, 85,
382 85, 86, 86, 86, 86, 86, 86, 86,
383 86, 86, 86, 87, 87, 87, 87, 87,
384 87, 87, 87, 87, 87, 88, 88, 88,
385 88, 88, 88, 88, 88, 88, 88, 89,
386 89, 89, 89, 89, 89, 89, 89, 89,
387 89, 89, 90, 90, 90, 90, 90, 90,
388 90, 90, 90, 90, 91, 91, 91, 91,
389 91, 91, 91, 91, 91, 91, 91, 92,
390 92, 92, 92, 92, 92, 92, 92, 92,
391 92, 92, 93, 93, 93, 93, 93, 93,
392 93, 93, 93, 93, 93, 94, 94, 94,
393 94, 94, 94, 94, 94, 94, 94, 94,
394 94, 95, 95, 95, 95, 95, 95, 95,
395 95, 95, 95, 95, 96, 96, 96, 96,
396 96, 96, 96, 96, 96, 96, 96, 96,
397 97, 97, 97, 97, 97, 97, 97, 97,
398 97, 97, 97, 97, 98, 98, 98, 98,
399 98, 98, 98, 98, 98, 98, 98, 98,
400 99, 99, 99, 99, 99, 99, 99, 99,
401 99, 99, 99, 99, 100, 100, 100, 100,
402 100, 100, 100, 100, 100, 100, 100, 100,
403 100, 101, 101, 101, 101, 101, 101, 101,
404 102, 102, 103, 104, 104, 105, 105, 106,
405 107, 107, 108, 108, 109, 109, 110, 111,
406 111, 112, 112, 113, 113, 114, 114, 115,
407 115, 116, 116, 117, 117, 118, 118, 119,
408 119, 120, 120, 121, 121, 122, 122, 123,
409 123, 124, 124, 125, 125, 126, 126, 127,
410 127, 127, 128, 128, 129, 129, 130, 130,
411 131, 131, 131, 132, 132, 133, 133, 134,
412 134, 134, 135, 135, 136, 136, 136, 137,
413 137, 138, 138, 139, 139, 139, 140, 140,
414 141, 141, 141, 142, 142, 142, 143, 143,
415 144, 144, 144, 145, 145, 145, 146, 146,
416 147, 147, 147, 148, 148, 148, 149, 149,
417 150, 150, 150, 151, 151, 151, 152, 152,
418 152, 153, 153, 153, 154, 154, 154, 155,
419 155, 155, 156, 156, 156, 157, 157, 157,
420 158, 158, 158, 159, 159, 159, 160, 160,
421 160, 161, 161, 161, 162, 162, 162, 163,
422 163, 163, 164, 164, 164, 165, 165, 165,
423 166, 166, 166, 166, 167, 167, 167, 168,
424 168, 168, 169, 169, 169, 169, 170, 170,
425 170, 171, 171, 171, 172, 172, 172, 172,
426 173, 173, 173, 174, 174, 174, 174, 175,
427 175, 175, 176, 176, 176, 176, 177, 177,
428 177, 178, 178, 178, 178, 179, 179, 179,
429 180, 180, 180, 180, 181, 181, 181, 181,
430 182, 182, 182, 183, 183, 183, 183, 184,
431 184, 184, 184, 185, 185, 185, 185, 186,
432 186, 186, 187, 187, 187, 187, 188, 188,
433 188, 188, 189, 189, 189, 189, 190, 190,
434 190, 190, 191, 191, 191, 191, 192, 192,
435 192, 192, 193, 193, 193, 193, 194, 194,
436 194, 194, 195, 195, 195, 195, 196, 196,
437 196, 196, 197, 197, 197, 197, 198, 198,
438 198, 198, 199, 199, 199, 199, 199, 200,
439 200, 200, 200, 201, 201, 201, 201, 202,
440 202, 202, 202, 203, 203, 203, 203, 203,
441 204, 204, 204, 204, 205, 205, 205, 205,
442 206, 206, 206, 206, 206, 207, 207, 207,
443 207, 208, 208, 208, 208, 208, 209, 209,
444 209, 209, 210, 210, 210, 210, 210, 211,
445 211, 211, 211, 212, 212, 212, 212, 212,
446 213, 213, 213, 213, 213, 214, 214, 214,
447 214, 215, 215, 215, 215, 215, 216, 216,
448 216, 216, 216, 217, 217, 217, 217, 218,
449 218, 218, 218, 218, 219, 219, 219, 219,
450 219, 220, 220, 220, 220, 220, 221, 221,
451 221, 221, 221, 222, 222, 222, 222, 222,
452 223, 223, 223, 223, 224, 224, 224, 224,
453 224, 225, 225, 225, 225, 225, 226, 226,
454 226, 226, 226, 227, 227, 227, 227, 227,
455 227, 228, 228, 228, 228, 228, 229, 229,
456 229, 229, 229, 230, 230, 230, 230, 230,
457 231, 231, 231, 231, 231, 232, 232, 232,
458 232, 232, 233, 233, 233, 233, 233, 233,
459 234, 234, 234, 234, 234, 235, 235, 235,
464 void tegra_dc_clk_enable(struct tegra_dc *dc)
466 clk_prepare_enable(dc->clk);
467 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
470 void tegra_dc_clk_disable(struct tegra_dc *dc)
472 clk_disable_unprepare(dc->clk);
473 tegra_dvfs_set_rate(dc->clk, 0);
476 void tegra_dc_get(struct tegra_dc *dc)
478 tegra_dc_io_start(dc);
480 /* extra reference to dc clk */
481 clk_prepare_enable(dc->clk);
484 void tegra_dc_put(struct tegra_dc *dc)
486 /* balance extra dc clk reference */
487 clk_disable_unprepare(dc->clk);
492 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
495 if (dc->out_ops && dc->out_ops->hold)
496 dc->out_ops->hold(dc);
499 void tegra_dc_release_dc_out(struct tegra_dc *dc)
501 if (dc->out_ops && dc->out_ops->release)
502 dc->out_ops->release(dc);
506 #define DUMP_REG(a) do { \
507 snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
508 #a, a, tegra_dc_readl(dc, a)); \
512 static void _dump_regs(struct tegra_dc *dc, void *data,
513 void (* print)(void *data, const char *str))
517 const char winname[] = "ABCDHT";
518 /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
520 /* If gated, quietly return. */
521 if (!tegra_powergate_is_powered(dc->powergate_id))
524 mutex_lock(&dc->lock);
526 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
527 DC_CMD_STATE_ACCESS);
529 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
530 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
531 DUMP_REG(DC_CMD_SIGNAL_RAISE);
532 DUMP_REG(DC_CMD_INT_STATUS);
533 DUMP_REG(DC_CMD_INT_MASK);
534 DUMP_REG(DC_CMD_INT_ENABLE);
535 DUMP_REG(DC_CMD_INT_TYPE);
536 DUMP_REG(DC_CMD_INT_POLARITY);
537 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
538 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
539 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
540 DUMP_REG(DC_CMD_STATE_ACCESS);
541 DUMP_REG(DC_CMD_STATE_CONTROL);
542 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
543 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
545 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
546 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
547 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
548 DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
549 DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
550 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
551 DUMP_REG(DC_DISP_REF_TO_SYNC);
552 DUMP_REG(DC_DISP_SYNC_WIDTH);
553 DUMP_REG(DC_DISP_BACK_PORCH);
554 DUMP_REG(DC_DISP_DISP_ACTIVE);
555 DUMP_REG(DC_DISP_FRONT_PORCH);
556 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
557 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
558 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
559 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
560 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
561 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
562 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
563 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
564 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
565 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
566 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
567 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
568 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
569 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
570 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
571 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
572 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
573 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
574 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
575 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
576 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
577 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
578 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
579 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
580 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
581 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
582 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
583 DUMP_REG(DC_DISP_M0_CONTROL);
584 DUMP_REG(DC_DISP_M1_CONTROL);
585 DUMP_REG(DC_DISP_DI_CONTROL);
586 DUMP_REG(DC_DISP_PP_CONTROL);
587 DUMP_REG(DC_DISP_PP_SELECT_A);
588 DUMP_REG(DC_DISP_PP_SELECT_B);
589 DUMP_REG(DC_DISP_PP_SELECT_C);
590 DUMP_REG(DC_DISP_PP_SELECT_D);
591 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
592 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
593 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
594 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
595 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
596 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
597 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
598 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
599 DUMP_REG(DC_DISP_BORDER_COLOR);
601 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
602 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
603 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
604 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
605 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
606 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
607 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
608 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
609 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
610 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
611 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
613 DUMP_REG(DC_DISP_CURSOR_POSITION);
614 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
615 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
616 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
617 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
618 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
619 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
620 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
621 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
622 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
623 DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
624 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
625 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
627 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
628 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
629 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_TEGRA_DC_INTERLACE)
630 DUMP_REG(DC_DISP_INTERLACE_CONTROL);
631 DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
632 DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
633 DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
634 DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
635 DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
637 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
639 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
642 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
643 DC_CMD_DISPLAY_WINDOW_HEADER);
644 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
645 DUMP_REG(DC_WIN_WIN_OPTIONS);
646 DUMP_REG(DC_WIN_BYTE_SWAP);
647 DUMP_REG(DC_WIN_BUFFER_CONTROL);
648 DUMP_REG(DC_WIN_COLOR_DEPTH);
649 DUMP_REG(DC_WIN_POSITION);
650 DUMP_REG(DC_WIN_SIZE);
651 DUMP_REG(DC_WIN_PRESCALED_SIZE);
652 DUMP_REG(DC_WIN_H_INITIAL_DDA);
653 DUMP_REG(DC_WIN_V_INITIAL_DDA);
654 DUMP_REG(DC_WIN_DDA_INCREMENT);
655 DUMP_REG(DC_WIN_LINE_STRIDE);
656 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
657 DUMP_REG(DC_WIN_BUF_STRIDE);
658 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
660 DUMP_REG(DC_WIN_BLEND_NOKEY);
661 DUMP_REG(DC_WIN_BLEND_1WIN);
662 DUMP_REG(DC_WIN_BLEND_2WIN_X);
663 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
664 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
665 DUMP_REG(DC_WINBUF_START_ADDR);
666 DUMP_REG(DC_WINBUF_START_ADDR_U);
667 DUMP_REG(DC_WINBUF_START_ADDR_V);
668 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
669 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
670 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
671 DUMP_REG(DC_WINBUF_START_ADDR_HI);
672 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
673 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
674 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
675 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
676 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
677 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
678 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
679 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
680 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
681 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
683 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
684 DUMP_REG(DC_WIN_CSC_YOF);
685 DUMP_REG(DC_WIN_CSC_KYRGB);
686 DUMP_REG(DC_WIN_CSC_KUR);
687 DUMP_REG(DC_WIN_CSC_KVR);
688 DUMP_REG(DC_WIN_CSC_KUG);
689 DUMP_REG(DC_WIN_CSC_KVG);
690 DUMP_REG(DC_WIN_CSC_KUB);
691 DUMP_REG(DC_WIN_CSC_KVB);
694 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
695 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
696 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
697 DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
698 DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
699 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
700 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
701 DUMP_REG(DC_DISP_M1_CONTROL);
702 DUMP_REG(DC_COM_PM1_CONTROL);
703 DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
704 DUMP_REG(DC_DISP_SD_CONTROL);
705 #ifdef CONFIG_TEGRA_DC_CMU
706 DUMP_REG(DC_COM_CMU_CSC_KRR);
707 DUMP_REG(DC_COM_CMU_CSC_KGR);
708 DUMP_REG(DC_COM_CMU_CSC_KBR);
709 DUMP_REG(DC_COM_CMU_CSC_KRG);
710 DUMP_REG(DC_COM_CMU_CSC_KGG);
711 DUMP_REG(DC_COM_CMU_CSC_KBR);
712 DUMP_REG(DC_COM_CMU_CSC_KRB);
713 DUMP_REG(DC_COM_CMU_CSC_KGB);
714 DUMP_REG(DC_COM_CMU_CSC_KBB);
718 mutex_unlock(&dc->lock);
724 static void dump_regs_print(void *data, const char *str)
726 struct tegra_dc *dc = data;
727 dev_dbg(&dc->ndev->dev, "%s", str);
730 static void dump_regs(struct tegra_dc *dc)
732 _dump_regs(dc, dc, dump_regs_print);
736 static void dump_regs(struct tegra_dc *dc) {}
740 #ifdef CONFIG_DEBUG_FS
742 static void dbg_regs_print(void *data, const char *str)
744 struct seq_file *s = data;
746 seq_printf(s, "%s", str);
751 static int dbg_dc_show(struct seq_file *s, void *unused)
753 struct tegra_dc *dc = s->private;
755 _dump_regs(dc, s, dbg_regs_print);
761 static int dbg_dc_open(struct inode *inode, struct file *file)
763 return single_open(file, dbg_dc_show, inode->i_private);
766 static const struct file_operations regs_fops = {
770 .release = single_release,
773 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
775 struct tegra_dc *dc = s->private;
776 struct tegra_dc_mode *m;
778 mutex_lock(&dc->lock);
782 "h_ref_to_sync: %d\n"
783 "v_ref_to_sync: %d\n"
790 "h_front_porch: %d\n"
791 "v_front_porch: %d\n"
793 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
794 m->h_sync_width, m->v_sync_width,
795 m->h_back_porch, m->v_back_porch,
796 m->h_active, m->v_active,
797 m->h_front_porch, m->v_front_porch,
799 mutex_unlock(&dc->lock);
803 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
805 return single_open(file, dbg_dc_mode_show, inode->i_private);
808 static const struct file_operations mode_fops = {
809 .open = dbg_dc_mode_open,
812 .release = single_release,
815 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
817 struct tegra_dc *dc = s->private;
819 mutex_lock(&dc->lock);
822 "underflows_a: %llu\n"
823 "underflows_b: %llu\n"
824 "underflows_c: %llu\n",
825 dc->stats.underflows,
826 dc->stats.underflows_a,
827 dc->stats.underflows_b,
828 dc->stats.underflows_c);
829 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
831 "underflows_d: %llu\n"
832 "underflows_h: %llu\n"
833 "underflows_t: %llu\n",
834 dc->stats.underflows_d,
835 dc->stats.underflows_h,
836 dc->stats.underflows_t);
838 mutex_unlock(&dc->lock);
843 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
845 return single_open(file, dbg_dc_stats_show, inode->i_private);
848 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
853 static ssize_t dbg_dc_event_inject_write(struct file *file,
854 const char __user *addr, size_t len, loff_t *pos)
856 struct seq_file *m = file->private_data; /* single_open() initialized */
857 struct tegra_dc *dc = m ? m->private : NULL;
864 ret = kstrtol_from_user(addr, len, 10, &event);
868 if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG */
869 tegra_dc_ext_process_hotplug(dc->ndev->id);
870 else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
871 tegra_dc_ext_process_bandwidth_renegotiate(
874 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
875 return -EINVAL; /* unknown event number */
880 static const struct file_operations stats_fops = {
881 .open = dbg_dc_stats_open,
884 .release = single_release,
887 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
889 return single_open(file, dbg_dc_event_inject_show, inode->i_private);
892 static const struct file_operations event_inject_fops = {
893 .open = dbg_dc_event_inject_open,
895 .write = dbg_dc_event_inject_write,
897 .release = single_release,
900 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
903 debugfs_remove_recursive(dc->debugdir);
907 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
909 struct dentry *retval;
911 dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
915 retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
920 retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
925 retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
930 retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
937 dev_err(&dc->ndev->dev, "could not create debugfs\n");
938 tegra_dc_remove_debugfs(dc);
941 #else /* !CONFIG_DEBUGFS */
942 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
943 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
944 #endif /* CONFIG_DEBUGFS */
946 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
947 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
949 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
953 usleep_range(poll_interval_us, poll_interval_us << 1);
954 reg_val = tegra_dc_readl(dc, reg);
955 } while (((reg_val & mask) != exp_val) &&
956 time_after(timeout_jf, jiffies));
958 if ((reg_val & mask) == exp_val)
959 return 0; /* success */
960 dev_err(&dc->ndev->dev,
961 "dc_poll_register 0x%x: timeout\n", reg);
962 return jiffies - timeout_jf + 1;
965 static int tegra_dc_set(struct tegra_dc *dc, int index)
969 mutex_lock(&tegra_dc_lock);
970 if (index >= TEGRA_MAX_DC) {
975 if (dc != NULL && tegra_dcs[index] != NULL) {
980 tegra_dcs[index] = dc;
983 mutex_unlock(&tegra_dc_lock);
988 unsigned int tegra_dc_has_multiple_dc(void)
991 unsigned int cnt = 0;
994 mutex_lock(&tegra_dc_lock);
995 for (idx = 0; idx < TEGRA_MAX_DC; idx++)
996 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
997 mutex_unlock(&tegra_dc_lock);
1002 /* get the stride size of a window.
1003 * return: stride size in bytes for window win. or 0 if unavailble. */
1004 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1010 BUG_ON(win > DC_N_WINDOWS);
1011 mutex_lock(&dc->lock);
1013 tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1014 DC_CMD_DISPLAY_WINDOW_HEADER);
1015 stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1017 mutex_unlock(&dc->lock);
1018 return GET_LINE_STRIDE(stride);
1020 EXPORT_SYMBOL(tegra_dc_get_stride);
1022 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
1024 if (idx < TEGRA_MAX_DC)
1025 return tegra_dcs[idx];
1029 EXPORT_SYMBOL(tegra_dc_get_dc);
1031 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
1033 if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
1036 return &dc->windows[win];
1038 EXPORT_SYMBOL(tegra_dc_get_window);
1040 bool tegra_dc_get_connected(struct tegra_dc *dc)
1042 return dc->connected;
1044 EXPORT_SYMBOL(tegra_dc_get_connected);
1046 bool tegra_dc_hpd(struct tegra_dc *dc)
1052 if (WARN_ON(!dc || !dc->out))
1055 if (dc->out->hotplug_state != 0) {
1056 if (dc->out->hotplug_state == 1) /* force on */
1058 if (dc->out->hotplug_state == -1) /* force off */
1061 level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
1063 sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
1065 hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
1066 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
1068 if (dc->out->hotplug_report)
1069 dc->out->hotplug_report(hpd);
1073 EXPORT_SYMBOL(tegra_dc_hpd);
1075 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1081 /* linear horizontal and vertical filters */
1082 for (i = 0; i < 16; i++) {
1083 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1084 DC_WIN_H_FILTER_P(i));
1086 tegra_dc_writel(dc, v0,
1087 DC_WIN_V_FILTER_P(i));
1093 #ifdef CONFIG_TEGRA_DC_CMU
1094 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
1095 struct tegra_dc_cmu *src_cmu)
1097 if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
1098 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
1099 dc->cmu_dirty = true;
1102 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1107 for (i = 0; i < 256; i++) {
1108 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1109 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1112 tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1113 tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1114 tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1115 tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1116 tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1117 tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1118 tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1119 tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1120 tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1122 for (i = 0; i < 960; i++) {
1123 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1124 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1127 dc->cmu_dirty = false;
1130 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1134 if (!dc->cmu_enabled)
1137 tegra_dc_cache_cmu(dc, cmu);
1139 if (dc->cmu_dirty) {
1140 /* Disable CMU to avoid programming it while it is in use */
1141 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1142 if (val & CMU_ENABLE) {
1144 tegra_dc_writel(dc, val,
1145 DC_DISP_DISP_COLOR_CONTROL);
1146 val = GENERAL_ACT_REQ;
1147 tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
1148 /*TODO: Sync up with vsync */
1151 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
1154 tegra_dc_set_cmu(dc, &dc->cmu);
1158 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1160 mutex_lock(&dc->lock);
1162 mutex_unlock(&dc->lock);
1168 _tegra_dc_update_cmu(dc, cmu);
1169 tegra_dc_set_color_control(dc);
1172 mutex_unlock(&dc->lock);
1176 EXPORT_SYMBOL(tegra_dc_update_cmu);
1178 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
1181 return dc->pdata->cmu;
1182 else if (dc->out->type == TEGRA_DC_OUT_HDMI)
1183 return &default_limited_cmu;
1185 return &default_cmu;
1188 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
1190 dc->cmu_enabled = cmu_enable;
1191 tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
1194 #define tegra_dc_cache_cmu(dc, src_cmu)
1195 #define tegra_dc_set_cmu(dc, cmu)
1196 #define tegra_dc_update_cmu(dc, cmu)
1199 /* disable_irq() blocks until handler completes, calling this function while
1200 * holding dc->lock can deadlock. */
1201 static inline void disable_dc_irq(const struct tegra_dc *dc)
1203 disable_irq(dc->irq);
1206 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1208 return dc->syncpt[i].id;
1210 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1212 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1216 mutex_lock(&dc->lock);
1218 max = nvhost_syncpt_incr_max_ext(dc->ndev,
1219 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1220 dc->syncpt[i].max = max;
1222 mutex_unlock(&dc->lock);
1227 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1229 mutex_lock(&dc->lock);
1232 while (dc->syncpt[i].min < val) {
1233 dc->syncpt[i].min++;
1234 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1237 mutex_unlock(&dc->lock);
1240 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
1242 struct nvhost_ctrl_sync_fence_info syncpt;
1243 u32 id = tegra_dc_get_syncpt_id(dc, i);
1246 syncpt.thresh = val;
1247 return nvhost_sync_create_fence(
1248 to_platform_device(dc->ndev->dev.parent),
1249 &syncpt, 1, dev_name(&dc->ndev->dev));
1253 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1256 unsigned long out_sel;
1257 unsigned long cmd_state;
1259 mutex_lock(&dc->lock);
1261 mutex_unlock(&dc->lock);
1267 ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1268 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1271 /* The new value should be effected immediately */
1272 cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1273 tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1275 switch (cfg->which_pwm) {
1277 /* Select the LM0 on PM0 */
1278 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1279 out_sel &= ~(7 << 0);
1280 out_sel |= (3 << 0);
1281 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1282 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1283 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1286 /* Select the LM1 on PM1 */
1287 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1288 out_sel &= ~(7 << 4);
1289 out_sel |= (3 << 4);
1290 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1291 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1292 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1295 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1298 tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1300 mutex_unlock(&dc->lock);
1302 EXPORT_SYMBOL(tegra_dc_config_pwm);
1304 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1305 const struct tegra_dc_out_pin *pins,
1306 const unsigned int n_pins)
1318 set1 = set3 = unset1 = unset3 = 0;
1320 for (i = 0; i < n_pins; i++) {
1321 name = (pins + i)->name;
1322 pol = (pins + i)->pol;
1324 /* set polarity by name */
1326 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1327 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1328 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1330 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1332 case TEGRA_DC_OUT_PIN_H_SYNC:
1333 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1334 set1 |= LHS_OUTPUT_POLARITY_LOW;
1336 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1338 case TEGRA_DC_OUT_PIN_V_SYNC:
1339 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1340 set1 |= LVS_OUTPUT_POLARITY_LOW;
1342 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1344 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1345 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1346 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1348 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1351 printk("Invalid argument in function %s\n",
1357 pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1358 pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1366 tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1367 tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1370 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1372 if (dc->out->type == TEGRA_DC_OUT_RGB ||
1373 dc->out->type == TEGRA_DC_OUT_HDMI ||
1374 dc->out->type == TEGRA_DC_OUT_DSI)
1375 return override_disp_mode[dc->out->type].pclk ?
1376 &override_disp_mode[dc->out->type] : NULL;
1381 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1383 struct tegra_dc_mode *mode;
1387 mode = tegra_dc_get_override_mode(dc);
1390 tegra_dc_set_mode(dc, mode);
1393 * Bootloader should and should only pass disp_params if
1394 * it has initialized display controller. Whenever we see
1395 * override modes, we should skip things cause display resets.
1397 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
1398 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
1399 dc->mode.h_active, dc->mode.v_active,
1400 dc->out->h_size, dc->out->v_size,
1402 dc->initialized = true;
1404 #ifdef CONFIG_TEGRA_DC_CMU
1406 * If the bootloader already set the mode, assume the CMU
1407 * parameters are also correctly set. It would be better to
1408 * read them, but unfortunately there is no reliable and
1409 * flicker-free way to do this!
1411 tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
1413 } else if (out->n_modes > 0)
1414 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1416 switch (out->type) {
1417 case TEGRA_DC_OUT_RGB:
1418 dc->out_ops = &tegra_dc_rgb_ops;
1421 case TEGRA_DC_OUT_HDMI:
1422 dc->out_ops = &tegra_dc_hdmi_ops;
1425 case TEGRA_DC_OUT_DSI:
1426 dc->out_ops = &tegra_dc_dsi_ops;
1429 #ifdef CONFIG_TEGRA_DP
1430 case TEGRA_DC_OUT_DP:
1431 dc->out_ops = &tegra_dc_dp_ops;
1433 #ifdef CONFIG_TEGRA_NVSR
1434 case TEGRA_DC_OUT_NVSR_DP:
1435 dc->out_ops = &tegra_dc_nvsr_ops;
1439 #ifdef CONFIG_TEGRA_LVDS
1440 case TEGRA_DC_OUT_LVDS:
1441 dc->out_ops = &tegra_dc_lvds_ops;
1449 if (dc->out_ops && dc->out_ops->init) {
1450 err = dc->out_ops->init(dc);
1454 dev_err(&dc->ndev->dev,
1455 "Error: out->type:%d out_ops->init() failed\n",
1464 /* returns on error: -EINVAL
1465 * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1466 int tegra_dc_get_out(const struct tegra_dc *dc)
1469 return dc->out->type;
1473 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1476 return dc->out->height;
1480 EXPORT_SYMBOL(tegra_dc_get_out_height);
1482 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1485 return dc->out->width;
1489 EXPORT_SYMBOL(tegra_dc_get_out_width);
1491 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1494 return dc->out->max_pixclock;
1498 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1500 void tegra_dc_enable_crc(struct tegra_dc *dc)
1504 mutex_lock(&dc->lock);
1507 val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1509 tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1510 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1512 mutex_unlock(&dc->lock);
1514 /* Register a client of frame_end interrupt */
1515 tegra_dc_config_frame_end_intr(dc, true);
1518 void tegra_dc_disable_crc(struct tegra_dc *dc)
1520 /* Unregister a client of frame_end interrupt */
1521 tegra_dc_config_frame_end_intr(dc, false);
1523 mutex_lock(&dc->lock);
1525 tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1526 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1529 mutex_unlock(&dc->lock);
1532 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1537 pr_err("Failed to get dc: NULL parameter.\n");
1541 /* If gated quitely return */
1542 if (!tegra_dc_is_powered(dc))
1545 INIT_COMPLETION(dc->crc_complete);
1546 if (dc->crc_pending &&
1547 wait_for_completion_interruptible(&dc->crc_complete)) {
1548 pr_err("CRC read interrupted.\n");
1552 mutex_lock(&dc->lock);
1554 crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1556 mutex_unlock(&dc->lock);
1561 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1565 if (tegra_platform_is_linsim())
1568 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1569 if (val & WIN_ALL_ACT_REQ)
1575 static inline void enable_dc_irq(const struct tegra_dc *dc)
1577 if (tegra_platform_is_fpga())
1578 /* Always disable DC interrupts on FPGA. */
1579 disable_irq(dc->irq);
1581 enable_irq(dc->irq);
1584 bool tegra_dc_has_vsync(struct tegra_dc *dc)
1586 return !!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE);
1589 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1593 /* Generally vsync comes at 60Hz (~16.67ms per cycle).
1594 * 2 time periods should be good enough for the timeout.
1595 * We add some margin here for the default timeout value.
1597 unsigned long timeout_ms = 40;
1599 if (dc->out->type == TEGRA_DC_OUT_DSI &&
1600 dc->out->dsi->rated_refresh_rate != 0)
1601 timeout_ms = 2 * DIV_ROUND_UP(1000,
1602 dc->out->dsi->rated_refresh_rate);
1604 mutex_lock(&dc->one_shot_lp_lock);
1606 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled) {
1607 mutex_unlock(&dc->one_shot_lp_lock);
1612 if (dc->out_ops && dc->out_ops->hold)
1613 dc->out_ops->hold(dc);
1616 * Logic is as follows
1617 * a) Indicate we need a vblank.
1618 * b) Wait for completion to be signalled from isr.
1619 * c) Initialize completion for next iteration.
1622 dc->out->user_needs_vblank = true;
1624 mutex_lock(&dc->lock);
1625 tegra_dc_unmask_interrupt(dc, MSF_INT);
1626 mutex_unlock(&dc->lock);
1628 ret = wait_for_completion_interruptible_timeout(
1629 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
1630 init_completion(&dc->out->user_vblank_comp);
1632 mutex_lock(&dc->lock);
1633 tegra_dc_mask_interrupt(dc, MSF_INT);
1634 mutex_unlock(&dc->lock);
1636 if (dc->out_ops && dc->out_ops->release)
1637 dc->out_ops->release(dc);
1640 mutex_unlock(&dc->one_shot_lp_lock);
1644 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1646 /* Do the actual brightness update outside of the mutex dc->lock */
1647 if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1648 dc->out->sd_settings->bl_device_name) {
1649 char *bl_device_name =
1650 dc->out->sd_settings->bl_device_name;
1651 dc->out->sd_settings->bl_device =
1652 get_backlight_device_by_name(bl_device_name);
1655 if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1656 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1657 backlight_update_status(bl);
1661 void tegra_dc_vsync_enable(struct tegra_dc *dc)
1663 mutex_lock(&dc->lock);
1664 set_bit(V_BLANK_USER, &dc->vblank_ref_count);
1665 tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1666 mutex_unlock(&dc->lock);
1669 void tegra_dc_vsync_disable(struct tegra_dc *dc)
1671 mutex_lock(&dc->lock);
1672 clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
1673 if (!dc->vblank_ref_count)
1674 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1675 mutex_unlock(&dc->lock);
1678 static void tegra_dc_vblank(struct work_struct *work)
1680 struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1681 bool nvsd_updated = false;
1683 mutex_lock(&dc->lock);
1686 mutex_unlock(&dc->lock);
1692 /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1693 if (!tegra_dc_windows_are_dirty(dc))
1694 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1696 /* Update the SD brightness */
1697 if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1698 nvsd_updated = nvsd_update_brightness(dc);
1699 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1700 * V_BLANK_NVSD bit of vblank ref-count. */
1702 set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1703 tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1705 clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1709 /* Mask vblank interrupt if ref-count is zero. */
1710 if (!dc->vblank_ref_count)
1711 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1714 mutex_unlock(&dc->lock);
1716 /* Do the actual brightness update outside of the mutex dc->lock */
1718 tegra_dc_prism_update_backlight(dc);
1721 static void tegra_dc_one_shot_worker(struct work_struct *work)
1723 struct tegra_dc *dc = container_of(
1724 to_delayed_work(work), struct tegra_dc, one_shot_work);
1725 mutex_lock(&dc->lock);
1727 /* memory client has gone idle */
1728 tegra_dc_clear_bandwidth(dc);
1730 if (dc->out_ops && dc->out_ops->idle) {
1731 tegra_dc_io_start(dc);
1732 dc->out_ops->idle(dc);
1733 tegra_dc_io_end(dc);
1736 mutex_unlock(&dc->lock);
1739 /* return an arbitrarily large number if count overflow occurs.
1740 * make it a nice base-10 number to show up in stats output */
1741 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1743 unsigned count = tegra_dc_readl(dc, reg);
1745 tegra_dc_writel(dc, 0, reg);
1746 return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1749 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1751 const u32 masks[] = {
1755 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1763 dc->stats.underflows++;
1764 if (dc->underflow_mask & WIN_A_UF_INT)
1765 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1766 DC_WINBUF_AD_UFLOW_STATUS);
1767 if (dc->underflow_mask & WIN_B_UF_INT)
1768 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1769 DC_WINBUF_BD_UFLOW_STATUS);
1770 if (dc->underflow_mask & WIN_C_UF_INT)
1771 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1772 DC_WINBUF_CD_UFLOW_STATUS);
1773 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1774 if (dc->underflow_mask & HC_UF_INT)
1775 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
1776 DC_WINBUF_HD_UFLOW_STATUS);
1777 if (dc->underflow_mask & WIN_D_UF_INT)
1778 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
1779 DC_WINBUF_DD_UFLOW_STATUS);
1780 if (dc->underflow_mask & WIN_T_UF_INT)
1781 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
1782 DC_WINBUF_TD_UFLOW_STATUS);
1785 /* Check for any underflow reset conditions */
1786 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1787 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
1788 "underflow stats unsupported"))
1789 break; /* bail if the table above is missing entries */
1791 continue; /* skip empty entries */
1793 if (dc->underflow_mask & masks[i]) {
1794 dc->windows[i].underflows++;
1796 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1797 if (i < 3 && dc->windows[i].underflows > 4) {
1798 schedule_work(&dc->reset_work);
1800 dc->windows[i].underflows = 0;
1801 trace_display_reset(dc);
1804 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1805 if (i < 3 && dc->windows[i].underflows > 4) {
1806 trace_display_reset(dc);
1807 tegra_dc_writel(dc, UF_LINE_FLUSH,
1808 DC_DISP_DISP_MISC_CONTROL);
1809 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1810 DC_CMD_STATE_CONTROL);
1812 tegra_dc_writel(dc, 0,
1813 DC_DISP_DISP_MISC_CONTROL);
1814 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1815 DC_CMD_STATE_CONTROL);
1819 dc->windows[i].underflows = 0;
1823 /* Clear the underflow mask now that we've checked it. */
1824 tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1825 dc->underflow_mask = 0;
1826 tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
1827 trace_underflow(dc);
1830 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1831 static void tegra_dc_vpulse2(struct work_struct *work)
1833 struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1834 bool nvsd_updated = false;
1836 mutex_lock(&dc->lock);
1839 mutex_unlock(&dc->lock);
1845 /* Clear the V_PULSE2_FLIP if no update */
1846 if (!tegra_dc_windows_are_dirty(dc))
1847 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1849 /* Update the SD brightness */
1850 if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1851 nvsd_updated = nvsd_update_brightness(dc);
1853 set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1854 tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1856 clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1860 /* Mask vpulse2 interrupt if ref-count is zero. */
1861 if (!dc->vpulse2_ref_count)
1862 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1865 mutex_unlock(&dc->lock);
1867 /* Do the actual brightness update outside of the mutex dc->lock */
1869 tegra_dc_prism_update_backlight(dc);
1873 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
1876 /* pending user vblank, so wakeup */
1877 if (status & (V_BLANK_INT | MSF_INT)) {
1878 if (dc->out->user_needs_vblank) {
1879 dc->out->user_needs_vblank = false;
1880 complete(&dc->out->user_vblank_comp);
1882 #ifdef CONFIG_ADF_TEGRA
1883 tegra_adf_process_vblank(dc->adf, timestamp);
1887 if (status & V_BLANK_INT) {
1888 /* Sync up windows. */
1889 tegra_dc_trigger_windows(dc);
1891 /* Schedule any additional bottom-half vblank actvities. */
1892 queue_work(system_freezable_wq, &dc->vblank_work);
1895 if (status & FRAME_END_INT) {
1896 /* Mark the frame_end as complete. */
1897 dc->crc_pending = false;
1898 if (!completion_done(&dc->frame_end_complete))
1899 complete(&dc->frame_end_complete);
1900 if (!completion_done(&dc->crc_complete))
1901 complete(&dc->crc_complete);
1903 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE && !dc->nvsr)
1907 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1908 if (status & V_PULSE2_INT)
1909 queue_work(system_freezable_wq, &dc->vpulse2_work);
1913 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
1916 /* Schedule any additional bottom-half vblank actvities. */
1917 if (status & V_BLANK_INT)
1918 queue_work(system_freezable_wq, &dc->vblank_work);
1920 #ifdef CONFIG_ADF_TEGRA
1921 if (status & (V_BLANK_INT | MSF_INT))
1922 tegra_adf_process_vblank(dc->adf, timestamp);
1925 if (status & FRAME_END_INT) {
1926 struct timespec tm = CURRENT_TIME;
1927 dc->frame_end_timestamp = timespec_to_ns(&tm);
1928 wake_up(&dc->timestamp_wq);
1930 /* Mark the frame_end as complete. */
1931 if (!completion_done(&dc->frame_end_complete))
1932 complete(&dc->frame_end_complete);
1933 if (!completion_done(&dc->crc_complete))
1934 complete(&dc->crc_complete);
1936 tegra_dc_trigger_windows(dc);
1939 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1940 if (status & V_PULSE2_INT)
1941 queue_work(system_freezable_wq, &dc->vpulse2_work);
1945 /* XXX: Not sure if we limit look ahead to 1 frame */
1946 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1948 BUG_ON(!dc->frametime_ns);
1949 return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1952 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1954 BUG_ON(!dc->frametime_ns);
1955 return (((new_ts - old_ts) > dc->frametime_ns)
1956 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1957 != div_s64((old_ts - dc->frame_end_timestamp),
1958 dc->frametime_ns)));
1961 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1963 ktime_t timestamp = ktime_get();
1964 struct tegra_dc *dc = ptr;
1965 unsigned long status;
1966 unsigned long underflow_mask;
1968 int need_disable = 0;
1970 if (tegra_platform_is_fpga())
1973 mutex_lock(&dc->lock);
1974 if (!tegra_dc_is_powered(dc)) {
1975 mutex_unlock(&dc->lock);
1981 if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
1982 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
1983 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1984 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1986 mutex_unlock(&dc->lock);
1990 /* clear all status flags except underflow, save those for the worker */
1991 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1992 tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
1993 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1994 tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
1997 * Overlays can get thier internal state corrupted during and underflow
1998 * condition. The only way to fix this state is to reset the DC.
1999 * if we get 4 consecutive frames with underflows, assume we're
2002 underflow_mask = status & ALL_UF_INT();
2004 /* Check underflow */
2005 if (underflow_mask) {
2006 dc->underflow_mask |= underflow_mask;
2007 schedule_delayed_work(&dc->underflow_work,
2008 msecs_to_jiffies(1));
2011 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2012 tegra_dc_one_shot_irq(dc, status, timestamp);
2014 tegra_dc_continuous_irq(dc, status, timestamp);
2017 tegra_dc_nvsr_irq(dc->nvsr, status);
2019 /* update video mode if it has changed since the last frame */
2020 if (status & (FRAME_END_INT | V_BLANK_INT))
2021 if (tegra_dc_update_mode(dc))
2022 need_disable = 1; /* force display off on error */
2024 if (status & FRAME_END_INT)
2025 if (dc->disp_active_dirty) {
2026 tegra_dc_writel(dc, dc->mode.h_active |
2027 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
2029 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2031 dc->disp_active_dirty = false;
2035 mutex_unlock(&dc->lock);
2038 tegra_dc_disable_nosync(dc);
2042 void tegra_dc_set_color_control(struct tegra_dc *dc)
2046 switch (dc->out->depth) {
2048 color_control = BASE_COLOR_SIZE111;
2052 color_control = BASE_COLOR_SIZE222;
2056 color_control = BASE_COLOR_SIZE332;
2060 color_control = BASE_COLOR_SIZE333;
2064 color_control = BASE_COLOR_SIZE444;
2068 color_control = BASE_COLOR_SIZE555;
2072 color_control = BASE_COLOR_SIZE565;
2076 color_control = BASE_COLOR_SIZE666;
2080 color_control = BASE_COLOR_SIZE888;
2084 switch (dc->out->dither) {
2085 case TEGRA_DC_UNDEFINED_DITHER:
2086 case TEGRA_DC_DISABLE_DITHER:
2087 color_control |= DITHER_CONTROL_DISABLE;
2089 case TEGRA_DC_ORDERED_DITHER:
2090 color_control |= DITHER_CONTROL_ORDERED;
2092 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
2093 case TEGRA_DC_TEMPORAL_DITHER:
2094 color_control |= DITHER_CONTROL_TEMPORAL;
2097 case TEGRA_DC_ERRDIFF_DITHER:
2098 /* The line buffer for error-diffusion dither is limited
2099 * to 1280 pixels per line. This limits the maximum
2100 * horizontal active area size to 1280 pixels when error
2101 * diffusion is enabled.
2103 BUG_ON(dc->mode.h_active > 1280);
2104 color_control |= DITHER_CONTROL_ERRDIFF;
2108 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
2111 #ifdef CONFIG_TEGRA_DC_CMU
2112 if (dc->cmu_enabled)
2113 color_control |= CMU_ENABLE;
2116 tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2119 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2121 if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
2122 return dc->win_syncpt[idx];
2126 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
2128 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2132 val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
2133 tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
2135 start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
2136 dc->mode.v_back_porch + dc->mode.v_active;
2138 val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
2139 tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
2141 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2142 val |= V_PULSE2_INT;
2143 tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
2145 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2146 tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2150 static int tegra_dc_init(struct tegra_dc *dc)
2156 tegra_dc_io_start(dc);
2157 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2158 if (dc->ndev->id == 0) {
2159 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2161 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2163 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2165 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2166 /* only present on Tegra2 and 3 */
2167 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2170 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2171 TEGRA_MC_PRIO_HIGH);
2172 } else if (dc->ndev->id == 1) {
2173 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2175 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2177 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2179 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2180 /* only present on Tegra2 and 3 */
2181 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2184 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2185 TEGRA_MC_PRIO_HIGH);
2187 tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2188 DC_CMD_CONT_SYNCPT_VSYNC);
2190 tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2191 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
2192 tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2193 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
2194 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2195 DC_CMD_INT_POLARITY);
2197 tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2198 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2199 DC_CMD_INT_POLARITY);
2201 tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2202 tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2203 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2204 tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2206 /* enable interrupts for vblank, frame_end and underflows */
2207 int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
2208 /* for panels with one-shot mode enable tearing effect interrupt */
2209 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2210 int_enable |= MSF_INT;
2212 tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
2213 tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
2214 tegra_dc_init_vpulse2_int(dc);
2216 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
2217 tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2219 tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
2222 #ifdef CONFIG_TEGRA_DC_CMU
2223 _tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2225 tegra_dc_set_color_control(dc);
2226 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2227 struct tegra_dc_win *win = &dc->windows[i];
2228 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2229 DC_CMD_DISPLAY_WINDOW_HEADER);
2230 tegra_dc_set_csc(dc, &win->csc);
2231 tegra_dc_set_lut(dc, win);
2232 tegra_dc_set_scaling_filter(dc);
2235 #ifdef CONFIG_TEGRA_DC_WIN_H
2236 /* Window H is set to window mode by default for t14x. */
2237 tegra_dc_writel(dc, WINH_CURS_SELECT(1),
2238 DC_DISP_BLEND_CURSOR_CONTROL);
2241 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2242 u32 syncpt = get_syncpt(dc, i);
2244 /* refuse to operate on invalid syncpts */
2245 if (WARN_ON(syncpt == NVSYNCPT_INVALID))
2248 dc->syncpt[i].id = syncpt;
2250 if (!nvhost_syncpt_read_ext_check(dc->ndev, syncpt, &val))
2251 dc->syncpt[i].min = dc->syncpt[i].max = val;
2254 dc->crc_pending = false;
2256 trace_display_mode(dc, &dc->mode);
2258 if (dc->mode.pclk) {
2259 if (!dc->initialized) {
2260 if (tegra_dc_program_mode(dc, &dc->mode)) {
2261 tegra_dc_io_end(dc);
2262 dev_warn(&dc->ndev->dev,
2263 "%s: tegra_dc_program_mode failed\n",
2268 dev_info(&dc->ndev->dev, "DC initialized, "
2269 "skipping tegra_dc_program_mode.\n");
2273 /* Initialize SD AFTER the modeset.
2274 nvsd_init handles the sd_settings = NULL case. */
2275 nvsd_init(dc, dc->out->sd_settings);
2277 tegra_dc_io_end(dc);
2282 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2284 int failed_init = 0;
2287 if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2290 tegra_dc_unpowergate_locked(dc);
2292 if (dc->out->enable)
2293 dc->out->enable(&dc->ndev->dev);
2295 tegra_dc_setup_clk(dc, dc->clk);
2297 /* dc clk always on for continuous mode */
2298 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2299 tegra_dc_clk_enable(dc);
2301 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
2305 tegra_dc_power_on(dc);
2307 /* do not accept interrupts during initialization */
2308 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2312 failed_init = tegra_dc_init(dc);
2314 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2315 disable_irq_nosync(dc->irq);
2316 tegra_dc_clear_bandwidth(dc);
2317 if (dc->out && dc->out->disable)
2320 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2321 tegra_dc_clk_disable(dc);
2323 tegra_dvfs_set_rate(dc->clk, 0);
2324 dev_warn(&dc->ndev->dev,
2325 "%s: tegra_dc_init failed\n", __func__);
2329 tegra_dpaux_pad_power(dc, false);
2331 if (dc->out_ops && dc->out_ops->enable)
2332 dc->out_ops->enable(dc);
2334 /* force a full blending update */
2335 for (i = 0; i < DC_N_WINDOWS; i++)
2336 dc->blend.z[i] = -1;
2338 tegra_dc_ext_enable(dc->ext);
2340 /* initialize cursor to defaults, as driver depends on HW state */
2341 tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
2342 tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
2343 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2344 tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
2345 tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
2347 tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
2348 tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
2349 tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
2350 tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
2351 tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
2353 trace_display_enable(dc);
2355 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2357 if (dc->out->postpoweron)
2358 dc->out->postpoweron(&dc->ndev->dev);
2360 if (dc->out_ops && dc->out_ops->postpoweron)
2361 dc->out_ops->postpoweron(dc);
2363 tegra_log_resume_time();
2365 * We will need to reinitialize the display the next time panel
2368 dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2375 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2376 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2380 if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2383 if (dc->out->enable)
2384 dc->out->enable(&dc->ndev->dev);
2386 tegra_dc_setup_clk(dc, dc->clk);
2387 tegra_dc_clk_enable(dc);
2389 if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2390 mutex_lock(&tegra_dcs[1]->lock);
2391 disable_irq_nosync(tegra_dcs[1]->irq);
2392 } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2393 mutex_lock(&tegra_dcs[0]->lock);
2394 disable_irq_nosync(tegra_dcs[0]->irq);
2398 tegra_periph_reset_assert(dc->clk);
2400 if (tegra_platform_is_silicon()) {
2401 tegra_periph_reset_deassert(dc->clk);
2405 if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2406 enable_dc_irq(tegra_dcs[1]);
2407 mutex_unlock(&tegra_dcs[1]->lock);
2408 } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2409 enable_dc_irq(tegra_dcs[0]);
2410 mutex_unlock(&tegra_dcs[0]->lock);
2415 if (tegra_dc_init(dc)) {
2416 dev_err(&dc->ndev->dev, "cannot initialize\n");
2420 if (dc->out_ops && dc->out_ops->enable)
2421 dc->out_ops->enable(dc);
2423 if (dc->out->postpoweron)
2424 dc->out->postpoweron(&dc->ndev->dev);
2426 /* force a full blending update */
2427 dc->blend.z[0] = -1;
2429 tegra_dc_ext_enable(dc->ext);
2432 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2433 _tegra_dc_controller_disable(dc);
2436 trace_display_reset(dc);
2441 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2443 if (dc->mode.pclk == 0) {
2444 switch (dc->out->type) {
2445 case TEGRA_DC_OUT_HDMI:
2446 /* If DC is enable called, and HDMI is connected,
2447 * but DC is not initialized by bootloader and no
2448 * mode is set up, then set a fallback mode.
2450 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
2451 return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2457 case TEGRA_DC_OUT_DP:
2458 case TEGRA_DC_OUT_NVSR_DP:
2459 return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2461 /* Do nothing for other outputs for now */
2462 case TEGRA_DC_OUT_RGB:
2464 case TEGRA_DC_OUT_DSI:
2474 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
2476 return _tegra_dc_set_default_videomode(dc);
2479 static bool _tegra_dc_enable(struct tegra_dc *dc)
2481 if (dc->mode.pclk == 0)
2490 pm_runtime_get_sync(&dc->ndev->dev);
2492 if (dc->out->type == TEGRA_DC_OUT_HDMI && !tegra_dc_hpd(dc))
2495 if (!_tegra_dc_controller_enable(dc)) {
2496 pm_runtime_put_sync(&dc->ndev->dev);
2503 void tegra_dc_enable(struct tegra_dc *dc)
2505 if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2508 mutex_lock(&dc->lock);
2511 dc->enabled = _tegra_dc_enable(dc);
2513 mutex_unlock(&dc->lock);
2514 trace_display_mode(dc, &dc->mode);
2517 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
2519 struct tegra_dc_win *w = &dc->windows[win];
2521 /* reset window bandwidth */
2523 w->new_bandwidth = 0;
2525 /* disable windows */
2526 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2528 /* refuse to operate on invalid syncpts */
2529 if (WARN_ON(dc->syncpt[win].id == NVSYNCPT_INVALID))
2532 /* flush any pending syncpt waits */
2533 dc->syncpt[win].max += 1;
2534 while (dc->syncpt[win].min < dc->syncpt[win].max) {
2535 trace_display_syncpt_flush(dc, dc->syncpt[win].id,
2536 dc->syncpt[win].min, dc->syncpt[win].max);
2537 dc->syncpt[win].min++;
2538 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[win].id);
2542 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2548 if (dc->out && dc->out->prepoweroff)
2549 dc->out->prepoweroff();
2551 if (dc->out_ops && dc->out_ops->disable)
2552 dc->out_ops->disable(dc);
2554 if (tegra_powergate_is_powered(dc->powergate_id))
2555 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2557 disable_irq_nosync(dc->irq);
2559 tegra_dc_clear_bandwidth(dc);
2561 if (dc->out && dc->out->disable)
2564 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2565 tegra_dc_disable_window(dc, i);
2567 trace_display_disable(dc);
2569 if (dc->out_ops && dc->out_ops->postpoweroff)
2570 dc->out_ops->postpoweroff(dc);
2574 /* disable always on dc clk in continuous mode */
2575 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2576 tegra_dc_clk_disable(dc);
2578 tegra_dvfs_set_rate(dc->clk, 0);
2581 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2583 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2586 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2588 val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2590 val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2591 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2596 bool tegra_dc_stats_get(struct tegra_dc *dc)
2598 #if 0 /* right now it is always enabled */
2603 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2604 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2614 /* blank selected windows by disabling them */
2615 void tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
2617 struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2619 unsigned long int blank_windows;
2622 blank_windows = windows & dc->valid_windows;
2627 for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
2628 dcwins[nr_win] = tegra_dc_get_window(dc, i);
2629 if (!dcwins[nr_win])
2631 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2634 tegra_dc_update_windows(dcwins, nr_win, NULL);
2635 tegra_dc_sync_windows(dcwins, nr_win);
2636 tegra_dc_program_bandwidth(dc, true);
2639 int tegra_dc_restore(struct tegra_dc *dc)
2641 return tegra_dc_ext_restore(dc->ext);
2644 static void _tegra_dc_disable(struct tegra_dc *dc)
2646 #ifdef CONFIG_TEGRA_DC_CMU
2647 /* power down resets the registers, setting to true
2648 * causes CMU to be restored in tegra_dc_init(). */
2649 dc->cmu_dirty = true;
2652 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2653 mutex_lock(&dc->one_shot_lock);
2654 cancel_delayed_work_sync(&dc->one_shot_work);
2657 tegra_dc_io_start(dc);
2658 _tegra_dc_controller_disable(dc);
2659 tegra_dc_io_end(dc);
2661 tegra_dc_powergate_locked(dc);
2663 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2664 mutex_unlock(&dc->one_shot_lock);
2665 pm_runtime_put(&dc->ndev->dev);
2667 tegra_log_suspend_time();
2670 static void tegra_dc_disable_nosync(struct tegra_dc *dc)
2672 if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2675 tegra_dc_ext_disable(dc->ext);
2677 /* it's important that new underflow work isn't scheduled before the
2678 * lock is acquired. */
2679 cancel_delayed_work_sync(&dc->underflow_work);
2681 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2682 mutex_lock(&dc->one_shot_lp_lock);
2683 mutex_lock(&dc->lock);
2686 dc->enabled = false;
2687 dc->blanked = false;
2690 _tegra_dc_disable(dc);
2693 #ifdef CONFIG_SWITCH
2694 switch_set_state(&dc->modeset_switch, 0);
2696 mutex_unlock(&dc->lock);
2697 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2698 mutex_unlock(&dc->one_shot_lp_lock);
2699 trace_display_mode(dc, &dc->mode);
2701 /* disable pending clks due to uncompleted frames */
2702 while (tegra_is_clk_enabled(dc->clk))
2706 void tegra_dc_disable(struct tegra_dc *dc)
2708 if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2711 tegra_dc_ext_disable(dc->ext);
2713 /* it's important that new underflow work isn't scheduled before the
2714 * lock is acquired. */
2715 cancel_delayed_work_sync(&dc->underflow_work);
2717 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2718 mutex_lock(&dc->one_shot_lp_lock);
2719 mutex_lock(&dc->lock);
2722 dc->enabled = false;
2723 dc->blanked = false;
2726 _tegra_dc_disable(dc);
2729 #ifdef CONFIG_SWITCH
2730 switch_set_state(&dc->modeset_switch, 0);
2732 mutex_unlock(&dc->lock);
2733 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2734 mutex_unlock(&dc->one_shot_lp_lock);
2735 synchronize_irq(dc->irq);
2736 trace_display_mode(dc, &dc->mode);
2738 /* disable pending clks due to uncompleted frames */
2739 while (tegra_is_clk_enabled(dc->clk))
2743 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2744 static void tegra_dc_reset_worker(struct work_struct *work)
2746 struct tegra_dc *dc =
2747 container_of(work, struct tegra_dc, reset_work);
2749 unsigned long val = 0;
2751 mutex_lock(&shared_lock);
2753 dev_warn(&dc->ndev->dev,
2754 "overlay stuck in underflow state. resetting.\n");
2756 tegra_dc_ext_disable(dc->ext);
2758 mutex_lock(&dc->lock);
2760 if (dc->enabled == false)
2763 dc->enabled = false;
2768 val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2769 val &= ~(0x00000100);
2770 tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2773 * set DC to STOP mode
2775 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2779 _tegra_dc_controller_disable(dc);
2781 /* _tegra_dc_controller_reset_enable deasserts reset */
2782 _tegra_dc_controller_reset_enable(dc);
2786 /* reopen host read bus */
2787 val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2788 val &= ~(0x00000100);
2790 tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2793 mutex_unlock(&dc->lock);
2794 mutex_unlock(&shared_lock);
2795 trace_display_reset(dc);
2799 static void tegra_dc_underflow_worker(struct work_struct *work)
2801 struct tegra_dc *dc = container_of(
2802 to_delayed_work(work), struct tegra_dc, underflow_work);
2804 mutex_lock(&dc->lock);
2808 tegra_dc_underflow_handler(dc);
2811 mutex_unlock(&dc->lock);
2814 static void (*flip_callback)(void);
2815 static spinlock_t flip_callback_lock;
2816 static bool init_tegra_dc_flip_callback_called;
2818 static int __init init_tegra_dc_flip_callback(void)
2820 spin_lock_init(&flip_callback_lock);
2821 init_tegra_dc_flip_callback_called = true;
2825 pure_initcall(init_tegra_dc_flip_callback);
2827 int tegra_dc_set_flip_callback(void (*callback)(void))
2829 WARN_ON(!init_tegra_dc_flip_callback_called);
2831 spin_lock(&flip_callback_lock);
2832 flip_callback = callback;
2833 spin_unlock(&flip_callback_lock);
2837 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
2839 int tegra_dc_unset_flip_callback()
2841 spin_lock(&flip_callback_lock);
2842 flip_callback = NULL;
2843 spin_unlock(&flip_callback_lock);
2847 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
2849 void tegra_dc_call_flip_callback()
2851 spin_lock(&flip_callback_lock);
2854 spin_unlock(&flip_callback_lock);
2856 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
2858 #ifdef CONFIG_SWITCH
2859 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2861 struct tegra_dc *dc =
2862 container_of(sdev, struct tegra_dc, modeset_switch);
2865 return sprintf(buf, "offline\n");
2867 return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2871 static int tegra_dc_probe(struct platform_device *ndev)
2873 struct tegra_dc *dc;
2874 struct tegra_dc_mode *mode;
2875 struct tegra_dc_platform_data *dt_pdata = NULL;
2877 #ifndef CONFIG_TEGRA_ISOMGR
2878 struct clk *emc_clk;
2880 int isomgr_client_id = -1;
2882 struct device_node *np = ndev->dev.of_node;
2883 struct resource *res;
2884 struct resource dt_res;
2885 struct resource *base_res;
2886 struct resource *fb_mem = NULL;
2892 if (!np && !ndev->dev.platform_data) {
2893 dev_err(&ndev->dev, "no platform data\n");
2897 /* Specify parameters for the maximum physical segment size. */
2898 ndev->dev.dma_parms = &tegra_dc_dma_parameters;
2900 dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2902 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2907 dt_pdata = of_dc_parse_platform_data(ndev);
2908 if (dt_pdata == NULL)
2912 irq = of_irq_to_resource(np, 0, NULL);
2917 ret = of_address_to_resource(np, 0, &dt_res);
2921 if (dt_res.start == TEGRA_DISPLAY_BASE)
2923 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
2930 irq = platform_get_irq_byname(ndev, "irq");
2932 dev_err(&ndev->dev, "no irq\n");
2937 res = platform_get_resource_byname(ndev,
2938 IORESOURCE_MEM, "regs");
2940 dev_err(&ndev->dev, "no mem resource\n");
2946 base_res = request_mem_region(res->start, resource_size(res),
2949 dev_err(&ndev->dev, "request_mem_region failed\n");
2954 base = ioremap(res->start, resource_size(res));
2956 dev_err(&ndev->dev, "registers can't be mapped\n");
2958 goto err_release_resource_reg;
2961 for (i = 0; i < DC_N_WINDOWS; i++)
2962 dc->win_syncpt[i] = NVSYNCPT_INVALID;
2964 if (TEGRA_DISPLAY_BASE == res->start) {
2965 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2966 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp0_a");
2967 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp0_b");
2968 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp0_c");
2969 dc->valid_windows = 0x07;
2970 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2971 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
2972 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp0_h");
2973 dc->valid_windows |= 0x18;
2974 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2975 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
2976 dc->valid_windows |= 0x08;
2978 dc->powergate_id = TEGRA_POWERGATE_DISA;
2979 #ifdef CONFIG_TEGRA_ISOMGR
2980 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
2982 } else if (TEGRA_DISPLAY2_BASE == res->start) {
2983 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2984 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp1_a");
2985 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp1_b");
2986 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp1_c");
2987 dc->valid_windows = 0x07;
2988 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2989 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp1_h");
2990 dc->valid_windows |= 0x10;
2992 dc->powergate_id = TEGRA_POWERGATE_DISB;
2993 #ifdef CONFIG_TEGRA_ISOMGR
2994 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
2998 "Unknown base address %llx: unable to assign syncpt\n",
3003 struct resource of_fb_res;
3005 tegra_get_fb_resource(&of_fb_res);
3006 else /*ndev->id == 1*/
3007 tegra_get_fb2_resource(&of_fb_res);
3009 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
3010 if (fb_mem == NULL) {
3012 goto err_iounmap_reg;
3014 fb_mem->name = "fbmem";
3015 fb_mem->flags = IORESOURCE_MEM;
3016 fb_mem->start = (resource_size_t)of_fb_res.start;
3017 fb_mem->end = (resource_size_t)of_fb_res.end;
3019 fb_mem = platform_get_resource_byname(ndev,
3020 IORESOURCE_MEM, "fbmem");
3023 clk = clk_get(&ndev->dev, NULL);
3024 if (IS_ERR_OR_NULL(clk)) {
3025 dev_err(&ndev->dev, "can't get clock\n");
3027 goto err_iounmap_reg;
3031 dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
3032 /* Initialize one shot work delay, it will be assigned by dsi
3033 * according to refresh rate later. */
3034 dc->one_shot_delay_ms = 40;
3036 dc->base_res = base_res;
3040 dc->fb_mem = fb_mem;
3043 dc->pdata = ndev->dev.platform_data;
3045 dc->pdata = dt_pdata;
3049 mutex_init(&dc->lock);
3050 mutex_init(&dc->one_shot_lock);
3051 mutex_init(&dc->one_shot_lp_lock);
3052 init_completion(&dc->frame_end_complete);
3053 init_completion(&dc->crc_complete);
3054 init_waitqueue_head(&dc->wq);
3055 init_waitqueue_head(&dc->timestamp_wq);
3056 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3057 INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3059 INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3060 dc->vblank_ref_count = 0;
3061 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3062 INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
3064 dc->vpulse2_ref_count = 0;
3065 INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3066 INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3068 tegra_dc_init_lut_defaults(&dc->fb_lut);
3070 dc->n_windows = DC_N_WINDOWS;
3071 for (i = 0; i < DC_N_WINDOWS; i++) {
3072 struct tegra_dc_win *win = &dc->windows[i];
3073 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
3074 if (!test_bit(i, &dc->valid_windows))
3075 win->flags |= TEGRA_WIN_FLAG_INVALID;
3080 tegra_dc_init_csc_defaults(&win->csc);
3081 tegra_dc_init_lut_defaults(&win->lut);
3084 ret = tegra_dc_set(dc, ndev->id);
3086 dev_err(&ndev->dev, "can't add dc\n");
3090 platform_set_drvdata(ndev, dc);
3092 #ifdef CONFIG_SWITCH
3093 dc->modeset_switch.name = dev_name(&ndev->dev);
3094 dc->modeset_switch.state = 0;
3095 dc->modeset_switch.print_state = switch_modeset_print_mode;
3096 ret = switch_dev_register(&dc->modeset_switch);
3098 dev_err(&ndev->dev, "failed to register switch driver\n");
3101 tegra_dc_feature_register(dc);
3103 if (dc->pdata->default_out) {
3104 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3105 if (dc->pdata->default_out->hotplug_init)
3106 dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
3107 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3108 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
3110 dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
3115 "No default output specified. Leaving output disabled.\n");
3117 dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
3119 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3120 if (dc->out && dc->out->n_modes &&
3121 (dc->out->type == TEGRA_DC_OUT_HDMI)) {
3122 struct fb_monspecs specs;
3123 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
3124 if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
3125 struct tegra_dc_mode *dcmode = &dc->out->modes[0];
3126 dcmode->pclk = specs.modedb->pixclock;
3127 dcmode->pclk = PICOS2KHZ(dcmode->pclk);
3128 dcmode->pclk *= 1000;
3129 dcmode->h_ref_to_sync = 1;
3130 dcmode->v_ref_to_sync = 1;
3131 dcmode->h_sync_width = specs.modedb->hsync_len;
3132 dcmode->v_sync_width = specs.modedb->vsync_len;
3133 dcmode->h_back_porch = specs.modedb->left_margin;
3134 dcmode->v_back_porch = specs.modedb->upper_margin;
3135 dcmode->h_active = specs.modedb->xres;
3136 dcmode->v_active = specs.modedb->yres;
3137 dcmode->h_front_porch = specs.modedb->right_margin;
3138 dcmode->v_front_porch = specs.modedb->lower_margin;
3139 tegra_dc_set_mode(dc, dcmode);
3140 dc->pdata->fb->xres = dcmode->h_active;
3141 dc->pdata->fb->yres = dcmode->v_active;
3144 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3146 #ifndef CONFIG_TEGRA_ISOMGR
3148 * The emc is a shared clock, it will be set based on
3149 * the requirements for each user on the bus.
3151 emc_clk = clk_get(&ndev->dev, "emc");
3152 if (IS_ERR_OR_NULL(emc_clk)) {
3153 dev_err(&ndev->dev, "can't get emc clock\n");
3157 dc->emc_clk = emc_clk;
3160 dc->ext = tegra_dc_ext_register(ndev, dc);
3161 if (IS_ERR_OR_NULL(dc->ext)) {
3162 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3166 /* interrupt handler must be registered before tegra_fb_register() */
3167 if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
3168 dev_name(&ndev->dev), dc)) {
3169 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3171 goto err_disable_dc;
3175 tegra_pd_add_device(&ndev->dev);
3176 pm_runtime_use_autosuspend(&ndev->dev);
3177 pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
3178 pm_runtime_enable(&ndev->dev);
3180 #ifdef CONFIG_TEGRA_DC_CMU
3181 /* if bootloader leaves this head enabled, then skip CMU programming. */
3182 dc->cmu_dirty = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) == 0;
3183 dc->cmu_enabled = dc->pdata->cmu_enable;
3186 if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
3187 /* WAR: BL is putting DC in bad state for EDP configuration */
3188 if (dc->out->type == TEGRA_DC_OUT_DP ||
3189 dc->out->type == TEGRA_DC_OUT_NVSR_DP) {
3190 clk_prepare_enable(dc->clk);
3191 tegra_periph_reset_assert(dc->clk);
3193 tegra_periph_reset_deassert(dc->clk);
3195 clk_disable_unprepare(dc->clk);
3197 _tegra_dc_set_default_videomode(dc);
3198 dc->enabled = _tegra_dc_enable(dc);
3200 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
3201 /* BL or PG init will keep DISA unpowergated after booting.
3202 * Adding an extra powergate to balance the refcount
3203 * since _tegra_dc_enable() increases the refcount.
3205 if (dc->powergate_id == TEGRA_POWERGATE_DISA)
3206 tegra_dc_powergate_locked(dc);
3210 #ifdef CONFIG_TEGRA_ISOMGR
3211 if (isomgr_client_id == -1) {
3212 dc->isomgr_handle = NULL;
3214 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
3215 tegra_dc_calc_min_bandwidth(dc),
3216 tegra_dc_bandwidth_renegotiate, dc);
3217 if (IS_ERR(dc->isomgr_handle)) {
3218 dev_err(&dc->ndev->dev,
3219 "could not register isomgr. err=%ld\n",
3220 PTR_ERR(dc->isomgr_handle));
3224 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
3226 * Use maximum value so we can try to reserve as much as
3227 * needed until we are told by isomgr to backoff.
3229 dc->available_bw = UINT_MAX;
3233 tegra_dc_create_debugfs(dc);
3235 dev_info(&ndev->dev, "probed\n");
3237 if (dc->pdata->fb) {
3238 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
3241 WINDOW_A_SELECT << dc->pdata->fb->win,
3242 DC_CMD_DISPLAY_WINDOW_HEADER);
3244 fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3245 dc->pdata->fb->bits_per_pixel =
3246 tegra_dc_fmt_bpp(fmt);
3249 mode = tegra_dc_get_override_mode(dc);
3251 dc->pdata->fb->xres = mode->h_active;
3252 dc->pdata->fb->yres = mode->v_active;
3255 #ifdef CONFIG_ADF_TEGRA
3256 tegra_dc_io_start(dc);
3257 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb);
3258 tegra_dc_io_end(dc);
3260 if (IS_ERR(dc->adf)) {
3261 tegra_dc_io_start(dc);
3262 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
3264 tegra_dc_io_end(dc);
3265 if (IS_ERR_OR_NULL(dc->fb)) {
3267 dev_err(&ndev->dev, "failed to register fb\n");
3268 goto err_remove_debugfs;
3272 tegra_dc_io_start(dc);
3273 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3274 tegra_dc_io_end(dc);
3275 if (IS_ERR_OR_NULL(dc->fb)) {
3277 dev_err(&ndev->dev, "failed to register fb\n");
3278 goto err_remove_debugfs;
3283 #ifndef CONFIG_FRAMEBUFFER_CONSOLE
3284 if (dc->out && dc->out->hotplug_init)
3285 dc->out->hotplug_init(&ndev->dev);
3286 #endif /* !CONFIG_FRAMEBUFFER_CONSOLE */
3289 if (dc->out_ops->detect)
3290 dc->connected = dc->out_ops->detect(dc);
3292 dc->connected = true;
3295 dc->connected = false;
3297 /* Powergate display module when it's unconnected. */
3298 /* detect() function, if presetns, responsible for the powergate */
3299 if (!tegra_dc_get_connected(dc) &&
3300 !(dc->out_ops && dc->out_ops->detect))
3301 tegra_dc_powergate_locked(dc);
3303 tegra_dc_create_sysfs(&dc->ndev->dev);
3306 * Overriding the display mode only applies for modes set up during
3307 * boot. It should not apply for e.g. HDMI hotplug.
3309 dc->initialized = false;
3314 tegra_dc_remove_debugfs(dc);
3318 tegra_dc_ext_disable(dc->ext);
3319 tegra_dc_ext_unregister(dc->ext);
3321 mutex_lock(&dc->lock);
3323 _tegra_dc_disable(dc);
3324 dc->enabled = false;
3325 mutex_unlock(&dc->lock);
3326 #ifdef CONFIG_SWITCH
3327 switch_dev_unregister(&dc->modeset_switch);
3329 #ifdef CONFIG_TEGRA_ISOMGR
3330 tegra_isomgr_unregister(dc->isomgr_handle);
3340 release_resource(fb_mem);
3344 err_release_resource_reg:
3345 release_resource(base_res);
3352 static int tegra_dc_remove(struct platform_device *ndev)
3354 struct tegra_dc *dc = platform_get_drvdata(ndev);
3355 struct device_node *np = ndev->dev.of_node;
3357 tegra_dc_remove_sysfs(&dc->ndev->dev);
3358 tegra_dc_remove_debugfs(dc);
3361 tegra_fb_unregister(dc->fb);
3364 release_resource(dc->fb_mem);
3370 #ifdef CONFIG_ADF_TEGRA
3372 tegra_adf_unregister(dc->adf);
3375 tegra_dc_ext_disable(dc->ext);
3378 tegra_dc_ext_unregister(dc->ext);
3380 mutex_lock(&dc->lock);
3382 _tegra_dc_disable(dc);
3383 dc->enabled = false;
3384 mutex_unlock(&dc->lock);
3385 synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3387 #ifdef CONFIG_SWITCH
3388 switch_dev_unregister(&dc->modeset_switch);
3390 free_irq(dc->irq, dc);
3391 #ifdef CONFIG_TEGRA_ISOMGR
3392 if (dc->isomgr_handle) {
3393 tegra_isomgr_unregister(dc->isomgr_handle);
3394 dc->isomgr_handle = NULL;
3397 clk_put(dc->emc_clk);
3402 release_resource(dc->base_res);
3404 tegra_dc_set(NULL, ndev->id);
3410 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
3412 struct tegra_dc *dc = platform_get_drvdata(ndev);
3415 trace_display_suspend(dc);
3416 dev_info(&ndev->dev, "suspend\n");
3418 tegra_dc_ext_disable(dc->ext);
3420 tegra_dc_cursor_suspend(dc);
3421 mutex_lock(&dc->lock);
3422 ret = tegra_dc_io_start(dc);
3424 if (dc->out_ops && dc->out_ops->suspend)
3425 dc->out_ops->suspend(dc);
3428 _tegra_dc_disable(dc);
3430 dc->suspended = true;
3433 if (dc->out && dc->out->postsuspend) {
3434 dc->out->postsuspend();
3435 /* avoid resume event due to voltage falling on interfaces that
3436 * support hotplug wake. And only do this if a panel is
3437 * connected, if we are already disconnected, then no phantom
3438 * hotplug can occur by disabling the voltage.
3440 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
3441 && tegra_dc_get_connected(dc))
3446 tegra_dc_io_end(dc);
3448 #ifdef CONFIG_TEGRA_DC_CMU
3450 * CMU settings are lost when the DC goes to sleep. User-space will
3451 * perform a blank ioctl upon resume which will call tegra_dc_init()
3452 * and apply CMU settings again, but only if the cached values are
3453 * different from those specified. Clearing the cache here ensures
3454 * that this will happen.
3456 * It would be better to reapply the CMU settings in tegra_dc_resume(),
3457 * but color corruption sometimes happens if we do so and
3458 * tegra_dc_init() seems to be the only safe place for this.
3460 memset(&dc->cmu, 0, sizeof(dc->cmu));
3463 mutex_unlock(&dc->lock);
3464 synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3469 static int tegra_dc_resume(struct platform_device *ndev)
3471 struct tegra_dc *dc = platform_get_drvdata(ndev);
3473 trace_display_resume(dc);
3474 dev_info(&ndev->dev, "resume\n");
3476 mutex_lock(&dc->lock);
3477 dc->suspended = false;
3479 /* To pan the fb on resume */
3480 tegra_fb_pan_display_reset(dc->fb);
3483 dc->enabled = false;
3484 _tegra_dc_set_default_videomode(dc);
3485 dc->enabled = _tegra_dc_enable(dc);
3488 if (dc->out && dc->out->hotplug_init)
3489 dc->out->hotplug_init(&ndev->dev);
3491 if (dc->out_ops && dc->out_ops->resume)
3492 dc->out_ops->resume(dc);
3494 mutex_unlock(&dc->lock);
3495 tegra_dc_cursor_resume(dc);
3500 #endif /* CONFIG_PM */
3502 static void tegra_dc_shutdown(struct platform_device *ndev)
3504 struct tegra_dc *dc = platform_get_drvdata(ndev);
3506 if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3512 tegra_dc_disable(dc);
3515 extern int suspend_set(const char *val, struct kernel_param *kp)
3517 if (!strcmp(val, "dump"))
3518 dump_regs(tegra_dcs[0]);
3520 else if (!strcmp(val, "suspend"))
3521 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3522 else if (!strcmp(val, "resume"))
3523 tegra_dc_resume(tegra_dcs[0]->ndev);
3529 extern int suspend_get(char *buffer, struct kernel_param *kp)
3536 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3540 static struct of_device_id tegra_display_of_match[] = {
3541 {.compatible = "nvidia,tegra114-dc", },
3542 {.compatible = "nvidia,tegra124-dc", },
3547 struct platform_driver tegra_dc_driver = {
3550 .owner = THIS_MODULE,
3553 of_match_ptr(tegra_display_of_match),
3556 .probe = tegra_dc_probe,
3557 .remove = tegra_dc_remove,
3559 .suspend = tegra_dc_suspend,
3560 .resume = tegra_dc_resume,
3562 .shutdown = tegra_dc_shutdown,
3566 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
3571 for (i = 0; i < ARRAY_SIZE(params); i++) {
3572 if ((p = strsep(&options, ",")) != NULL) {
3574 params[i] = simple_strtoul(p, &p, 10);
3579 if ((mode->pclk = params[0]) == 0)
3582 mode->h_active = params[1];
3583 mode->v_active = params[2];
3584 mode->h_ref_to_sync = params[3];
3585 mode->v_ref_to_sync = params[4];
3586 mode->h_sync_width = params[5];
3587 mode->v_sync_width = params[6];
3588 mode->h_back_porch = params[7];
3589 mode->v_back_porch = params[8];
3590 mode->h_front_porch = params[9];
3591 mode->v_front_porch = params[10];
3596 static int __init tegra_dc_mode_override(char *str)
3598 char *p = str, *options;
3603 p = strstr(str, "hdmi:");
3606 options = strsep(&p, ";");
3607 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
3611 p = strstr(str, "rgb:");
3614 options = strsep(&p, ";");
3615 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
3619 p = strstr(str, "dsi:");
3622 options = strsep(&p, ";");
3623 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
3630 __setup("disp_params=", tegra_dc_mode_override);
3633 static int __init tegra_dc_module_init(void)
3635 int ret = tegra_dc_ext_module_init();
3638 return platform_driver_register(&tegra_dc_driver);
3641 static void __exit tegra_dc_module_exit(void)
3643 platform_driver_unregister(&tegra_dc_driver);
3644 tegra_dc_ext_module_exit();
3647 module_exit(tegra_dc_module_exit);
3648 module_init(tegra_dc_module_init);