2 * NVIDIA Tegra CSI Device
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
6 * Author: Bryan Wu <pengw@nvidia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/module.h>
18 #include <linux/of_graph.h>
19 #include <linux/platform_device.h>
21 #include <media/media-entity.h>
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/camera_common.h>
30 static int csi_get_clks(struct tegra_csi_device *csi,
31 struct platform_device *pdev)
33 csi->clk = devm_clk_get(&pdev->dev, "csi");
34 if (IS_ERR(csi->clk)) {
35 dev_err(&pdev->dev, "Failed to get csi clock\n");
36 return PTR_ERR(csi->clk);
39 csi->tpg_clk = devm_clk_get(&pdev->dev, "pll_d");
40 if (IS_ERR(csi->tpg_clk)) {
41 dev_err(&pdev->dev, "Failed to get tpg clock\n");
42 return PTR_ERR(csi->tpg_clk);
45 csi->cil[0] = devm_clk_get(&pdev->dev, "cilab");
46 if (IS_ERR(csi->cil[0])) {
47 dev_err(&pdev->dev, "Failed to get cilab clock\n");
48 return PTR_ERR(csi->cil[0]);
51 csi->cil[1] = devm_clk_get(&pdev->dev, "cilcd");
52 if (IS_ERR(csi->cil[1])) {
53 dev_err(&pdev->dev, "Failed to get cilcd clock\n");
54 return PTR_ERR(csi->cil[1]);
57 csi->cil[2] = devm_clk_get(&pdev->dev, "cile");
58 if (IS_ERR(csi->cil[2])) {
59 dev_err(&pdev->dev, "Failed to get cile clock\n");
60 return PTR_ERR(csi->cil[2]);
66 static int set_csi_properties(struct tegra_csi_device *csi,
67 struct platform_device *pdev)
69 struct camera_common_data *s_data = &csi->s_data[0];
72 * These values are only used for tpg mode
73 * With sensor, CSI power and clock info are provided
74 * by the sensor sub device
77 s_data->numlanes = 12;
78 csi->clk_freq = TEGRA_CLOCK_CSI_PORT_MAX;
81 int port_num = (s_data->numlanes >> 1);
82 csi->ports = devm_kzalloc(&pdev->dev,
83 (port_num * sizeof(struct tegra_csi_port)),
87 csi->num_ports = port_num;
93 void set_csi_portinfo(struct tegra_csi_device *csi,
94 unsigned int port, unsigned int numlanes)
96 struct camera_common_data *s_data = &csi->s_data[port];
98 s_data->csi_port = port;
99 s_data->numlanes = numlanes;
100 s_data->def_clk_freq = TEGRA_CLOCK_CSI_PORT_MAX;
101 csi->ports[port].lanes = numlanes;
103 EXPORT_SYMBOL(set_csi_portinfo);
105 static void set_csi_registers(struct tegra_csi_device *csi,
106 void __iomem *regbase)
110 csi->iomem[0] = (regbase + TEGRA_CSI_PIXEL_PARSER_0_BASE);
111 csi->iomem[1] = (regbase + TEGRA_CSI_PIXEL_PARSER_2_BASE);
112 csi->iomem[2] = (regbase + TEGRA_CSI_PIXEL_PARSER_4_BASE);
114 for (j = 0; j < 3; j++) {
115 for (i = 0; i < 2; i++) {
117 /* Initialize port register bases */
118 csi->ports[idx].pixel_parser = csi->iomem[j] +
119 i * TEGRA_CSI_PORT_OFFSET;
120 csi->ports[idx].cil = csi->iomem[j] +
121 TEGRA_CSI_CIL_OFFSET +
122 i * TEGRA_CSI_PORT_OFFSET;
123 csi->ports[idx].tpg = csi->iomem[j] +
124 TEGRA_CSI_TPG_OFFSET +
125 i * TEGRA_CSI_PORT_OFFSET;
127 csi->ports[idx].num = idx;
128 csi->ports[idx].lanes = 2;
133 static int clock_start(struct tegra_csi_device *csi,
134 struct clk *clk, unsigned int freq)
138 err = clk_prepare_enable(clk);
140 dev_err(csi->dev, "csi clk enable error %d\n", err);
141 err = clk_set_rate(clk, freq);
143 dev_err(csi->dev, "csi clk set rate error %d\n", err);
148 void tegra_csi_pad_control(struct tegra_csi_device *csi,
149 unsigned char *port_num, int enable)
154 for (i = 0; csi_port_is_valid(port_num[i]); i++) {
156 camera_common_dpd_disable(&csi->s_data[port]);
159 for (i = 0; csi_port_is_valid(port_num[i]); i++) {
161 camera_common_dpd_enable(&csi->s_data[port]);
165 EXPORT_SYMBOL(tegra_csi_pad_control);
167 int tegra_csi_channel_power(struct tegra_csi_device *csi,
168 unsigned char *port_num, int enable)
171 int i, cil_num, port;
174 for (i = 0; csi_port_is_valid(port_num[i]); i++) {
177 err = clock_start(csi,
178 csi->cil[cil_num], csi->clk_freq);
180 dev_err(csi->dev, "cil clk start error\n");
181 camera_common_dpd_disable(&csi->s_data[port]);
184 for (i = 0; csi_port_is_valid(port_num[i]); i++) {
187 camera_common_dpd_enable(&csi->s_data[port]);
188 clk_disable_unprepare(csi->cil[cil_num]);
194 EXPORT_SYMBOL(tegra_csi_channel_power);
196 int tegra_csi_power(struct tegra_csi_device *csi, int enable)
201 /* set clk and power */
202 err = clk_prepare_enable(csi->clk);
204 dev_err(csi->dev, "csi clk enable error\n");
207 err = clock_start(csi, csi->tpg_clk,
208 TEGRA_CLOCK_TPG_MAX);
210 dev_err(csi->dev, "tpg clk start error\n");
212 tegra_clk_cfg_ex(csi->tpg_clk,
213 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
214 tegra_clk_cfg_ex(csi->tpg_clk,
215 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
216 tegra_clk_cfg_ex(csi->tpg_clk,
217 TEGRA_CLK_MIPI_CSI_OUT_ENB, 0);
222 tegra_clk_cfg_ex(csi->tpg_clk,
223 TEGRA_CLK_MIPI_CSI_OUT_ENB, 1);
224 tegra_clk_cfg_ex(csi->tpg_clk,
225 TEGRA_CLK_PLLD_CSI_OUT_ENB, 0);
226 tegra_clk_cfg_ex(csi->tpg_clk,
227 TEGRA_CLK_PLLD_DSI_OUT_ENB, 0);
228 clk_disable_unprepare(csi->tpg_clk);
230 clk_disable_unprepare(csi->clk);
235 EXPORT_SYMBOL(tegra_csi_power);
238 * -----------------------------------------------------------------------------
239 * CSI Subdevice Video Operations
240 * -----------------------------------------------------------------------------
243 /* Test Pattern Generator setup */
244 void tegra_csi_tpg_start_streaming(struct tegra_csi_device *csi,
245 enum tegra_csi_port_num port_num)
247 csi->fops->soc_tpg_start_streaming(csi, port_num);
250 void tegra_csi_start_streaming(struct tegra_csi_device *csi,
251 enum tegra_csi_port_num port_num)
253 csi->fops->soc_start_streaming(csi, port_num);
255 EXPORT_SYMBOL(tegra_csi_start_streaming);
257 int tegra_csi_error(struct tegra_csi_device *csi,
258 enum tegra_csi_port_num port_num)
260 return csi->fops->soc_error(csi, port_num);
263 void tegra_csi_status(struct tegra_csi_device *csi,
264 enum tegra_csi_port_num port_num)
266 csi->fops->soc_status(csi, port_num);
268 EXPORT_SYMBOL(tegra_csi_status);
270 void tegra_csi_error_recover(struct tegra_csi_device *csi,
271 enum tegra_csi_port_num port_num)
273 csi->fops->soc_error_recover(csi, port_num);
276 void tegra_csi_stop_streaming(struct tegra_csi_device *csi,
277 enum tegra_csi_port_num port_num)
279 csi->fops->soc_stop_streaming(csi, port_num);
281 EXPORT_SYMBOL(tegra_csi_stop_streaming);
283 static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable)
285 struct tegra_csi_device *csi = to_csi(subdev);
286 struct tegra_channel *chan;
292 chan = subdev->host_priv;
293 for (index = 0; index < chan->valid_ports; index++) {
294 enum tegra_csi_port_num port_num = chan->port[index];
296 tegra_csi_start_streaming(csi, port_num);
298 tegra_csi_stop_streaming(csi, port_num);
305 * Only use this subdevice media bus ops for test pattern generator,
306 * because CSI device is an separated subdevice which has 6 source
307 * pads to generate test pattern.
309 static struct v4l2_mbus_framefmt tegra_csi_tpg_fmts[] = {
313 V4L2_MBUS_FMT_SRGGB10_1X10,
320 V4L2_MBUS_FMT_RGBA8888_4X8_LE,
327 static struct v4l2_frmsize_discrete tegra_csi_tpg_sizes[] = {
333 static int tegra_csi_enum_framesizes(struct v4l2_subdev *sd,
334 struct v4l2_frmsizeenum *sizes)
337 struct tegra_csi_device *csi = to_csi(sd);
340 dev_err(csi->dev, "CSI is not in TPG mode\n");
344 if (sizes->index >= ARRAY_SIZE(tegra_csi_tpg_sizes))
347 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) {
348 const struct tegra_video_format *format =
349 tegra_core_get_format_by_code(tegra_csi_tpg_fmts[i].code);
350 if (format && format->fourcc == sizes->pixel_format)
353 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts))
356 sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
357 sizes->discrete = tegra_csi_tpg_sizes[sizes->index];
361 #define TPG_PIXEL_OUTPUT_RATE 182476800
363 static int tegra_csi_enum_frameintervals(struct v4l2_subdev *sd,
364 struct v4l2_frmivalenum *intervals)
367 struct tegra_csi_device *csi = to_csi(sd);
370 dev_err(csi->dev, "CSI is not in TPG mode\n");
374 /* One resolution just one framerate */
375 if (intervals->index > 0)
378 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) {
379 const struct tegra_video_format *format =
380 tegra_core_get_format_by_code(tegra_csi_tpg_fmts[i].code);
381 if (format && format->fourcc == intervals->pixel_format)
384 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts))
387 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_sizes); i++) {
388 if (tegra_csi_tpg_sizes[i].width == intervals->width &&
389 tegra_csi_tpg_sizes[i].height == intervals->height)
392 if (i == ARRAY_SIZE(tegra_csi_tpg_sizes))
395 intervals->type = V4L2_FRMIVAL_TYPE_DISCRETE;
396 intervals->discrete.numerator = 1;
397 intervals->discrete.denominator = TPG_PIXEL_OUTPUT_RATE /
398 (intervals->width * intervals->height);
402 static int tegra_csi_try_mbus_fmt(struct v4l2_subdev *sd,
403 struct v4l2_mbus_framefmt *mf)
406 struct tegra_csi_device *csi = to_csi(sd);
407 static struct v4l2_frmsize_discrete *sizes;
410 dev_err(csi->dev, "CSI is not in TPG mode\n");
414 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) {
415 struct v4l2_mbus_framefmt *fmt = &tegra_csi_tpg_fmts[i];
416 if (mf->code == fmt->code && mf->field == fmt->field &&
417 mf->colorspace == fmt->colorspace) {
418 for (j = 0; j < ARRAY_SIZE(tegra_csi_tpg_sizes); j++) {
419 sizes = &tegra_csi_tpg_sizes[j];
420 if (mf->width == sizes->width &&
421 mf->height == sizes->height)
427 memcpy(mf, tegra_csi_tpg_fmts, sizeof(struct v4l2_mbus_framefmt));
432 static int tegra_csi_s_mbus_fmt(struct v4l2_subdev *sd,
433 struct v4l2_mbus_framefmt *fmt)
436 struct tegra_csi_device *csi = to_csi(sd);
439 dev_err(csi->dev, "CSI is not in TPG mode\n");
443 tegra_csi_try_mbus_fmt(sd, fmt);
445 for (i = 0; i < csi->num_ports; i++) {
446 struct v4l2_mbus_framefmt *format = &csi->ports[i].format;
447 memcpy(format, fmt, sizeof(struct v4l2_mbus_framefmt));
453 static int tegra_csi_g_mbus_fmt(struct v4l2_subdev *sd,
454 struct v4l2_mbus_framefmt *fmt)
456 return tegra_csi_try_mbus_fmt(sd, fmt);
459 static int tegra_csi_g_input_status(struct v4l2_subdev *sd, u32 *status)
461 struct tegra_csi_device *csi = to_csi(sd);
463 *status = !!csi->pg_mode;
468 /* -----------------------------------------------------------------------------
469 * V4L2 Subdevice Pad Operations
472 static int tegra_csi_get_format(struct v4l2_subdev *subdev,
473 struct v4l2_subdev_fh *cfg,
474 struct v4l2_subdev_format *fmt)
476 struct v4l2_mbus_framefmt mbus_fmt;
479 ret = tegra_csi_g_mbus_fmt(subdev, &mbus_fmt);
483 fmt->format = mbus_fmt;
488 static int tegra_csi_set_format(struct v4l2_subdev *subdev,
489 struct v4l2_subdev_fh *cfg,
490 struct v4l2_subdev_format *fmt)
493 struct tegra_csi_device *csi = to_csi(subdev);
495 ret = tegra_csi_try_mbus_fmt(subdev, &fmt->format);
499 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
502 for (i = 0; i < csi->num_ports; i++) {
503 struct v4l2_mbus_framefmt *format = &csi->ports[i].format;
504 memcpy(format, &fmt->format, sizeof(struct v4l2_mbus_framefmt));
510 /* -----------------------------------------------------------------------------
511 * V4L2 Subdevice Operations
513 static struct v4l2_subdev_video_ops tegra_csi_video_ops = {
514 .s_stream = tegra_csi_s_stream,
515 .try_mbus_fmt = tegra_csi_try_mbus_fmt,
516 .s_mbus_fmt = tegra_csi_s_mbus_fmt,
517 .g_mbus_fmt = tegra_csi_g_mbus_fmt,
518 .g_input_status = tegra_csi_g_input_status,
519 .enum_framesizes = tegra_csi_enum_framesizes,
520 .enum_frameintervals = tegra_csi_enum_frameintervals,
523 static struct v4l2_subdev_pad_ops tegra_csi_pad_ops = {
524 .get_fmt = tegra_csi_get_format,
525 .set_fmt = tegra_csi_set_format,
528 static struct v4l2_subdev_ops tegra_csi_ops = {
529 .video = &tegra_csi_video_ops,
530 .pad = &tegra_csi_pad_ops,
533 /* -----------------------------------------------------------------------------
537 static const struct media_entity_operations tegra_csi_media_ops = {
538 .link_validate = v4l2_subdev_link_validate,
541 /* -----------------------------------------------------------------------------
542 * Platform Device Driver
545 static int tegra_csi_parse_of(struct tegra_csi_device *csi,
546 struct platform_device *pdev)
548 struct device_node *node = csi->dev->of_node;
549 struct device_node *ports;
550 struct device_node *port;
551 struct device_node *ep;
552 unsigned int lanes, pad_num, port_num;
555 ret = of_property_read_u32(node, "num-ports", &port_num);
559 csi->ports = devm_kzalloc(&pdev->dev,
560 (port_num * sizeof(struct tegra_csi_port)), GFP_KERNEL);
563 csi->num_ports = port_num;
565 csi->pads = devm_kzalloc(&pdev->dev,
566 (port_num * 2 * sizeof(struct media_pad)), GFP_KERNEL);
570 ports = of_get_child_by_name(node, "ports");
574 for_each_child_of_node(ports, port) {
575 if (!port->name || of_node_cmp(port->name, "port"))
578 ret = of_property_read_u32(port, "reg", &pad_num);
581 port_num = (pad_num >> 1);
582 csi->ports[port_num].num = port_num;
584 for_each_child_of_node(port, ep) {
585 if (!ep->name || of_node_cmp(ep->name, "endpoint"))
588 /* Get number of data lanes for the first endpoint */
589 ret = of_property_read_u32(ep, "bus-width", &lanes);
592 csi->ports[port_num].lanes = lanes;
599 static int tegra_tpg_csi_parse_data(struct tegra_csi_device *csi,
600 struct platform_device *pdev)
604 csi->ports = devm_kzalloc(&pdev->dev,
605 (csi->num_ports * sizeof(struct tegra_csi_port)), GFP_KERNEL);
609 csi->pads = devm_kzalloc(&pdev->dev,
610 (csi->num_ports * sizeof(struct media_pad)), GFP_KERNEL);
614 for (i = 0; i < csi->num_ports; i++) {
615 csi->ports[i].num = i;
616 csi->ports[i].lanes = 2;
622 int tegra_csi_init(struct tegra_csi_device *csi,
623 struct platform_device *pdev)
626 struct nvhost_device_data *pdata = pdev->dev.platform_data;
628 csi->dev = &pdev->dev;
629 err = set_csi_properties(csi, pdev);
633 set_csi_registers(csi, pdata->aperture[0]);
635 err = csi_get_clks(csi, pdev);
637 dev_err(&pdev->dev, "Failed to get CSI clks\n");
641 EXPORT_SYMBOL(tegra_csi_init);
643 int tegra_csi_media_controller_init(struct tegra_csi_device *csi,
644 struct platform_device *pdev)
646 struct v4l2_subdev *subdev;
649 csi->dev = &pdev->dev;
652 ret = tegra_tpg_csi_parse_data(csi, pdev);
654 ret = tegra_csi_parse_of(csi, pdev);
658 ret = tegra_csi_init(csi, pdev);
662 /* Initialize V4L2 subdevice and media entity */
663 subdev = &csi->subdev;
664 v4l2_subdev_init(subdev, &tegra_csi_ops);
665 subdev->dev = &pdev->dev;
666 strlcpy(subdev->name, dev_name(&pdev->dev), sizeof(subdev->name));
667 v4l2_set_subdevdata(subdev, csi);
668 subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
669 subdev->entity.ops = &tegra_csi_media_ops;
671 for (i = 0; i < csi->num_ports; i++) {
672 /* Initialize the default format */
673 csi->ports[i].format.code = TEGRA_VF_DEF;
674 csi->ports[i].format.field = V4L2_FIELD_NONE;
675 csi->ports[i].format.colorspace = V4L2_COLORSPACE_SRGB;
676 csi->ports[i].format.width = TEGRA_DEF_WIDTH;
677 csi->ports[i].format.height = TEGRA_DEF_HEIGHT;
680 csi->pads[i].flags = MEDIA_PAD_FL_SOURCE;
682 csi->pads[i * 2].flags = MEDIA_PAD_FL_SINK;
683 csi->pads[i * 2 + 1].flags = MEDIA_PAD_FL_SOURCE;
687 /* Initialize media entity */
688 ret = media_entity_init(&subdev->entity,
689 csi->pg_mode ? csi->num_ports :
695 ret = v4l2_async_register_subdev(subdev);
697 dev_err(&pdev->dev, "failed to register subdev\n");
704 media_entity_cleanup(&subdev->entity);
707 EXPORT_SYMBOL(tegra_csi_media_controller_init);
709 int tegra_csi_media_controller_remove(struct tegra_csi_device *csi)
711 struct v4l2_subdev *subdev = &csi->subdev;
713 v4l2_async_unregister_subdev(subdev);
714 media_entity_cleanup(&subdev->entity);
717 EXPORT_SYMBOL(tegra_csi_media_controller_remove);