drivers/usb/host/xhci-tegra.c

   1 /*
   2  * xhci-tegra.c - Nvidia xHCI host controller driver
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/clk.h>
  24 #include <linux/ioport.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/irq.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/platform_data/tegra_usb.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/kthread.h>
  34 #include <linux/gpio.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-powergate.h>
  38 #include <linux/firmware.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/tegra-fuse.h>
  44 #include <linux/tegra_pm_domains.h>
  45
  46 #include <mach/tegra_usb_pad_ctrl.h>
  47 #include <mach/tegra_usb_pmc.h>
  48 #include <mach/mc.h>
  49 #include <mach/xusb.h>
  50
  51 #include "xhci-tegra.h"
  52 #include "xhci.h"
  53 #include "../../../arch/arm/mach-tegra/iomap.h"
  54
  55 /* macros */
  56 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
  57 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
  58 #define FW_IOCTL_DATA_SHIFT             (0)
  59 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
  60 #define FW_IOCTL_TYPE_SHIFT             (24)
  61 #define FW_IOCTL_TYPE_MASK              (0xff000000)
  62 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
  63 #define FW_LOG_COUNT                    (4096)
  64 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
  65 #define FW_LOG_PAYLOAD_SIZE             (27)
  66 #define DRIVER                          (0x01)
  67 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
  68 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
  69
  70 /* tegra_xhci_firmware_log.flags bits */
  71 #define FW_LOG_CONTEXT_VALID            (0)
  72 #define FW_LOG_FILE_OPENED              (1)
  73
  74 #define PAGE_SELECT_MASK                        0xFFFFFE00
  75 #define PAGE_SELECT_SHIFT                       9
  76 #define PAGE_OFFSET_MASK                        0x000001FF
  77 #define CSB_PAGE_SELECT(_addr)                                          \
  78         ({                                                              \
  79                 typecheck(u32, _addr);                                  \
  80                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
  81         })
  82 #define CSB_PAGE_OFFSET(_addr)                                          \
  83         ({                                                              \
  84                 typecheck(u32, _addr);                                  \
  85                 (_addr & PAGE_OFFSET_MASK);                             \
  86         })
  87
  88 #define reg_dump(_dev, _base, _reg)                                     \
  89         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
  90                 _reg, readl(_base + _reg))
  91
  92 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
  93 #define GET_SS_PORTMAP(map, p)          (((map) >> 4*(p)) & 0xF)
  94
  95 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
  96 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
  97 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
  98
  99 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
 100
 101 /* private data types */
 102 /* command requests from the firmware */
 103 enum MBOX_CMD_TYPE {
 104         MBOX_CMD_MSG_ENABLED = 1,
 105         MBOX_CMD_INC_FALC_CLOCK,
 106         MBOX_CMD_DEC_FALC_CLOCK,
 107         MBOX_CMD_INC_SSPI_CLOCK,
 108         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
 109         MBOX_CMD_SET_BW,
 110         MBOX_CMD_SET_SS_PWR_GATING,
 111         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
 112         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 113         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 114         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
 115         MBOX_CMD_STAR_HSIC_IDLE,
 116         MBOX_CMD_STOP_HSIC_IDLE,
 117         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 118         MBOX_CMD_HSIC_PRETEND_CONNECT,
 119
 120         /* needs to be the last cmd */
 121         MBOX_CMD_MAX,
 122
 123         /* resp msg to ack above commands */
 124         MBOX_CMD_ACK = 128,
 125         MBOX_CMD_NACK
 126 };
 127
 128 struct log_entry {
 129         u32 sequence_no;
 130         u8 data[FW_LOG_PAYLOAD_SIZE];
 131         u8 owner;
 132 };
 133
 134 /* Usb3 Firmware Cfg Table */
 135 struct cfgtbl {
 136         u32 boot_loadaddr_in_imem;
 137         u32 boot_codedfi_offset;
 138         u32 boot_codetag;
 139         u32 boot_codesize;
 140
 141         /* Physical memory reserved by Bootloader/BIOS */
 142         u32 phys_memaddr;
 143         u16 reqphys_memsize;
 144         u16 alloc_phys_memsize;
 145
 146         /* .rodata section */
 147         u32 rodata_img_offset;
 148         u32 rodata_section_start;
 149         u32 rodata_section_end;
 150         u32 main_fnaddr;
 151
 152         u32 fwimg_cksum;
 153         u32 fwimg_created_time;
 154
 155         /* Fields that get filled by linker during linking phase
 156          * or initialized in the FW code.
 157          */
 158         u32 imem_resident_start;
 159         u32 imem_resident_end;
 160         u32 idirect_start;
 161         u32 idirect_end;
 162         u32 l2_imem_start;
 163         u32 l2_imem_end;
 164         u32 version_id;
 165         u8 init_ddirect;
 166         u8 reserved[3];
 167         u32 phys_addr_log_buffer;
 168         u32 total_log_entries;
 169         u32 dequeue_ptr;
 170
 171         /*      Below two dummy variables are used to replace
 172          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
 173          *      retain the size of struct _CFG_TBL used by other AP/Module.
 174          */
 175         u32 dummy_var1;
 176         u32 dummy_var2;
 177
 178         /* fwimg_len */
 179         u32 fwimg_len;
 180         u8 magic[8];
 181         u32 SS_low_power_entry_timeout;
 182         u8 num_hsic_port;
 183         u8 ss_portmap;
 184         u8 padding[138]; /* padding bytes to makeup 256-bytes cfgtbl */
 185 };
 186
 187 struct xusb_save_regs {
 188         u32 msi_bar_sz;
 189         u32 msi_axi_barst;
 190         u32 msi_fpci_barst;
 191         u32 msi_vec0;
 192         u32 msi_en_vec0;
 193         u32 fpci_error_masks;
 194         u32 intr_mask;
 195         u32 ipfs_intr_enable;
 196         u32 ufpci_config;
 197         u32 clkgate_hysteresis;
 198         u32 xusb_host_mccif_fifo_cntrl;
 199
 200         /* PG does not mention below */
 201         u32 hs_pls;
 202         u32 fs_pls;
 203         u32 hs_fs_speed;
 204         u32 hs_fs_pp;
 205         u32 cfg_aru;
 206         u32 cfg_order;
 207         u32 cfg_fladj;
 208         u32 cfg_sid;
 209         /* DFE and CTLE */
 210         u32 tap1_val[XUSB_SS_PORT_COUNT];
 211         u32 amp_val[XUSB_SS_PORT_COUNT];
 212         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
 213         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
 214 };
 215
 216 struct tegra_xhci_firmware {
 217         void *data; /* kernel virtual address */
 218         size_t size; /* firmware size */
 219         dma_addr_t dma; /* dma address for controller */
 220 };
 221
 222 struct tegra_xhci_firmware_log {
 223         dma_addr_t phys_addr;           /* dma-able address */
 224         void *virt_addr;                /* kernel va of the shared log buffer */
 225         struct log_entry *dequeue;      /* current dequeue pointer (va) */
 226         struct circ_buf circ;           /* big circular buffer */
 227         u32 seq;                        /* log sequence number */
 228
 229         struct task_struct *thread;     /* a thread to consume log */
 230         struct mutex mutex;
 231         wait_queue_head_t read_wait;
 232         wait_queue_head_t write_wait;
 233         wait_queue_head_t intr_wait;
 234         struct dentry *path;
 235         struct dentry *log_file;
 236         unsigned long flags;
 237 };
 238
 239 /* structure to hold the offsets of padctl registers */
 240 struct tegra_xusb_padctl_regs {
 241         u16 boot_media_0;
 242         u16 usb2_pad_mux_0;
 243         u16 usb2_port_cap_0;
 244         u16 snps_oc_map_0;
 245         u16 usb2_oc_map_0;
 246         u16 ss_port_map_0;
 247         u16 oc_det_0;
 248         u16 elpg_program_0;
 249         u16 usb2_bchrg_otgpad0_ctl0_0;
 250         u16 usb2_bchrg_otgpad0_ctl1_0;
 251         u16 usb2_bchrg_otgpad1_ctl0_0;
 252         u16 usb2_bchrg_otgpad1_ctl1_0;
 253         u16 usb2_bchrg_otgpad2_ctl0_0;
 254         u16 usb2_bchrg_otgpad2_ctl1_0;
 255         u16 usb2_bchrg_bias_pad_0;
 256         u16 usb2_bchrg_tdcd_dbnc_timer_0;
 257         u16 iophy_pll_p0_ctl1_0;
 258         u16 iophy_pll_p0_ctl2_0;
 259         u16 iophy_pll_p0_ctl3_0;
 260         u16 iophy_pll_p0_ctl4_0;
 261         u16 iophy_usb3_pad0_ctl1_0;
 262         u16 iophy_usb3_pad1_ctl1_0;
 263         u16 iophy_usb3_pad0_ctl2_0;
 264         u16 iophy_usb3_pad1_ctl2_0;
 265         u16 iophy_usb3_pad0_ctl3_0;
 266         u16 iophy_usb3_pad1_ctl3_0;
 267         u16 iophy_usb3_pad0_ctl4_0;
 268         u16 iophy_usb3_pad1_ctl4_0;
 269         u16 iophy_misc_pad_p0_ctl1_0;
 270         u16 iophy_misc_pad_p1_ctl1_0;
 271         u16 iophy_misc_pad_p0_ctl2_0;
 272         u16 iophy_misc_pad_p1_ctl2_0;
 273         u16 iophy_misc_pad_p0_ctl3_0;
 274         u16 iophy_misc_pad_p1_ctl3_0;
 275         u16 iophy_misc_pad_p0_ctl4_0;
 276         u16 iophy_misc_pad_p1_ctl4_0;
 277         u16 iophy_misc_pad_p0_ctl5_0;
 278         u16 iophy_misc_pad_p1_ctl5_0;
 279         u16 iophy_misc_pad_p0_ctl6_0;
 280         u16 iophy_misc_pad_p1_ctl6_0;
 281         u16 usb2_otg_pad0_ctl0_0;
 282         u16 usb2_otg_pad1_ctl0_0;
 283         u16 usb2_otg_pad2_ctl0_0;
 284         u16 usb2_otg_pad0_ctl1_0;
 285         u16 usb2_otg_pad1_ctl1_0;
 286         u16 usb2_otg_pad2_ctl1_0;
 287         u16 usb2_bias_pad_ctl0_0;
 288         u16 usb2_bias_pad_ctl1_0;
 289         u16 usb2_hsic_pad0_ctl0_0;
 290         u16 usb2_hsic_pad1_ctl0_0;
 291         u16 usb2_hsic_pad0_ctl1_0;
 292         u16 usb2_hsic_pad1_ctl1_0;
 293         u16 usb2_hsic_pad0_ctl2_0;
 294         u16 usb2_hsic_pad1_ctl2_0;
 295         u16 ulpi_link_trim_ctl0;
 296         u16 ulpi_null_clk_trim_ctl0;
 297         u16 hsic_strb_trim_ctl0;
 298         u16 wake_ctl0;
 299         u16 pm_spare0;
 300         u16 iophy_misc_pad_p2_ctl1_0;
 301         u16 iophy_misc_pad_p3_ctl1_0;
 302         u16 iophy_misc_pad_p4_ctl1_0;
 303         u16 iophy_misc_pad_p2_ctl2_0;
 304         u16 iophy_misc_pad_p3_ctl2_0;
 305         u16 iophy_misc_pad_p4_ctl2_0;
 306         u16 iophy_misc_pad_p2_ctl3_0;
 307         u16 iophy_misc_pad_p3_ctl3_0;
 308         u16 iophy_misc_pad_p4_ctl3_0;
 309         u16 iophy_misc_pad_p2_ctl4_0;
 310         u16 iophy_misc_pad_p3_ctl4_0;
 311         u16 iophy_misc_pad_p4_ctl4_0;
 312         u16 iophy_misc_pad_p2_ctl5_0;
 313         u16 iophy_misc_pad_p3_ctl5_0;
 314         u16 iophy_misc_pad_p4_ctl5_0;
 315         u16 iophy_misc_pad_p2_ctl6_0;
 316         u16 iophy_misc_pad_p3_ctl6_0;
 317         u16 iophy_misc_pad_p4_ctl6_0;
 318         u16 usb3_pad_mux_0;
 319         u16 iophy_pll_s0_ctl1_0;
 320         u16 iophy_pll_s0_ctl2_0;
 321         u16 iophy_pll_s0_ctl3_0;
 322         u16 iophy_pll_s0_ctl4_0;
 323         u16 iophy_misc_pad_s0_ctl1_0;
 324         u16 iophy_misc_pad_s0_ctl2_0;
 325         u16 iophy_misc_pad_s0_ctl3_0;
 326         u16 iophy_misc_pad_s0_ctl4_0;
 327         u16 iophy_misc_pad_s0_ctl5_0;
 328         u16 iophy_misc_pad_s0_ctl6_0;
 329 };
 330
 331 struct tegra_xhci_hcd {
 332         struct platform_device *pdev;
 333         struct xhci_hcd *xhci;
 334         u16 device_id;
 335
 336         spinlock_t lock;
 337         struct mutex sync_lock;
 338
 339         int smi_irq;
 340         int padctl_irq;
 341         int usb3_irq;
 342         int usb2_irq;
 343
 344         bool ss_wake_event;
 345         bool ss_pwr_gated;
 346         bool host_pwr_gated;
 347         bool hs_wake_event;
 348         bool host_resume_req;
 349         bool lp0_exit;
 350         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
 351         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
 352         unsigned long last_jiffies;
 353         unsigned long host_phy_base;
 354         unsigned long host_phy_size;
 355         void __iomem *host_phy_virt_base;
 356
 357         void __iomem *padctl_base;
 358         void __iomem *fpci_base;
 359         void __iomem *ipfs_base;
 360
 361         struct tegra_xusb_platform_data *pdata;
 362         struct tegra_xusb_board_data *bdata;
 363         struct tegra_xusb_chip_calib *cdata;
 364         struct tegra_xusb_padctl_regs *padregs;
 365         const struct tegra_xusb_soc_config *soc_config;
 366         u64 tegra_xusb_dmamask;
 367
 368         /* mailbox variables */
 369         struct mutex mbox_lock;
 370         u32 mbox_owner;
 371         u32 cmd_type;
 372         u32 cmd_data;
 373
 374         struct regulator *xusb_utmi_vbus_regs[XUSB_UTMI_COUNT];
 375
 376         struct regulator *xusb_s1p05v_reg;
 377         struct regulator *xusb_s3p3v_reg;
 378         struct regulator *xusb_s1p8v_reg;
 379         struct regulator *vddio_hsic_reg;
 380         int vddio_hsic_refcnt;
 381
 382         struct work_struct mbox_work;
 383         struct work_struct ss_elpg_exit_work;
 384         struct work_struct host_elpg_exit_work;
 385
 386         struct clk *host_clk;
 387         struct clk *ss_clk;
 388
 389         /* XUSB Falcon SuperSpeed Clock */
 390         struct clk *falc_clk;
 391
 392         /* EMC Clock */
 393         struct clk *emc_clk;
 394         /* XUSB SS PI Clock */
 395         struct clk *ss_src_clk;
 396         /* PLLE Clock */
 397         struct clk *plle_clk;
 398         struct clk *pll_u_480M;
 399         struct clk *clk_m;
 400         /* refPLLE clk */
 401         struct clk *pll_re_vco_clk;
 402         /*
 403          * XUSB/IPFS specific registers these need to be saved/restored in
 404          * addition to spec defined registers
 405          */
 406         struct xusb_save_regs sregs;
 407         bool usb2_rh_suspend;
 408         bool usb3_rh_suspend;
 409         bool hc_in_elpg;
 410
 411         /* otg transceiver */
 412         struct usb_phy *transceiver;
 413         struct notifier_block otgnb;
 414
 415         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
 416         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
 417         /* firmware loading related */
 418         struct tegra_xhci_firmware firmware;
 419
 420         struct tegra_xhci_firmware_log log;
 421         struct device_attribute hsic_power_attr[XUSB_HSIC_COUNT];
 422
 423         bool init_done;
 424 };
 425
 426 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
 427 static int tegra_xhci_remove(struct platform_device *pdev);
 428 static void init_filesystem_firmware_done(const struct firmware *fw,
 429                                         void *context);
 430
 431 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
 432 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
 433 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
 434         u8 port)  __attribute__ ((unused));
 435
 436 #define FIRMWARE_FILE "tegra_xusb_firmware"
 437 static char *firmware_file = FIRMWARE_FILE;
 438 #define FIRMWARE_FILE_HELP      \
 439         "used to specify firmware file of Tegra XHCI host controller. "\
 440         "Default value is \"" FIRMWARE_FILE "\"."
 441
 442 module_param(firmware_file, charp, S_IRUGO);
 443 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
 444
 445 /* functions */
 446 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
 447 {
 448         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
 449 }
 450
 451 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
 452 {
 453 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
 454         WARN_ON(tegra->sync_lock.owner != current);
 455 #endif
 456 }
 457
 458 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
 459         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
 460             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
 461             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
 462
 463 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
 464                                                 int start, int last)
 465 {
 466         unsigned long portmap = tegra->bdata->portmap;
 467         return find_next_bit(&portmap, last , start);
 468 }
 469
 470 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
 471                                                 int curr_pad)
 472 {
 473         int start = XUSB_HSIC_INDEX + curr_pad;
 474         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
 475
 476         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
 477                 return -1;
 478
 479         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
 480 }
 481
 482 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
 483 {
 484         int err = 0;
 485
 486         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
 487                 return;
 488
 489         if (tegra->bdata->lane_owner & BIT(0)) {
 490                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
 491                  * GPIO P11 to '0'
 492                  */
 493                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
 494                         "gpio_ss1_sata");
 495                 if (err < 0)
 496                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
 497                                 __func__, err);
 498                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
 499                         & 0xffff), 1);
 500                 if (err < 0)
 501                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
 502                                 __func__, err);
 503                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
 504                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
 505         }
 506 }
 507
 508 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
 509 {
 510         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
 511         __le32 __iomem *addr;
 512
 513         if (port >= num_ports) {
 514                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
 515                 return -1;
 516         }
 517
 518         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
 519         return xhci_readl(xhci, addr);
 520 }
 521
 522 static void debug_print_portsc(struct xhci_hcd *xhci)
 523 {
 524         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
 525         u32 reg;
 526         int i;
 527         int ports;
 528
 529         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 530         for (i = 0; i < ports; i++) {
 531                 reg = xhci_read_portsc(xhci, i);
 532                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
 533                                 addr, i, (unsigned int) reg);
 534                 addr += NUM_PORT_REGS;
 535         }
 536 }
 537 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
 538
 539 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
 540 {
 541         if (!tegra->transceiver)
 542                 return true;
 543         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
 544                 return true;
 545         else
 546                 return false;
 547 }
 548
 549 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
 550 {
 551         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
 552         u32 portsc;
 553
 554         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
 555         if (DEV_FULLSPEED(portsc))
 556                 return USB_PMC_PORT_SPEED_FULL;
 557         else if (DEV_HIGHSPEED(portsc))
 558                 return USB_PMC_PORT_SPEED_HIGH;
 559         else if (DEV_LOWSPEED(portsc))
 560                 return USB_PMC_PORT_SPEED_LOW;
 561         else if (DEV_SUPERSPEED(portsc))
 562                 return USB_PMC_PORT_SPEED_SUPER;
 563         else
 564                 return USB_PMC_PORT_SPEED_UNKNOWN;
 565 }
 566
 567 static void pmc_init(struct tegra_xhci_hcd *tegra)
 568 {
 569         struct tegra_usb_pmc_data *pmc;
 570         struct device *dev = &tegra->pdev->dev;
 571         int pad;
 572
 573         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 574                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 575                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 576                         pmc = &pmc_data[pad];
 577                         if (tegra->soc_config->pmc_portmap)
 578                                 pmc->instance = PMC_PORTMAP_MASK(
 579                                                 tegra->soc_config->pmc_portmap,
 580                                                 pad);
 581                         else
 582                                 pmc->instance = pad;
 583                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
 584                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
 585                         pmc->controller_type = TEGRA_USB_3_0;
 586                         tegra_usb_pmc_init(pmc);
 587                 }
 588         }
 589
 590         for_each_enabled_hsic_pad(pad, tegra) {
 591                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 592                 pmc = &pmc_hsic_data[pad];
 593                 pmc->instance = pad + 1;
 594                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
 595                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
 596                 pmc->controller_type = TEGRA_USB_3_0;
 597                 tegra_usb_pmc_init(pmc);
 598         }
 599 }
 600
 601 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
 602 {
 603         struct tegra_usb_pmc_data *pmc;
 604         struct device *dev = &tegra->pdev->dev;
 605         u32 portsc;
 606         int port;
 607         int pad;
 608
 609         for_each_enabled_hsic_pad(pad, tegra) {
 610                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 611
 612                 pmc = &pmc_hsic_data[pad];
 613                 port = hsic_pad_to_port(pad);
 614                 portsc = xhci_read_portsc(tegra->xhci, port);
 615                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
 616                         __func__, pad, portsc);
 617
 618                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
 619                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 620         }
 621
 622         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 623                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 624                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 625                         pmc = &pmc_data[pad];
 626                         pmc->port_speed = update_speed(tegra, pad);
 627                         if (pad == 0) {
 628                                 if (is_otg_host(tegra))
 629                                         pmc->pmc_ops->setup_pmc_wake_detect(
 630                                                                         pmc);
 631                         } else
 632                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
 633                 }
 634         }
 635 }
 636
 637 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
 638 {
 639         struct tegra_usb_pmc_data *pmc;
 640         struct device *dev = &tegra->pdev->dev;
 641         int pad;
 642
 643         for_each_enabled_hsic_pad(pad, tegra) {
 644                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
 645
 646                 pmc = &pmc_hsic_data[pad];
 647                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 648         }
 649
 650         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
 651                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
 652                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
 653                         pmc = &pmc_data[pad];
 654                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
 655                 }
 656         }
 657 }
 658
 659 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
 660 {
 661         void __iomem *fpci_base = tegra->fpci_base;
 662         struct platform_device *pdev = tegra->pdev;
 663         u32 input_addr;
 664         u32 data;
 665         u32 csb_page_select;
 666
 667         /* to select the appropriate CSB page to write to */
 668         csb_page_select = CSB_PAGE_SELECT(addr);
 669
 670         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
 671                         csb_page_select);
 672
 673         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 674
 675         /* selects the appropriate offset in the page to read from */
 676         input_addr = CSB_PAGE_OFFSET(addr);
 677         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 678
 679         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
 680                         input_addr, data);
 681         return data;
 682 }
 683
 684 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
 685 {
 686         void __iomem *fpci_base = tegra->fpci_base;
 687         struct platform_device *pdev = tegra->pdev;
 688         u32 input_addr;
 689         u32 csb_page_select;
 690
 691         /* to select the appropriate CSB page to write to */
 692         csb_page_select = CSB_PAGE_SELECT(addr);
 693
 694         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
 695                         csb_page_select);
 696
 697         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
 698
 699         /* selects the appropriate offset in the page to write to */
 700         input_addr = CSB_PAGE_OFFSET(addr);
 701         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
 702
 703         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
 704                         input_addr, data);
 705 }
 706
 707 static int fw_message_send(struct tegra_xhci_hcd *tegra,
 708         enum MBOX_CMD_TYPE type, u32 data)
 709 {
 710         struct device *dev = &tegra->pdev->dev;
 711         void __iomem *base = tegra->fpci_base;
 712         unsigned long target;
 713         u32 reg;
 714
 715         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
 716
 717         mutex_lock(&tegra->mbox_lock);
 718
 719         target = jiffies + msecs_to_jiffies(20);
 720         /* wait mailbox to become idle, timeout in 20ms */
 721         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
 722                 time_is_after_jiffies(target)) {
 723                 mutex_unlock(&tegra->mbox_lock);
 724                 usleep_range(100, 200);
 725                 mutex_lock(&tegra->mbox_lock);
 726         }
 727
 728         if (reg != 0) {
 729                 dev_err(dev, "%s mailbox is still busy\n", __func__);
 730                 goto timeout;
 731         }
 732
 733         target = jiffies + msecs_to_jiffies(10);
 734         /* acquire mailbox , timeout in 10ms */
 735         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 736         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
 737                 && time_is_after_jiffies(target)) {
 738                 mutex_unlock(&tegra->mbox_lock);
 739                 usleep_range(100, 200);
 740                 mutex_lock(&tegra->mbox_lock);
 741                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
 742         }
 743
 744         if (reg != MBOX_OWNER_SW) {
 745                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
 746                 goto timeout;
 747         }
 748
 749         reg = CMD_TYPE(type) | CMD_DATA(data);
 750         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
 751
 752         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 753         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
 754         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
 755
 756         mutex_unlock(&tegra->mbox_lock);
 757         return 0;
 758
 759 timeout:
 760         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
 761         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
 762         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
 763         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
 764         mutex_unlock(&tegra->mbox_lock);
 765         return -ETIMEDOUT;
 766 }
 767
 768 /**
 769  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
 770  *      This function takes care of wrapping. That means when current log entry
 771  *      is the last one, it returns with the first one.
 772  *
 773  * @param log   The tegra_xhci_firmware_log context.
 774  * @param this  The current log entry.
 775  * @return      The log entry which is next to the current one.
 776  */
 777 static inline struct log_entry *fw_log_next(
 778                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
 779 {
 780         struct log_entry *first = (struct log_entry *) log->virt_addr;
 781         struct log_entry *last = first + FW_LOG_COUNT - 1;
 782
 783         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
 784
 785         return (this == last) ? first : (this + 1);
 786 }
 787
 788 /**
 789  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
 790  *      tegra_xhci_firmware_log.dequeue.
 791  *
 792  * @param log   The tegra_xhci_firmware_log context.
 793  * @param n     Counts of log entries to fast-forward.
 794  */
 795 static inline void fw_log_update_deq_pointer(
 796                 struct tegra_xhci_firmware_log *log, int n)
 797 {
 798         struct tegra_xhci_hcd *tegra =
 799                         container_of(log, struct tegra_xhci_hcd, log);
 800         struct device *dev = &tegra->pdev->dev;
 801         struct log_entry *deq = tegra->log.dequeue;
 802         dma_addr_t physical_addr;
 803         u32 reg;
 804
 805         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
 806         while (n-- > 0)
 807                 deq = fw_log_next(log, deq);
 808
 809         tegra->log.dequeue = deq;
 810         physical_addr = tegra->log.phys_addr +
 811                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
 812
 813         /* update dequeue pointer to firmware */
 814         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
 815         reg |= (physical_addr & 0xffff); /* lower 16-bits */
 816         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 817
 818         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
 819         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
 820         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
 821
 822         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, (u32)physical_addr);
 823 }
 824
 825 static inline bool circ_buffer_full(struct circ_buf *circ)
 826 {
 827         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
 828
 829         return (space <= FW_LOG_SIZE);
 830 }
 831
 832 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
 833 {
 834         return (tegra->log.dequeue->owner == DRIVER);
 835 }
 836
 837 /**
 838  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
 839  *      log buffer.
 840  * @param tegra:        tegra_xhci_hcd context
 841  * @param msec:         timeout value in millisecond
 842  * @return true:        shared log buffer is empty,
 843  *         false:       shared log buffer isn't empty.
 844  */
 845 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
 846                 unsigned timeout)
 847 {
 848         unsigned long target = jiffies + msecs_to_jiffies(timeout);
 849         bool ret;
 850
 851         mutex_lock(&tegra->log.mutex);
 852
 853         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
 854                 mutex_unlock(&tegra->log.mutex);
 855                 usleep_range(1000, 2000);
 856                 mutex_lock(&tegra->log.mutex);
 857         }
 858
 859         ret = fw_log_available(tegra);
 860         mutex_unlock(&tegra->log.mutex);
 861
 862         return ret;
 863 }
 864
 865 /**
 866  * fw_log_copy - copy firmware log from device's buffer to driver's circular
 867  *      buffer.
 868  * @param tegra tegra_xhci_hcd context
 869  * @return true,        We still have firmware log in device's buffer to copy.
 870  *                      This function returned due the driver's circular buffer
 871  *                      is full. Caller should invoke this function again as
 872  *                      soon as there is space in driver's circular buffer.
 873  *         false,       Device's buffer is empty.
 874  */
 875 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
 876 {
 877         struct device *dev = &tegra->pdev->dev;
 878         struct circ_buf *circ = &tegra->log.circ;
 879         int head, tail;
 880         int buffer_len, copy_len;
 881         struct log_entry *entry;
 882         struct log_entry *first = tegra->log.virt_addr;
 883
 884         while (fw_log_available(tegra)) {
 885
 886                 /* calculate maximum contiguous driver buffer length */
 887                 head = circ->head;
 888                 tail = ACCESS_ONCE(circ->tail);
 889                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
 890                 /* round down to FW_LOG_SIZE */
 891                 buffer_len -= (buffer_len % FW_LOG_SIZE);
 892                 if (!buffer_len)
 893                         return true; /* log available but no space left */
 894
 895                 /* calculate maximum contiguous log copy length */
 896                 entry = tegra->log.dequeue;
 897                 copy_len = 0;
 898                 do {
 899                         if (tegra->log.seq != entry->sequence_no) {
 900                                 dev_warn(dev,
 901                                 "%s: discontinuous seq no, expect %u get %u\n",
 902                                 __func__, tegra->log.seq, entry->sequence_no);
 903                         }
 904                         tegra->log.seq = entry->sequence_no + 1;
 905
 906                         copy_len += FW_LOG_SIZE;
 907                         buffer_len -= FW_LOG_SIZE;
 908                         if (!buffer_len)
 909                                 break; /* no space left */
 910                         entry = fw_log_next(&tegra->log, entry);
 911                 } while ((entry->owner == DRIVER) && (entry != first));
 912
 913                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
 914                 memset(tegra->log.dequeue, 0, copy_len);
 915                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
 916
 917                 mb();
 918
 919                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
 920
 921                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
 922                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
 923                 wake_up_interruptible(&tegra->log.read_wait);
 924         }
 925
 926         return false;
 927 }
 928
 929 static int fw_log_thread(void *data)
 930 {
 931         struct tegra_xhci_hcd *tegra = data;
 932         struct device *dev = &tegra->pdev->dev;
 933         struct circ_buf *circ = &tegra->log.circ;
 934         bool logs_left;
 935
 936         dev_dbg(dev, "start firmware log thread\n");
 937
 938         do {
 939                 mutex_lock(&tegra->log.mutex);
 940                 if (circ_buffer_full(circ)) {
 941                         mutex_unlock(&tegra->log.mutex);
 942                         dev_info(dev, "%s: circ buffer full\n", __func__);
 943                         wait_event_interruptible(tegra->log.write_wait,
 944                             kthread_should_stop() || !circ_buffer_full(circ));
 945                         mutex_lock(&tegra->log.mutex);
 946                 }
 947
 948                 logs_left = fw_log_copy(tegra);
 949                 mutex_unlock(&tegra->log.mutex);
 950
 951                 /* relax if no logs left  */
 952                 if (!logs_left)
 953                         wait_event_interruptible_timeout(tegra->log.intr_wait,
 954                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
 955         } while (!kthread_should_stop());
 956
 957         dev_dbg(dev, "stop firmware log thread\n");
 958         return 0;
 959 }
 960
 961 static inline bool circ_buffer_empty(struct circ_buf *circ)
 962 {
 963         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
 964 }
 965
 966 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
 967                 size_t count, loff_t *offp)
 968 {
 969         struct tegra_xhci_hcd *tegra = file->private_data;
 970         struct platform_device *pdev = tegra->pdev;
 971         struct circ_buf *circ = &tegra->log.circ;
 972         int head, tail;
 973         size_t n = 0;
 974         int s;
 975
 976         mutex_lock(&tegra->log.mutex);
 977
 978         while (circ_buffer_empty(circ)) {
 979                 mutex_unlock(&tegra->log.mutex);
 980                 if (file->f_flags & O_NONBLOCK)
 981                         return -EAGAIN; /* non-blocking read */
 982
 983                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
 984
 985                 if (wait_event_interruptible(tegra->log.read_wait,
 986                                 !circ_buffer_empty(circ)))
 987                         return -ERESTARTSYS;
 988
 989                 if (mutex_lock_interruptible(&tegra->log.mutex))
 990                         return -ERESTARTSYS;
 991         }
 992
 993         while (count > 0) {
 994                 head = ACCESS_ONCE(circ->head);
 995                 tail = circ->tail;
 996                 s = min_t(int, count,
 997                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
 998
 999                 if (s > 0) {
1000                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
1001                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1002                                 mutex_unlock(&tegra->log.mutex);
1003                                 return -EFAULT;
1004                         }
1005                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1006
1007                         count -= s;
1008                         n += s;
1009                 } else
1010                         break;
1011         }
1012
1013         mutex_unlock(&tegra->log.mutex);
1014
1015         wake_up_interruptible(&tegra->log.write_wait);
1016
1017         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
1018
1019         return n;
1020 }
1021
1022 static int fw_log_file_open(struct inode *inode, struct file *file)
1023 {
1024         struct tegra_xhci_hcd *tegra;
1025         file->private_data = inode->i_private;
1026         tegra = file->private_data;
1027
1028         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1029                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1030                 return -EBUSY;
1031         }
1032
1033         return 0;
1034 }
1035
1036 static int fw_log_file_close(struct inode *inode, struct file *file)
1037 {
1038         struct tegra_xhci_hcd *tegra = file->private_data;
1039
1040         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1041
1042         return 0;
1043 }
1044
1045 static const struct file_operations firmware_log_fops = {
1046                 .open           = fw_log_file_open,
1047                 .release        = fw_log_file_close,
1048                 .read           = fw_log_file_read,
1049                 .owner          = THIS_MODULE,
1050 };
1051
1052 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1053 {
1054         struct platform_device *pdev = tegra->pdev;
1055         int rc = 0;
1056
1057         /* allocate buffer to be shared between driver and firmware */
1058         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1059                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1060
1061         if (!tegra->log.virt_addr) {
1062                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1063                                 FW_LOG_RING_SIZE);
1064                 return -ENOMEM;
1065         }
1066
1067         dev_info(&pdev->dev,
1068                 "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1069                 FW_LOG_RING_SIZE, (u32)tegra->log.phys_addr,
1070                 tegra->log.virt_addr);
1071
1072         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1073         tegra->log.dequeue = tegra->log.virt_addr;
1074
1075         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1076         if (!tegra->log.circ.buf) {
1077                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1078                 rc = -ENOMEM;
1079                 goto error_free_dma;
1080         }
1081
1082         tegra->log.circ.head = 0;
1083         tegra->log.circ.tail = 0;
1084
1085         init_waitqueue_head(&tegra->log.read_wait);
1086         init_waitqueue_head(&tegra->log.write_wait);
1087         init_waitqueue_head(&tegra->log.intr_wait);
1088
1089         mutex_init(&tegra->log.mutex);
1090
1091         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1092         if (IS_ERR_OR_NULL(tegra->log.path)) {
1093                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1094                 rc = -ENOMEM;
1095                 goto error_free_mem;
1096         }
1097
1098         tegra->log.log_file = debugfs_create_file("firmware_log",
1099                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1100         if ((!tegra->log.log_file) ||
1101                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1102                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1103                 rc = -ENOMEM;
1104                 goto error_remove_debugfs_path;
1105         }
1106
1107         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1108         if (IS_ERR(tegra->log.thread)) {
1109                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1110                 rc = -ENOMEM;
1111                 goto error_remove_debugfs_file;
1112         }
1113
1114         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1115         return rc;
1116
1117 error_remove_debugfs_file:
1118         debugfs_remove(tegra->log.log_file);
1119 error_remove_debugfs_path:
1120         debugfs_remove(tegra->log.path);
1121 error_free_mem:
1122         vfree(tegra->log.circ.buf);
1123 error_free_dma:
1124         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1125                         tegra->log.virt_addr, tegra->log.phys_addr);
1126         memset(&tegra->log, sizeof(tegra->log), 0);
1127         return rc;
1128 }
1129
1130 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1131 {
1132         struct platform_device *pdev = tegra->pdev;
1133
1134         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1135
1136                 debugfs_remove(tegra->log.log_file);
1137                 debugfs_remove(tegra->log.path);
1138
1139                 wake_up_interruptible(&tegra->log.read_wait);
1140                 wake_up_interruptible(&tegra->log.write_wait);
1141                 kthread_stop(tegra->log.thread);
1142
1143                 mutex_lock(&tegra->log.mutex);
1144                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1145                         tegra->log.virt_addr, tegra->log.phys_addr);
1146                 vfree(tegra->log.circ.buf);
1147                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1148                 mutex_unlock(&tegra->log.mutex);
1149
1150                 mutex_destroy(&tegra->log.mutex);
1151         }
1152 }
1153
1154 /* hsic pad operations */
1155 /*
1156  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1157  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1158  */
1159 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1160 {
1161         struct device *dev = &tegra->pdev->dev;
1162         const struct tegra_xusb_regulator_name *supply =
1163                                 &tegra->soc_config->supply;
1164         int ret;
1165
1166         if (tegra->vddio_hsic_reg)
1167                 goto done;
1168
1169         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1170         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1171                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1172                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1173                 goto get_failed;
1174         }
1175
1176         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1177         ret = regulator_enable(tegra->vddio_hsic_reg);
1178         if (ret < 0) {
1179                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1180                 goto enable_failed;
1181         }
1182
1183 done:
1184         tegra->vddio_hsic_refcnt++;
1185         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1186                         "vddio_hsic_refcnt exceeds\n");
1187         return 0;
1188
1189 enable_failed:
1190         devm_regulator_put(tegra->vddio_hsic_reg);
1191 get_failed:
1192         tegra->vddio_hsic_reg = NULL;
1193         return ret;
1194 }
1195
1196 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1197 {
1198         struct device *dev = &tegra->pdev->dev;
1199         int ret;
1200
1201         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1202
1203         tegra->vddio_hsic_refcnt--;
1204         if (tegra->vddio_hsic_refcnt)
1205                 return 0;
1206
1207         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1208         ret = regulator_disable(tegra->vddio_hsic_reg);
1209         if (ret < 0) {
1210                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1211                 tegra->vddio_hsic_refcnt++;
1212                 return ret;
1213         }
1214
1215         devm_regulator_put(tegra->vddio_hsic_reg);
1216         tegra->vddio_hsic_reg = NULL;
1217
1218         return 0;
1219 }
1220
1221 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1222 {
1223         struct device *dev = &tegra->pdev->dev;
1224         void __iomem *base = tegra->padctl_base;
1225         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1226         u32 reg;
1227
1228         if (pad >= XUSB_HSIC_COUNT) {
1229                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1230                 return -EINVAL;
1231         }
1232
1233         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1234
1235         reg = readl(base + HSIC_PAD_CTL_2(pad));
1236         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1237         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1238         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1239         writel(reg, base + HSIC_PAD_CTL_2(pad));
1240
1241         reg = readl(base + HSIC_PAD_CTL_0(pad));
1242         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1243         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1244         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1245         reg |= TX_SLEWP(hsic->tx_slew_p);
1246         reg |= TX_SLEWN(hsic->tx_slew_n);
1247         writel(reg, base + HSIC_PAD_CTL_0(pad));
1248
1249         reg = readl(base + HSIC_PAD_CTL_1(pad));
1250         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1251         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1252         if (hsic->auto_term_en)
1253                 reg |= AUTO_TERM_EN;
1254         else
1255                 reg &= ~AUTO_TERM_EN;
1256         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1257         writel(reg, base + HSIC_PAD_CTL_1(pad));
1258
1259         /* Wait for 25 us */
1260         usleep_range(25, 50);
1261
1262         /* Power down tracking circuit */
1263         reg = readl(base + HSIC_PAD_CTL_1(pad));
1264         reg |= PD_TRX;
1265         writel(reg, base + HSIC_PAD_CTL_1(pad));
1266
1267         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1268         reg &= ~(STRB_TRIM_VAL(~0));
1269         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1270         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1271
1272         reg = readl(base + USB2_PAD_MUX);
1273         reg |= USB2_HSIC_PAD_PORT(pad);
1274         writel(reg, base + USB2_PAD_MUX);
1275
1276         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1277         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1278         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1279         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1280         reg_dump(dev, base, USB2_PAD_MUX);
1281         return 0;
1282 }
1283
1284 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1285 {
1286         struct device *dev = &tegra->pdev->dev;
1287         struct tegra_xusb_hsic_config *hsic;
1288         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1289         int pad;
1290         u32 portsc;
1291         int port;
1292         int enabled_pads = 0;
1293         unsigned long wait_ports = 0;
1294         unsigned long target;
1295
1296         for_each_enabled_hsic_pad(pad, tegra) {
1297                 hsic = &tegra->bdata->hsic[pad];
1298                 if (hsic->pretend_connect)
1299                         enabled_pads++;
1300         }
1301
1302         if (enabled_pads == 0) {
1303                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1304                 return;
1305         }
1306
1307         usb_disable_autosuspend(hs_root_hub);
1308
1309         for_each_enabled_hsic_pad(pad, tegra) {
1310                 hsic = &tegra->bdata->hsic[pad];
1311                 if (!hsic->pretend_connect)
1312                         continue;
1313
1314                 port = hsic_pad_to_port(pad);
1315                 portsc = xhci_read_portsc(tegra->xhci, port);
1316                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1317
1318                 if (!(portsc & PORT_CONNECT)) {
1319                         /* firmware wants 1-based port index */
1320                         fw_message_send(tegra,
1321                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1322                 }
1323
1324                 set_bit(port, &wait_ports);
1325         }
1326
1327         /* wait till port reaches U0 */
1328         target = jiffies + msecs_to_jiffies(500);
1329         do {
1330                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1331                         portsc = xhci_read_portsc(tegra->xhci, port);
1332                         pad = port_to_hsic_pad(port);
1333                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1334                                 pad, portsc);
1335                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1336                                 clear_bit(port, &wait_ports);
1337                 }
1338
1339                 if (wait_ports)
1340                         usleep_range(1000, 5000);
1341         } while (wait_ports && time_is_after_jiffies(target));
1342
1343         if (wait_ports)
1344                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1345
1346         usb_enable_autosuspend(hs_root_hub);
1347
1348         return;
1349 }
1350
1351 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1352 {
1353         struct device *dev = &tegra->pdev->dev;
1354         void __iomem *base = tegra->padctl_base;
1355         u32 reg;
1356
1357         if (pad >= XUSB_HSIC_COUNT) {
1358                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1359                 return -EINVAL;
1360         }
1361
1362         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1363
1364         reg = readl(base + USB2_PAD_MUX);
1365         reg &= ~USB2_HSIC_PAD_PORT(pad);
1366         writel(reg, base + USB2_PAD_MUX);
1367
1368         reg = readl(base + HSIC_PAD_CTL_1(pad));
1369         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1370         writel(reg, base + HSIC_PAD_CTL_1(pad));
1371
1372         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1373         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1374         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1375         reg_dump(dev, base, USB2_PAD_MUX);
1376         return 0;
1377 }
1378
1379 enum hsic_pad_pupd {
1380         PUPD_DISABLE = 0,
1381         PUPD_IDLE,
1382         PUPD_RESET
1383 };
1384
1385 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1386         enum hsic_pad_pupd pupd)
1387 {
1388         struct device *dev = &tegra->pdev->dev;
1389         void __iomem *base = tegra->padctl_base;
1390         u32 reg;
1391
1392         if (pad >= XUSB_HSIC_COUNT) {
1393                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1394                 return -EINVAL;
1395         }
1396
1397         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1398
1399         reg = readl(base + HSIC_PAD_CTL_1(pad));
1400         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1401
1402         if (pupd == PUPD_IDLE)
1403                 reg |= (RPD_DATA | RPU_STROBE);
1404         else if (pupd == PUPD_RESET)
1405                 reg |= (RPD_DATA | RPD_STROBE);
1406         else if (pupd != PUPD_DISABLE) {
1407                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1408                 return -EINVAL;
1409         }
1410
1411         writel(reg, base + HSIC_PAD_CTL_1(pad));
1412
1413         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1414
1415         return 0;
1416 }
1417
1418
1419 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1420 {
1421         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1422         struct xhci_hcd *xhci = tegra->xhci;
1423         u32 reg;
1424
1425         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1426         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1427         xhci_info(xhci, " PAD MUX = %x\n", reg);
1428         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1429         xhci_info(xhci, " PORT CAP = %x\n", reg);
1430         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1431         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1432         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1433         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1434         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1435         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1436         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1437         xhci_info(xhci, " OC DET 0= %x\n", reg);
1438         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1439         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1440         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1441         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1442         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1443         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1444         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1445         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1446         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1447         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1448         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1449         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1450         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1451         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1452         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1453         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1454         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1455         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1456         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1457 }
1458
1459 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1460 {
1461         u32 reg;
1462
1463         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1464         reg |= IPFS_EN_FPCI;
1465         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1466         udelay(10);
1467
1468         /* Program Bar0 Space */
1469         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1470         reg |= tegra->host_phy_base;
1471         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1472         usleep_range(100, 200);
1473
1474         /* Enable Bus Master */
1475         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1476         reg |= 0x7;
1477         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1478
1479         /* Set intr mask to enable intr assertion */
1480         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1481         reg |= IPFS_IP_INT_MASK;
1482         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1483
1484         /* Set hysteris to 0x80 */
1485         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1486 }
1487
1488 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1489                 struct platform_device *pdev)
1490 {
1491         const struct tegra_xusb_regulator_name *supply =
1492                                 &tegra->soc_config->supply;
1493         int i;
1494         int err = 0;
1495
1496         tegra->xusb_s3p3v_reg =
1497                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1498         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1499                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1500                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1501                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1502                 goto err_null_regulator;
1503         } else {
1504                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1505                 if (err < 0) {
1506                         dev_err(&pdev->dev,
1507                                 "3p3v: regulator enable failed:%d\n", err);
1508                         goto err_null_regulator;
1509                 }
1510         }
1511
1512         /* enable utmi vbuses */
1513         memset(tegra->xusb_utmi_vbus_regs, 0,
1514                         sizeof(tegra->xusb_utmi_vbus_regs));
1515         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1516                 struct regulator *reg = NULL;
1517                 const char *reg_name = supply->utmi_vbuses[i];
1518                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1519                         if (i == 0 && tegra->transceiver)
1520                                 continue;
1521                         reg = devm_regulator_get(&pdev->dev, reg_name);
1522                         if (IS_ERR(reg)) {
1523                                 dev_err(&pdev->dev,
1524                                         "%s regulator not found: %ld.",
1525                                         reg_name, PTR_ERR(reg));
1526                                 err = PTR_ERR(reg);
1527                         } else {
1528                                 err = regulator_enable(reg);
1529                                 if (err < 0) {
1530                                         dev_err(&pdev->dev,
1531                                         "%s: regulator enable failed: %d\n",
1532                                         reg_name, err);
1533                                 }
1534                         }
1535                         if (err)
1536                                 goto err_put_utmi_vbus_reg;
1537                 }
1538                 tegra->xusb_utmi_vbus_regs[i] = reg;
1539         }
1540
1541         tegra->xusb_s1p8v_reg =
1542                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1543         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1544                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1545                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1546                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1547                 goto err_put_utmi_vbus_reg;
1548         } else {
1549                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1550                 if (err < 0) {
1551                         dev_err(&pdev->dev,
1552                         "1p8v: regulator enable failed:%d\n", err);
1553                         goto err_put_utmi_vbus_reg;
1554                 }
1555         }
1556
1557         tegra->xusb_s1p05v_reg =
1558                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1559         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1560                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1561                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1562                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1563                 goto err_put_s1p8v_reg;
1564         } else {
1565                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1566                 if (err < 0) {
1567                         dev_err(&pdev->dev,
1568                         "1p05v: regulator enable failed:%d\n", err);
1569                         goto err_put_s1p8v_reg;
1570                 }
1571         }
1572
1573         return err;
1574
1575 err_put_s1p8v_reg:
1576         regulator_disable(tegra->xusb_s1p8v_reg);
1577 err_put_utmi_vbus_reg:
1578         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1579                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1580                 if (!IS_ERR_OR_NULL(reg))
1581                         regulator_disable(reg);
1582         }
1583         regulator_disable(tegra->xusb_s3p3v_reg);
1584 err_null_regulator:
1585         for (i = 0; i < XUSB_UTMI_COUNT; i++)
1586                 tegra->xusb_utmi_vbus_regs[i] = NULL;
1587         tegra->xusb_s1p05v_reg = NULL;
1588         tegra->xusb_s3p3v_reg = NULL;
1589         tegra->xusb_s1p8v_reg = NULL;
1590         return err;
1591 }
1592
1593 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1594 {
1595         int i;
1596
1597         regulator_disable(tegra->xusb_s1p05v_reg);
1598         regulator_disable(tegra->xusb_s1p8v_reg);
1599
1600         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1601                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1602                         struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1603                         if (!IS_ERR_OR_NULL(reg))
1604                                 regulator_disable(reg);
1605                         tegra->xusb_utmi_vbus_regs[i] = NULL;
1606                 }
1607         }
1608
1609         regulator_disable(tegra->xusb_s3p3v_reg);
1610
1611         tegra->xusb_s1p05v_reg = NULL;
1612         tegra->xusb_s1p8v_reg = NULL;
1613         tegra->xusb_s3p3v_reg = NULL;
1614 }
1615
1616 /*
1617  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1618  * are under hardware control
1619  */
1620 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1621 {
1622         struct platform_device *pdev = tegra->pdev;
1623         int err = 0;
1624
1625         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1626         if (IS_ERR(tegra->plle_clk)) {
1627                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1628                 err = PTR_ERR(tegra->plle_clk);
1629                 return err;
1630         }
1631         err = clk_enable(tegra->plle_clk);
1632         if (err) {
1633                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1634                         __func__);
1635                 return err;
1636         }
1637
1638         return err;
1639 }
1640
1641 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1642 {
1643         clk_disable(tegra->plle_clk);
1644         tegra->plle_clk = NULL;
1645 }
1646
1647 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1648 {
1649         struct platform_device *pdev = tegra->pdev;
1650         int err = 0;
1651
1652         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1653         if (IS_ERR(tegra->emc_clk)) {
1654                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1655                 return PTR_ERR(tegra->emc_clk);
1656         }
1657
1658         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1659                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1660                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1661                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1662                         err = PTR_ERR(tegra->pll_re_vco_clk);
1663                         goto get_pll_re_vco_clk_failed;
1664                 }
1665         }
1666
1667         /* get the clock handle of 120MHz clock source */
1668         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1669         if (IS_ERR(tegra->pll_u_480M)) {
1670                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1671                 err = PTR_ERR(tegra->pll_u_480M);
1672                 goto get_pll_u_480M_failed;
1673         }
1674
1675         /* get the clock handle of 12MHz clock source */
1676         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1677         if (IS_ERR(tegra->clk_m)) {
1678                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1679                 err = PTR_ERR(tegra->clk_m);
1680                 goto clk_get_clk_m_failed;
1681         }
1682
1683         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1684         if (IS_ERR(tegra->ss_src_clk)) {
1685                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1686                 err = PTR_ERR(tegra->ss_src_clk);
1687                 tegra->ss_src_clk = NULL;
1688                 goto get_ss_src_clk_failed;
1689         }
1690
1691         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1692         if (IS_ERR(tegra->host_clk)) {
1693                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1694                 err = PTR_ERR(tegra->host_clk);
1695                 tegra->host_clk = NULL;
1696                 goto get_host_clk_failed;
1697         }
1698
1699         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1700         if (IS_ERR(tegra->ss_clk)) {
1701                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1702                 err = PTR_ERR(tegra->ss_clk);
1703                 tegra->ss_clk = NULL;
1704                 goto get_ss_clk_failed;
1705         }
1706
1707         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1708                 err = clk_enable(tegra->pll_re_vco_clk);
1709                 if (err) {
1710                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1711                         goto enable_pll_re_vco_clk_failed;
1712                 }
1713         }
1714         return 0;
1715
1716 enable_pll_re_vco_clk_failed:
1717         tegra->ss_clk = NULL;
1718
1719 get_ss_clk_failed:
1720         tegra->host_clk = NULL;
1721
1722 get_host_clk_failed:
1723         tegra->ss_src_clk = NULL;
1724
1725 get_ss_src_clk_failed:
1726         tegra->clk_m = NULL;
1727
1728 clk_get_clk_m_failed:
1729         tegra->pll_u_480M = NULL;
1730
1731 get_pll_u_480M_failed:
1732         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1733                 tegra->pll_re_vco_clk = NULL;
1734
1735 get_pll_re_vco_clk_failed:
1736         tegra->emc_clk = NULL;
1737
1738         return err;
1739 }
1740
1741 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1742 {
1743         clk_disable(tegra->ss_clk);
1744         clk_disable(tegra->host_clk);
1745         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1746                 clk_disable(tegra->pll_re_vco_clk);
1747         tegra->ss_clk = NULL;
1748         tegra->host_clk = NULL;
1749         tegra->ss_src_clk = NULL;
1750         tegra->clk_m = NULL;
1751         tegra->pll_u_480M = NULL;
1752         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1753                 tegra->pll_re_vco_clk = NULL;
1754 }
1755
1756 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1757         bool enable)
1758 {
1759         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1760         u32 reg;
1761
1762         /* Issue is only applicable for T114 */
1763         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1764                 return;
1765
1766         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1767                 reg = readl(tegra->padctl_base +
1768                         padregs->iophy_misc_pad_p0_ctl3_0);
1769                 if (enable) {
1770                         reg &= ~RX_IDLE_MODE;
1771                         reg |= RX_IDLE_MODE_OVRD;
1772                 } else {
1773                         reg |= RX_IDLE_MODE;
1774                         reg &= ~RX_IDLE_MODE_OVRD;
1775                 }
1776                 writel(reg, tegra->padctl_base +
1777                         padregs->iophy_misc_pad_p0_ctl3_0);
1778         }
1779
1780         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1781                 reg = readl(tegra->padctl_base +
1782                         padregs->iophy_misc_pad_p1_ctl3_0);
1783                 if (enable) {
1784                         reg &= ~RX_IDLE_MODE;
1785                         reg |= RX_IDLE_MODE_OVRD;
1786                 } else {
1787                         reg |= RX_IDLE_MODE;
1788                         reg &= ~RX_IDLE_MODE_OVRD;
1789                 }
1790                 writel(reg, tegra->padctl_base +
1791                         padregs->iophy_misc_pad_p1_ctl3_0);
1792
1793                 /* SATA lane also if USB3_SS port1 mapped to it */
1794                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1795                                 tegra->bdata->lane_owner & BIT(0)) {
1796                         reg = readl(tegra->padctl_base +
1797                                 padregs->iophy_misc_pad_s0_ctl3_0);
1798                         if (enable) {
1799                                 reg &= ~RX_IDLE_MODE;
1800                                 reg |= RX_IDLE_MODE_OVRD;
1801                         } else {
1802                                 reg |= RX_IDLE_MODE;
1803                                 reg &= ~RX_IDLE_MODE_OVRD;
1804                         }
1805                         writel(reg, tegra->padctl_base +
1806                                 padregs->iophy_misc_pad_s0_ctl3_0);
1807                 }
1808         }
1809 }
1810
1811 /* Enable ss clk, host clk, falcon clk,
1812  * fs clk, dev clk, plle and refplle
1813  */
1814
1815 static int
1816 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1817                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1818 {
1819         int ret = 0;
1820         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1821         int fw_req_rate = rate, cur_rate;
1822
1823         /* Do not handle clock change as needed for HS disconnect issue */
1824         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1825                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1826                 return ret;
1827         }
1828
1829         /* frequency request from firmware is in KHz.
1830          * Convert it to MHz
1831          */
1832
1833         /* get current rate of clock */
1834         cur_rate = clk_get_rate(clk_handle);
1835         cur_rate /= 1000;
1836
1837         if (fw_req_rate == cur_rate) {
1838                 cmd_ack = MBOX_CMD_ACK;
1839
1840         } else {
1841
1842                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1843                         /* Change SS clock source to CLK_M at 12MHz */
1844                         clk_set_parent(clk_handle, tegra->clk_m);
1845                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1846
1847                         /* save leakage power when SS freq is being decreased */
1848                         tegra_xhci_rx_idle_mode_override(tegra, true);
1849                 } else if (clk_handle == tegra->ss_src_clk &&
1850                                 fw_req_rate == 120000) {
1851                         /* Change SS clock source to HSIC_480 at 120MHz */
1852                         clk_set_rate(clk_handle,  3000 * 1000);
1853                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1854
1855                         /* clear ovrd bits when SS freq is being increased */
1856                         tegra_xhci_rx_idle_mode_override(tegra, false);
1857                 }
1858
1859                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1860
1861                 if (cur_rate != fw_req_rate) {
1862                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1863                                 cur_rate, fw_req_rate);
1864                         cmd_ack = MBOX_CMD_NACK;
1865                 }
1866         }
1867         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1868         return ret;
1869 }
1870
1871 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1872 {
1873         unsigned int freq_khz;
1874
1875         freq_khz = tegra_emc_bw_to_freq_req(bw);
1876         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1877 }
1878
1879 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1880         u8 port)
1881 {
1882         struct xhci_hcd *xhci = tegra->xhci;
1883         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1884         u32 offset;
1885         u32 reg;
1886
1887         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1888                 pr_err("%s invalid SS port number %u\n", __func__, port);
1889                 return;
1890         }
1891
1892         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1893
1894         /* if port1 is mapped to SATA lane then read from SATA register */
1895         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1896                         tegra->bdata->lane_owner & BIT(0))
1897                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1898         else
1899                 offset = MISC_PAD_CTL_6_0(port);
1900
1901         /*
1902          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1903          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1904          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1905          */
1906         reg = readl(tegra->padctl_base + offset);
1907         reg &= ~MISC_OUT_SEL(~0);
1908         reg |= MISC_OUT_SEL(0x32);
1909         writel(reg, tegra->padctl_base + offset);
1910
1911         reg = readl(tegra->padctl_base + offset);
1912         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1913
1914         reg = readl(tegra->padctl_base + offset);
1915         reg &= ~MISC_OUT_SEL(~0);
1916         reg |= MISC_OUT_SEL(0x33);
1917         writel(reg, tegra->padctl_base + offset);
1918
1919         reg = readl(tegra->padctl_base + offset);
1920         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1921
1922         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1923         reg &= ~DFE_CNTL_TAP_VAL(~0);
1924         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1925         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1926
1927         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1928         reg &= ~DFE_CNTL_AMP_VAL(~0);
1929         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1930         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1931
1932         tegra->dfe_ctx_saved[port] = true;
1933 }
1934
1935 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1936         u8 port)
1937 {
1938         struct xhci_hcd *xhci = tegra->xhci;
1939         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1940         u32 offset;
1941         u32 reg;
1942
1943         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1944                 pr_err("%s invalid SS port number %u\n", __func__, port);
1945                 return;
1946         }
1947
1948         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1949
1950         /* if port1 is mapped to SATA lane then read from SATA register */
1951         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1952                         tegra->bdata->lane_owner & BIT(0))
1953                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1954         else
1955                 offset = MISC_PAD_CTL_6_0(port);
1956
1957         /*
1958          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1959          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1960          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1961          */
1962         reg = readl(tegra->padctl_base + offset);
1963         reg &= ~MISC_OUT_SEL(~0);
1964         reg |= MISC_OUT_SEL(0xa1);
1965         writel(reg, tegra->padctl_base + offset);
1966
1967         reg = readl(tegra->padctl_base + offset);
1968         reg &= ~MISC_OUT_SEL(~0);
1969         reg |= MISC_OUT_SEL(0x21);
1970         writel(reg, tegra->padctl_base + offset);
1971
1972         reg = readl(tegra->padctl_base + offset);
1973         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1974
1975         reg = readl(tegra->padctl_base + offset);
1976         reg &= ~MISC_OUT_SEL(~0);
1977         reg |= MISC_OUT_SEL(0x48);
1978         writel(reg, tegra->padctl_base + offset);
1979
1980         reg = readl(tegra->padctl_base + offset);
1981         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1982
1983         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1984         reg &= ~RX_EQ_Z_VAL(~0);
1985         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1986         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1987
1988         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1989         reg &= ~RX_EQ_G_VAL(~0);
1990         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1991         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1992
1993         tegra->ctle_ctx_saved[port] = true;
1994 }
1995
1996 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1997         u8 port)
1998 {
1999         struct xhci_hcd *xhci = tegra->xhci;
2000         u32 reg;
2001
2002         /* don't restore if not saved */
2003         if (tegra->dfe_ctx_saved[port] == false)
2004                 return;
2005
2006         xhci_info(xhci, "restoring dfe context of port %d\n", port);
2007
2008         /* restore dfe_cntl for the port */
2009         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2010         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
2011                         DFE_CNTL_TAP_VAL(~0));
2012         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
2013                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2014         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2015 }
2016
2017 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2018         u8 port)
2019 {
2020         struct xhci_hcd *xhci = tegra->xhci;
2021         u32 reg;
2022
2023         /* don't restore if not saved */
2024         if (tegra->ctle_ctx_saved[port] == false)
2025                 return;
2026
2027         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2028
2029         /* restore ctle for the port */
2030         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2031         reg &= ~(RX_EQ_Z_VAL(~0) |
2032                         RX_EQ_G_VAL(~0));
2033         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2034                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2035         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2036 }
2037
2038 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2039         u8 port)
2040 {
2041         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2042         u32 reg;
2043
2044         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2045         reg &= ~USB2_ULPI_PAD;
2046         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2047         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2048
2049         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2050         reg &= ~USB2_ULPI_PORT_CAP;
2051         reg |= (tegra->bdata->ulpicap << 24);
2052         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2053         /* FIXME: Program below when more details available
2054          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2055          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2056          */
2057 }
2058
2059 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2060         u8 port)
2061 {
2062         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2063         u32 reg;
2064         u32 ctl0_offset, ctl1_offset;
2065
2066         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2067         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2068         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2069         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2070
2071         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2072         reg &= ~USB2_PORT_CAP_MASK(port);
2073         reg |= USB2_PORT_CAP_HOST(port);
2074         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2075
2076         /*
2077          * Modify only the bits which belongs to the port
2078          * and enable respective VBUS_PAD for the port
2079          */
2080         if (tegra->bdata->uses_external_pmic == false) {
2081                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2082                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2083                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2084                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2085
2086                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2087                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2088                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2089                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2090         }
2091         /*
2092          * enable respective VBUS_PAD if port is mapped to any SS port
2093          */
2094         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2095         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2096                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2097         reg |= (0x4 | port) << (port * 3);
2098         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2099
2100         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2101                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2102                                 padregs->usb2_otg_pad0_ctl0_0;
2103         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2104                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2105                                 padregs->usb2_otg_pad0_ctl1_0;
2106
2107         reg = readl(tegra->padctl_base + ctl0_offset);
2108         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2109                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2110                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2111
2112         reg |= tegra->soc_config->hs_slew;
2113         reg |= (port == 2) ? tegra->soc_config->ls_rslew_pad2 :
2114                         port ? tegra->soc_config->ls_rslew_pad1 :
2115                         tegra->soc_config->ls_rslew_pad0;
2116         reg |= (port == 2) ? tegra->cdata->hs_curr_level_pad2 :
2117                         port ? tegra->cdata->hs_curr_level_pad1 :
2118                         tegra->cdata->hs_curr_level_pad0;
2119         writel(reg, tegra->padctl_base + ctl0_offset);
2120
2121         reg = readl(tegra->padctl_base + ctl1_offset);
2122         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2123                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2124                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2125                 | USB2_OTG_PD_DR);
2126         reg |= (tegra->cdata->hs_iref_cap << 9) |
2127                 (tegra->cdata->hs_term_range_adj << 3);
2128         writel(reg, tegra->padctl_base + ctl1_offset);
2129
2130         /*Release OTG port if not in host mode*/
2131
2132         if ((port == 0) && !is_otg_host(tegra))
2133                 tegra_xhci_release_otg_port(true);
2134 }
2135
2136 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2137 {
2138         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2139         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2140                 && (tegra->bdata->lane_owner & BIT(0))));
2141 }
2142
2143 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2144         u8 port)
2145 {
2146         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2147         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2148         u32 reg;
2149
2150         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2151                         padregs->iophy_usb3_pad0_ctl2_0;
2152         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2153                         padregs->iophy_usb3_pad0_ctl4_0;
2154         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2155                         padregs->iophy_misc_pad_p0_ctl5_0;
2156
2157         reg = readl(tegra->padctl_base + ctl2_offset);
2158         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2159                 IOPHY_USB3_CDRCNTL);
2160         reg |= tegra->soc_config->rx_wander | tegra->soc_config->rx_eq |
2161                 tegra->soc_config->cdr_cntl;
2162         writel(reg, tegra->padctl_base + ctl2_offset);
2163
2164         reg = readl(tegra->padctl_base + ctl4_offset);
2165         reg = tegra->soc_config->dfe_cntl;
2166         writel(reg, tegra->padctl_base + ctl4_offset);
2167
2168         reg = readl(tegra->padctl_base + ctl5_offset);
2169         reg |= RX_QEYE_EN;
2170         writel(reg, tegra->padctl_base + ctl5_offset);
2171
2172         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2173         reg &= ~SPARE_IN(~0);
2174         reg |= SPARE_IN(tegra->soc_config->spare_in);
2175         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2176
2177         if (xusb_use_sata_lane(tegra)) {
2178                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2179                 reg |= RX_QEYE_EN;
2180                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2181
2182                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2183                 reg &= ~SPARE_IN(~0);
2184                 reg |= SPARE_IN(tegra->soc_config->spare_in);
2185                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2186         }
2187
2188         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2189         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2190         reg |= (tegra->bdata->ss_portmap &
2191                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2192         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2193
2194         /* Make sure the SS port capability set correctly */
2195         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2196         reg &= ~USB2_PORT_CAP_MASK(
2197                         GET_SS_PORTMAP(tegra->bdata->ss_portmap, port));
2198         reg |= USB2_PORT_CAP_HOST(
2199                         GET_SS_PORTMAP(tegra->bdata->ss_portmap, port));
2200         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2201
2202         tegra_xhci_restore_dfe_context(tegra, port);
2203         tegra_xhci_restore_ctle_context(tegra, port);
2204 }
2205
2206 /* This function assigns the USB ports to the controllers,
2207  * then programs the port capabilities and pad parameters
2208  * of ports assigned to XUSB after booted to OS.
2209  */
2210 void
2211 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2212 {
2213         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2214         u32 reg, oc_bits = 0;
2215         unsigned pad;
2216
2217         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2218         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2219         reg |= tegra->cdata->hs_squelch_level | tegra->soc_config->hs_disc_lvl;
2220         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2221
2222         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2223         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2224         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2225         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2226
2227         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2228         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2229         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2230                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2231         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2232
2233         /* check if over current seen. Clear if present */
2234         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2235                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2236         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2237                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2238         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2239                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2240
2241         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2242         if (reg & oc_bits) {
2243                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2244                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2245
2246                 usleep_range(100, 200);
2247
2248                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2249                 if (reg & oc_bits)
2250                         xhci_info(tegra->xhci, "Over current still present\n");
2251         }
2252
2253         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2254         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2255         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2256                 reg |= USB2_OC_MAP_PORT2;
2257         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2258
2259         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2260                 tegra_xhci_program_utmip_pad(tegra, 0);
2261         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2262                 tegra_xhci_program_utmip_pad(tegra, 1);
2263         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2264                 tegra_xhci_program_utmip_pad(tegra, 2);
2265
2266         for_each_enabled_hsic_pad(pad, tegra)
2267                 hsic_pad_enable(tegra, pad);
2268
2269         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2270                 tegra_xhci_program_ulpi_pad(tegra, 0);
2271
2272         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2273                 tegra_xhci_program_ss_pad(tegra, 0);
2274         } else {
2275                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2276                 reg = readl(tegra->padctl_base +
2277                         padregs->iophy_misc_pad_p0_ctl3_0);
2278                 reg &= ~RX_IDLE_MODE;
2279                 reg |= RX_IDLE_MODE_OVRD;
2280                 writel(reg, tegra->padctl_base +
2281                         padregs->iophy_misc_pad_p0_ctl3_0);
2282         }
2283
2284         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2285                 tegra_xhci_program_ss_pad(tegra, 1);
2286         } else {
2287                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2288                 reg = readl(tegra->padctl_base +
2289                         padregs->iophy_misc_pad_p1_ctl3_0);
2290                 reg &= ~RX_IDLE_MODE;
2291                 reg |= RX_IDLE_MODE_OVRD;
2292                 writel(reg, tegra->padctl_base +
2293                         padregs->iophy_misc_pad_p1_ctl3_0);
2294
2295                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2296                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2297                                 tegra->bdata->lane_owner & BIT(0)) {
2298                         reg = readl(tegra->padctl_base +
2299                                 padregs->iophy_misc_pad_s0_ctl3_0);
2300                         reg &= ~RX_IDLE_MODE;
2301                         reg |= RX_IDLE_MODE_OVRD;
2302                         writel(reg, tegra->padctl_base +
2303                                 padregs->iophy_misc_pad_s0_ctl3_0);
2304                 }
2305         }
2306         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2307                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2308                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2309         }
2310 }
2311
2312 /* This function read XUSB registers and stores in device context */
2313 static void
2314 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2315 {
2316
2317         /* a. Save the IPFS registers */
2318         tegra->sregs.msi_bar_sz =
2319                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2320
2321         tegra->sregs.msi_axi_barst =
2322                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2323
2324         tegra->sregs.msi_fpci_barst =
2325                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2326
2327         tegra->sregs.msi_vec0 =
2328                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2329
2330         tegra->sregs.msi_en_vec0 =
2331                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2332
2333         tegra->sregs.fpci_error_masks =
2334                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2335
2336         tegra->sregs.intr_mask =
2337                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2338
2339         tegra->sregs.ipfs_intr_enable =
2340                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2341
2342         tegra->sregs.ufpci_config =
2343                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2344
2345         tegra->sregs.clkgate_hysteresis =
2346                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2347
2348         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2349                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2350
2351         /* b. Save the CFG registers */
2352
2353         tegra->sregs.hs_pls =
2354                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2355
2356         tegra->sregs.fs_pls =
2357                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2358
2359         tegra->sregs.hs_fs_speed =
2360                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2361
2362         tegra->sregs.hs_fs_pp =
2363                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2364
2365         tegra->sregs.cfg_aru =
2366                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2367
2368         tegra->sregs.cfg_order =
2369                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2370
2371         tegra->sregs.cfg_fladj =
2372                 readl(tegra->fpci_base + XUSB_CFG_24);
2373
2374         tegra->sregs.cfg_sid =
2375                 readl(tegra->fpci_base + XUSB_CFG_16);
2376 }
2377
2378 /* This function restores XUSB registers from device context */
2379 static void
2380 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2381 {
2382         /* Restore Cfg registers */
2383         writel(tegra->sregs.hs_pls,
2384                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2385
2386         writel(tegra->sregs.fs_pls,
2387                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2388
2389         writel(tegra->sregs.hs_fs_speed,
2390                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2391
2392         writel(tegra->sregs.hs_fs_pp,
2393                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2394
2395         writel(tegra->sregs.cfg_aru,
2396                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2397
2398         writel(tegra->sregs.cfg_order,
2399                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2400
2401         writel(tegra->sregs.cfg_fladj,
2402                 tegra->fpci_base + XUSB_CFG_24);
2403
2404         writel(tegra->sregs.cfg_sid,
2405                 tegra->fpci_base + XUSB_CFG_16);
2406
2407         /* Restore IPFS registers */
2408
2409         writel(tegra->sregs.msi_bar_sz,
2410                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2411
2412         writel(tegra->sregs.msi_axi_barst,
2413                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2414
2415         writel(tegra->sregs.msi_fpci_barst,
2416                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2417
2418         writel(tegra->sregs.msi_vec0,
2419                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2420
2421         writel(tegra->sregs.msi_en_vec0,
2422                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2423
2424         writel(tegra->sregs.fpci_error_masks,
2425                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2426
2427         writel(tegra->sregs.intr_mask,
2428                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2429
2430         writel(tegra->sregs.ipfs_intr_enable,
2431                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2432
2433         writel(tegra->sregs.ufpci_config,
2434                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2435
2436         writel(tegra->sregs.clkgate_hysteresis,
2437                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2438
2439         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2440                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2441 }
2442
2443 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2444 {
2445         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2446 }
2447
2448 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2449 {
2450         struct platform_device *pdev = tegra->pdev;
2451         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2452         u32 phys_addr_lo;
2453         u32 HwReg;
2454         u16 nblocks;
2455         time_t fw_time;
2456         struct tm fw_tm;
2457         u8 hc_caplength;
2458         u32 usbsts, count = 0xff;
2459         struct xhci_cap_regs __iomem *cap_regs;
2460         struct xhci_op_regs __iomem *op_regs;
2461         int pad;
2462
2463         /* Program SS port map config */
2464         cfg_tbl->ss_portmap = 0x0;
2465         cfg_tbl->ss_portmap |=
2466                 (tegra->bdata->portmap & ((1 << XUSB_SS_PORT_COUNT) - 1));
2467
2468         /* First thing, reset the ARU. By the time we get to
2469          * loading boot code below, reset would be complete.
2470          * alternatively we can busy wait on rst pending bit.
2471          */
2472         /* Don't reset during ELPG/LP0 exit path */
2473         if (resetARU) {
2474                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2475                 usleep_range(1000, 2000);
2476         }
2477
2478         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2479                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2480                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2481                 return 0;
2482         }
2483
2484         /* update the phys_log_buffer and total_entries here */
2485         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2486         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2487
2488         phys_addr_lo = tegra->firmware.dma;
2489         phys_addr_lo += sizeof(struct cfgtbl);
2490
2491         /* Program the size of DFI into ILOAD_ATTR */
2492         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2493
2494         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2495          * to get to the start of the dfi in system memory.
2496          */
2497         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2498
2499         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2500         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2501
2502         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2503         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2504
2505         /* Invalidate L2IMEM. */
2506         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2507
2508         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2509          * Program BootCode location and size in system memory.
2510          */
2511         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2512                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2513                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2514         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2515                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2516                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2517         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2518
2519         /* Trigger L2IMEM Load operation. */
2520         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2521
2522         /* Setup Falcon Auto-fill */
2523         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2524         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2525                 nblocks += 1;
2526         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2527
2528         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2529         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2530                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2531         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2532
2533         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2534         msleep(50);
2535
2536         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2537
2538         /* Start Falcon CPU */
2539         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2540         usleep_range(1000, 2000);
2541
2542         fw_time = cfg_tbl->fwimg_created_time;
2543         time_to_tm(fw_time, 0, &fw_tm);
2544         dev_info(&pdev->dev,
2545                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2546                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2547                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2548                 fw_tm.tm_min, fw_tm.tm_sec,
2549                 csb_read(tegra, XUSB_FALC_CPUCTL));
2550
2551         cfg_tbl->num_hsic_port = 0;
2552         for_each_enabled_hsic_pad(pad, tegra)
2553                 cfg_tbl->num_hsic_port++;
2554
2555         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2556
2557         /* return fail if firmware status is not good */
2558         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2559                 return -EFAULT;
2560
2561         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2562         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2563         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2564
2565         /* wait for USBSTS_CNR to get set */
2566         do {
2567                 usbsts = ioread32(&op_regs->status);
2568         } while ((usbsts & STS_CNR) && count--);
2569
2570         if (!count && (usbsts & STS_CNR)) {
2571                 dev_err(&pdev->dev, "Controller not ready\n");
2572                 return -EFAULT;
2573         }
2574         for_each_enabled_hsic_pad(pad, tegra)
2575                 hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
2576
2577         return 0;
2578 }
2579
2580 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2581         bool release)
2582 {
2583         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2584         u32 reg;
2585
2586         /* Issue is only applicable for T114 */
2587         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2588                 return;
2589
2590         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2591         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2592                         USB2_OTG_PAD_PORT_MASK(2));
2593
2594         if (!release) {
2595                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2596                         if (is_otg_host(tegra))
2597                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2598                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2599                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2600                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2601                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2602         }
2603
2604         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2605 }
2606 /* SS ELPG Entry initiated by fw */
2607 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2608 {
2609         struct xhci_hcd *xhci = tegra->xhci;
2610         u32 ret = 0;
2611
2612         must_have_sync_lock(tegra);
2613
2614         /* update maximum BW requirement to 0 */
2615         tegra_xusb_set_bw(tegra, 0);
2616
2617         /* This is SS partition ELPG entry
2618          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2619          */
2620
2621         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2622          * only if it is sw initiated one
2623          */
2624
2625         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2626          * SuperSpeed partition ELPG entry via mailbox protocol
2627          */
2628
2629         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2630          * enable the XUSB wakeup interrupts for the SuperSpeed
2631          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2632          */
2633         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2634
2635         /* STEP 3: xHCI PEP driver initiates the signal sequence
2636          * to enable the XUSB SSwake detection logic for the
2637          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2638          */
2639         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2640
2641         /* STEP 4: System Power Management driver asserts reset
2642          * to XUSB SuperSpeed partition then disables its clocks
2643          */
2644         tegra_periph_reset_assert(tegra->ss_clk);
2645         clk_disable(tegra->ss_clk);
2646
2647         usleep_range(100, 200);
2648
2649         /* STEP 5: System Power Management driver disables the
2650          * XUSB SuperSpeed partition power rails.
2651          */
2652         debug_print_portsc(xhci);
2653
2654         /* tegra_powergate_partition also does partition reset assert */
2655         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2656         if (ret) {
2657                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2658                                 __func__);
2659                 /* TODO: error recovery? */
2660         }
2661         tegra->ss_pwr_gated = true;
2662
2663         /* STEP 6: xHCI PEP driver initiates the signal sequence
2664          * to enable the XUSB SSwake detection logic for the
2665          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2666          */
2667         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2668
2669         return ret;
2670 }
2671
2672 /* Host ELPG Entry */
2673 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2674 {
2675         struct xhci_hcd *xhci = tegra->xhci;
2676         u32 ret;
2677
2678         must_have_sync_lock(tegra);
2679
2680         /* If ss is already powergated skip ss ctx save stuff */
2681         if (tegra->ss_pwr_gated) {
2682                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2683                         __func__);
2684         } else {
2685                 ret = tegra_xhci_ss_elpg_entry(tegra);
2686                 if (ret) {
2687                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2688                                 __func__, ret);
2689                         return ret;
2690                 }
2691         }
2692
2693         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2694
2695         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2696         tegra_xhci_save_xusb_ctx(tegra);
2697
2698         /* calculate rctrl_val and tctrl_val */
2699         tegra_xhci_war_for_tctrl_rctrl(tegra);
2700
2701         pmc_setup_wake_detect(tegra);
2702
2703         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2704         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2705                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2706
2707         /* tegra_powergate_partition also does partition reset assert */
2708         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2709         if (ret) {
2710                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2711                         __func__, ret);
2712                 /* TODO: error handling? */
2713                 return ret;
2714         }
2715         tegra->host_pwr_gated = true;
2716         clk_disable(tegra->host_clk);
2717
2718         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2719                 clk_disable(tegra->pll_re_vco_clk);
2720         clk_disable(tegra->emc_clk);
2721         /* set port ownership to SNPS */
2722         tegra_xhci_release_port_ownership(tegra, true);
2723
2724         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2725                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2726
2727         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2728         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2729                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2730         return ret;
2731 }
2732
2733 /* SS ELPG Exit triggered by PADCTL irq */
2734 /**
2735  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2736  *
2737  * This function must be called with tegra->sync_lock acquired.
2738  *
2739  * @tegra: xhci controller context
2740  * @return 0 for success, or error numbers
2741  */
2742 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2743 {
2744         struct xhci_hcd *xhci = tegra->xhci;
2745         int ret = 0;
2746
2747         must_have_sync_lock(tegra);
2748
2749         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2750                         tegra->hs_wake_event || tegra->host_resume_req)) {
2751
2752                 /*
2753                  * PWR_UNGATE SS partition. XUSBA
2754                  * tegra_unpowergate_partition also does partition reset
2755                  * deassert
2756                  */
2757                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2758                 if (ret) {
2759                         xhci_err(xhci,
2760                         "%s: could not unpowergate xusba partition %d\n",
2761                         __func__, ret);
2762                         goto out;
2763                 }
2764                 if (tegra->ss_wake_event)
2765                         tegra->ss_wake_event = false;
2766
2767         } else {
2768                 xhci_info(xhci, "%s: ss already power gated\n",
2769                         __func__);
2770                 return ret;
2771         }
2772
2773         /* Step 3: Enable clock to ss partition */
2774         clk_enable(tegra->ss_clk);
2775
2776         /* Step 4: Disable ss wake detection logic */
2777         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2778
2779         /* Step 4.1: Disable ss wake detection logic */
2780         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2781
2782         /* wait 150us */
2783         usleep_range(150, 200);
2784
2785         /* Step 4.2: Disable ss wake detection logic */
2786         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2787
2788         /* Step 6 Deassert reset for ss clks */
2789         tegra_periph_reset_deassert(tegra->ss_clk);
2790
2791         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2792         tegra->ss_pwr_gated = false;
2793 out:
2794         return ret;
2795 }
2796
2797 static void ss_partition_elpg_exit_work(struct work_struct *work)
2798 {
2799         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2800                 ss_elpg_exit_work);
2801
2802         mutex_lock(&tegra->sync_lock);
2803         tegra_xhci_ss_partition_elpg_exit(tegra);
2804         mutex_unlock(&tegra->sync_lock);
2805 }
2806
2807 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2808 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2809 {
2810         struct xhci_hcd *xhci = tegra->xhci;
2811         u32 wake2_status;
2812         int port;
2813
2814 #define PMC_WAKE2_STATUS        0x168
2815 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2816
2817         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2818
2819         if (wake2_status & PADCTL_WAKE) {
2820                 /* FIXME: This is customized for Dalmore, find a generic way */
2821                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2822                 /* clear wake status */
2823                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2824         }
2825
2826         /* set all usb2 ports with RESUME link state as wakup ports  */
2827         for (port = 0; port < xhci->num_usb2_ports; port++) {
2828                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2829                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2830                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2831         }
2832
2833         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2834                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2835         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2836                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2837 }
2838
2839 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2840 {
2841         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2842         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2843         int port, num_ports;
2844         unsigned long *remote_wakeup_ports;
2845         u32 portsc;
2846         __le32 __iomem  **port_array;
2847         unsigned char *rh;
2848         unsigned int retry = 64;
2849         struct xhci_bus_state *bus_state;
2850
2851         bus_state = &xhci->bus_state[hcd_index(hcd)];
2852
2853         if (hcd == xhci->shared_hcd) {
2854                 port_array = xhci->usb3_ports;
2855                 num_ports = xhci->num_usb3_ports;
2856                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2857                 rh = "usb3 roothub";
2858         } else {
2859                 port_array = xhci->usb2_ports;
2860                 num_ports = xhci->num_usb2_ports;
2861                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2862                 rh = "usb2 roothub";
2863         }
2864
2865         while (*remote_wakeup_ports && retry--) {
2866                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2867                         bool can_continue;
2868
2869                         portsc = xhci_readl(xhci, port_array[port]);
2870
2871                         if (!(portsc & PORT_CONNECT)) {
2872                                 /* nothing to do if already disconnected */
2873                                 clear_bit(port, remote_wakeup_ports);
2874                                 continue;
2875                         }
2876
2877                         if (hcd == xhci->shared_hcd) {
2878                                 can_continue =
2879                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2880                         } else {
2881                                 unsigned long flags;
2882
2883                                 spin_lock_irqsave(&xhci->lock, flags);
2884                                 can_continue =
2885                                 test_bit(port, &bus_state->resuming_ports);
2886                                 spin_unlock_irqrestore(&xhci->lock, flags);
2887                         }
2888
2889                         if (can_continue)
2890                                 clear_bit(port, remote_wakeup_ports);
2891                         else
2892                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2893                                         __func__, rh, port, portsc);
2894                 }
2895
2896                 if (*remote_wakeup_ports)
2897                         msleep(20); /* give some time, irq will direct U0 */
2898         }
2899
2900         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2901                         *remote_wakeup_ports);
2902 }
2903
2904 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2905 {
2906         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2907         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2908
2909         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2910         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2911                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2912
2913         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2914                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2915                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2916         }
2917
2918         /* Use xusb padctl space only when xusb owns all UTMIP port */
2919         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2920         if ((pad_mux & portmux) == portowner) {
2921                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2922                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2923                  */
2924                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2925                 reg &= ~((1 << 12) | (1 << 13));
2926                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2927
2928                 /* wait 20us */
2929                 usleep_range(20, 30);
2930
2931                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2932                  * :: TCTRL and RCTRL
2933                  */
2934                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2935                 utmip_rctrl_val = RCTRL(reg);
2936                 utmip_tctrl_val = TCTRL(reg);
2937
2938                 /*
2939                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2940                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2941                  */
2942                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2943                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2944                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2945                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2946                                         utmip_rctrl_val, utmip_tctrl_val);
2947
2948                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2949                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2950                  */
2951                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2952                 reg |= (1 << 13);
2953                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2954
2955                 /* Program these values into PMC regiseter and program the
2956                  * PMC override.
2957                  */
2958                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2959                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2960                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2961                                         0xffffffff, reg);
2962                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2963                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2964         } else {
2965                 /* Use common PMC API to use SNPS register space */
2966                 utmi_phy_set_snps_trking_data();
2967         }
2968 }
2969
2970 /* Host ELPG Exit triggered by PADCTL irq */
2971 /**
2972  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2973  *
2974  * This function must be called with tegra->sync_lock acquired.
2975  *
2976  * @tegra: xhci controller context
2977  * @return 0 for success, or error numbers
2978  */
2979 static int
2980 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2981 {
2982         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2983         struct xhci_hcd *xhci = tegra->xhci;
2984         int ret = 0;
2985
2986         must_have_sync_lock(tegra);
2987
2988         if (!tegra->hc_in_elpg)
2989                 return 0;
2990
2991         clk_enable(tegra->emc_clk);
2992         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2993                 clk_enable(tegra->pll_re_vco_clk);
2994
2995         if (tegra->lp0_exit) {
2996                 u32 reg, oc_bits = 0;
2997
2998                 /* Issue is only applicable for T114 */
2999                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
3000                         tegra_xhci_war_for_tctrl_rctrl(tegra);
3001                 /* check if over current seen. Clear if present */
3002                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
3003                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
3004                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
3005                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
3006                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
3007                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
3008
3009                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
3010                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
3011                 if (reg & oc_bits) {
3012                         xhci_info(xhci, "Over current detected. Clearing...\n");
3013                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
3014
3015                         usleep_range(100, 200);
3016
3017                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
3018                         if (reg & oc_bits)
3019                                 xhci_info(xhci, "Over current still present\n");
3020                 }
3021                 tegra_xhci_padctl_portmap_and_caps(tegra);
3022                 /* release clamps post deassert */
3023                 tegra->lp0_exit = false;
3024         }
3025
3026         /* Clear FLUSH_ENABLE of MC client */
3027         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
3028
3029         /* set port ownership back to xusb */
3030         tegra_xhci_release_port_ownership(tegra, false);
3031
3032         /*
3033          * PWR_UNGATE Host partition. XUSBC
3034          * tegra_unpowergate_partition also does partition reset deassert
3035          */
3036         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3037         if (ret) {
3038                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3039                         __func__, ret);
3040                 goto out;
3041         }
3042         clk_enable(tegra->host_clk);
3043
3044         /* Step 4: Deassert reset to host partition clk */
3045         tegra_periph_reset_deassert(tegra->host_clk);
3046
3047         /* Step 6.1: IPFS and XUSB BAR initialization */
3048         tegra_xhci_cfg(tegra);
3049
3050         /* Step 6.2: IPFS and XUSB related restore */
3051         tegra_xhci_restore_ctx(tegra);
3052
3053         /* Step 8: xhci spec related ctx restore
3054          * will be done in xhci_resume().Do it here.
3055          */
3056
3057         tegra_xhci_ss_partition_elpg_exit(tegra);
3058
3059         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3060         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3061                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3062                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3063         }
3064
3065         /* clear ovrd bits */
3066         tegra_xhci_rx_idle_mode_override(tegra, false);
3067
3068         /* Load firmware */
3069         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3070                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3071                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3072                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3073                         __func__,
3074                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3075                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3076                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3077                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3078                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3079                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3080                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3081                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3082                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3083         debug_print_portsc(xhci);
3084
3085         tegra_xhci_enable_fw_message(tegra);
3086         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3087         if (ret < 0) {
3088                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3089                         __func__, ret);
3090                 goto out;
3091         }
3092
3093         pmc_disable_bus_ctrl(tegra);
3094
3095         tegra->hc_in_elpg = false;
3096         ret = xhci_resume(tegra->xhci, 0);
3097         if (ret) {
3098                 xhci_err(xhci, "%s: could not resume right %d\n",
3099                                 __func__, ret);
3100                 goto out;
3101         }
3102
3103         update_remote_wakeup_ports(tegra);
3104
3105         if (tegra->hs_wake_event)
3106                 tegra->hs_wake_event = false;
3107
3108         if (tegra->host_resume_req)
3109                 tegra->host_resume_req = false;
3110
3111         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3112                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3113
3114         tegra->host_pwr_gated = false;
3115 out:
3116         return ret;
3117 }
3118
3119 static void host_partition_elpg_exit_work(struct work_struct *work)
3120 {
3121         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3122                 host_elpg_exit_work);
3123
3124         mutex_lock(&tegra->sync_lock);
3125         tegra_xhci_host_partition_elpg_exit(tegra);
3126         mutex_unlock(&tegra->sync_lock);
3127 }
3128
3129 /* Mailbox handling function. This function handles requests
3130  * from firmware and communicates with clock and powergating
3131  * module to alter clock rates and to power gate/ungate xusb
3132  * partitions.
3133  *
3134  * Following is the structure of mailbox messages.
3135  * bit 31:28 - msg type
3136  * bits 27:0 - mbox data
3137  * FIXME:  Check if we can just call clock functions like below
3138  * or should we schedule it for calling later ?
3139  */
3140
3141 static void
3142 tegra_xhci_process_mbox_message(struct work_struct *work)
3143 {
3144         u32 sw_resp = 0, cmd, data_in, fw_msg;
3145         int ret = 0;
3146         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3147                                         mbox_work);
3148         struct xhci_hcd *xhci = tegra->xhci;
3149         int pad, port;
3150         unsigned long ports;
3151         enum MBOX_CMD_TYPE response;
3152
3153         mutex_lock(&tegra->mbox_lock);
3154
3155         /* get the mbox message from firmware */
3156         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3157
3158         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3159         if (data_in) {
3160                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3161                         __func__, data_in);
3162                 mutex_unlock(&tegra->mbox_lock);
3163                 return;
3164         }
3165
3166         /* get cmd type and cmd data */
3167         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3168         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3169
3170         /* decode the message and make appropriate requests to
3171          * clock or powergating module.
3172          */
3173
3174         switch (tegra->cmd_type) {
3175         case MBOX_CMD_INC_FALC_CLOCK:
3176         case MBOX_CMD_DEC_FALC_CLOCK:
3177                 ret = tegra_xusb_request_clk_rate(
3178                                 tegra,
3179                                 tegra->falc_clk,
3180                                 tegra->cmd_data,
3181                                 &sw_resp);
3182                 if (ret)
3183                         xhci_err(xhci, "%s: could not set required falc rate\n",
3184                                 __func__);
3185                 goto send_sw_response;
3186         case MBOX_CMD_INC_SSPI_CLOCK:
3187         case MBOX_CMD_DEC_SSPI_CLOCK:
3188                 ret = tegra_xusb_request_clk_rate(
3189                                 tegra,
3190                                 tegra->ss_src_clk,
3191                                 tegra->cmd_data,
3192                                 &sw_resp);
3193                 if (ret)
3194                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3195                                 __func__);
3196                 goto send_sw_response;
3197
3198         case MBOX_CMD_SET_BW:
3199                 /* fw sends BW request in MByte/sec */
3200                 mutex_lock(&tegra->sync_lock);
3201                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3202                 mutex_unlock(&tegra->sync_lock);
3203                 break;
3204
3205         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3206                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3207                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3208                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3209                 goto send_sw_response;
3210
3211         case MBOX_CMD_STAR_HSIC_IDLE:
3212                 ports = tegra->cmd_data;
3213                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3214                         pad = port_to_hsic_pad(port - 1);
3215                         mutex_lock(&tegra->sync_lock);
3216                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3217                         mutex_unlock(&tegra->sync_lock);
3218                         if (ret)
3219                                 break;
3220                 }
3221
3222                 sw_resp = CMD_DATA(tegra->cmd_data);
3223                 if (!ret)
3224                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3225                 else
3226                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3227
3228                 goto send_sw_response;
3229
3230         case MBOX_CMD_STOP_HSIC_IDLE:
3231                 ports = tegra->cmd_data;
3232                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3233                         pad = port_to_hsic_pad(port - 1);
3234                         mutex_lock(&tegra->sync_lock);
3235                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3236                         mutex_unlock(&tegra->sync_lock);
3237                         if (ret)
3238                                 break;
3239                 }
3240
3241                 sw_resp = CMD_DATA(tegra->cmd_data);
3242                 if (!ret)
3243                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3244                 else
3245                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3246                 goto send_sw_response;
3247
3248         case MBOX_CMD_ACK:
3249                 xhci_dbg(xhci, "%s firmware responds with ACK\n", __func__);
3250                 break;
3251         case MBOX_CMD_NACK:
3252                 xhci_warn(xhci, "%s firmware responds with NACK\n", __func__);
3253                 break;
3254         default:
3255                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3256                                 __func__, tegra->cmd_type);
3257         }
3258
3259         /* clear MBOX_SMI_INT_EN bit */
3260         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3261         cmd &= ~MBOX_SMI_INT_EN;
3262         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3263
3264         /* clear mailbox ownership */
3265         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3266
3267         mutex_unlock(&tegra->mbox_lock);
3268         return;
3269
3270 send_sw_response:
3271         response = (sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3272         if (response == MBOX_CMD_NACK)
3273                 xhci_warn(xhci, "%s respond fw message 0x%x with NACK\n",
3274                         __func__, fw_msg);
3275         else if (response == MBOX_CMD_ACK)
3276                 xhci_dbg(xhci, "%s respond fw message 0x%x with ACK\n",
3277                         __func__, fw_msg);
3278         else
3279                 xhci_err(xhci, "%s respond fw message 0x%x with %d\n",
3280                 __func__, fw_msg, response);
3281
3282         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3283         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3284         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3285         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3286
3287         mutex_unlock(&tegra->mbox_lock);
3288 }
3289
3290 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3291 {
3292         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3293         struct xhci_hcd *xhci = tegra->xhci;
3294
3295         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3296         return IRQ_HANDLED;
3297 }
3298
3299 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3300 {
3301         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3302         struct xhci_hcd *xhci = tegra->xhci;
3303         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3304         u32 elpg_program0 = 0;
3305
3306         spin_lock(&tegra->lock);
3307
3308         tegra->last_jiffies = jiffies;
3309
3310         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3311         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3312
3313         /* Clear the interrupt cause. We already read the intr status. */
3314         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3315         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3316
3317         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3318         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3319                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3320         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3321                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3322         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3323                 __func__,
3324                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3325         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3326                 __func__,
3327                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3328         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3329                 __func__,
3330                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3331
3332         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3333                 tegra->ss_wake_event = true;
3334         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3335                         USB2_PORT1_WAKEUP_EVENT |
3336                         USB2_PORT2_WAKEUP_EVENT |
3337                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3338                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3339                 tegra->hs_wake_event = true;
3340
3341         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3342                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3343                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3344                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3345                 } else if (tegra->ss_pwr_gated
3346                                 && tegra->host_pwr_gated) {
3347                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3348                                 __func__);
3349                         schedule_work(&tegra->host_elpg_exit_work);
3350                 }
3351         } else {
3352                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3353                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3354         }
3355         spin_unlock(&tegra->lock);
3356         return IRQ_HANDLED;
3357 }
3358
3359 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3360 {
3361         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3362         u32 temp;
3363
3364         spin_lock(&tegra->lock);
3365
3366         /* clear the mbox intr status 1st thing. Other
3367          * bits are W1C bits, so just write to SMI bit.
3368          */
3369
3370         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3371         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3372
3373         xhci_dbg(tegra->xhci, "SMI INTR status 0x%x\n", temp);
3374         if (temp & SMI_INTR_STATUS_FW_REINIT)
3375                 xhci_err(tegra->xhci, "Firmware reinit.\n");
3376         if (temp & SMI_INTR_STATUS_MBOX)
3377                 schedule_work(&tegra->mbox_work);
3378
3379         spin_unlock(&tegra->lock);
3380         return IRQ_HANDLED;
3381 }
3382
3383 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3384 {
3385         /*
3386          * As of now platform drivers don't provide MSI support so we ensure
3387          * here that the generic code does not try to make a pci_dev from our
3388          * dev struct in order to setup MSI
3389          */
3390         xhci->quirks |= XHCI_PLAT;
3391         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3392 }
3393
3394 /* called during probe() after chip reset completes */
3395 static int xhci_plat_setup(struct usb_hcd *hcd)
3396 {
3397         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3398 }
3399
3400 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3401         int num, void __iomem **region)
3402 {
3403         struct resource *res;
3404         void __iomem *mem;
3405
3406         res = platform_get_resource(pdev, IORESOURCE_MEM, num);
3407         if (!res) {
3408                 dev_err(&pdev->dev, "memory resource %d doesn't exist\n", num);
3409                 return -ENODEV;
3410         }
3411
3412         mem = devm_request_and_ioremap(&pdev->dev, res);
3413         if (!mem) {
3414                 dev_err(&pdev->dev, "failed to ioremap for %d\n", num);
3415                 return -EFAULT;
3416         }
3417         *region = mem;
3418
3419         return 0;
3420 }
3421
3422 static int tegra_xhci_request_irq(struct platform_device *pdev,
3423         int num, irq_handler_t handler, unsigned long irqflags,
3424         const char *devname, int *irq_no)
3425 {
3426         int ret;
3427         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3428         struct resource *res;
3429
3430         res = platform_get_resource(pdev, IORESOURCE_IRQ, num);
3431         if (!res) {
3432                 dev_err(&pdev->dev, "irq resource %d doesn't exist\n", num);
3433                 return -ENODEV;
3434         }
3435
3436         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3437                         devname, tegra);
3438         if (ret != 0) {
3439                 dev_err(&pdev->dev,
3440                         "failed to request_irq for %s (irq %d), error = %d\n",
3441                         devname, (int)res->start, ret);
3442                 return ret;
3443         }
3444         *irq_no = res->start;
3445
3446         return 0;
3447 }
3448
3449 #ifdef CONFIG_PM
3450
3451 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3452 {
3453         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3454         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3455         int err = 0;
3456         unsigned long flags;
3457
3458         mutex_lock(&tegra->sync_lock);
3459
3460         if (xhci->shared_hcd == hcd) {
3461                 tegra->usb3_rh_suspend = true;
3462                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3463         } else if (xhci->main_hcd == hcd) {
3464                 tegra->usb2_rh_suspend = true;
3465                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3466         }
3467
3468         WARN_ON(tegra->hc_in_elpg);
3469
3470         /* suspend xhci bus. This will also set remote mask */
3471         err = xhci_bus_suspend(hcd);
3472         if (err) {
3473                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3474                                 __func__, err);
3475                 goto xhci_bus_suspend_failed;
3476         }
3477
3478         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3479                 goto done; /* one of the root hubs is still working */
3480
3481         spin_lock_irqsave(&tegra->lock, flags);
3482         tegra->hc_in_elpg = true;
3483         spin_unlock_irqrestore(&tegra->lock, flags);
3484
3485         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3486
3487         /* save xhci spec ctx. Already done by xhci_suspend */
3488         err = xhci_suspend(tegra->xhci);
3489         if (err) {
3490                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3491                 goto xhci_suspend_failed;
3492         }
3493
3494         /* Powergate host. Include ss power gate if not already done */
3495         err = tegra_xhci_host_elpg_entry(tegra);
3496         if (err) {
3497                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3498                                 __func__, err);
3499                 goto tegra_xhci_host_elpg_entry_failed;
3500         }
3501
3502         /* At this point,ensure ss/hs intr enables are always on */
3503         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3504         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3505
3506         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3507         if (fw_log_wait_empty_timeout(tegra, 100))
3508                 xhci_warn(xhci, "%s still has logs\n", __func__);
3509         tegra->log.dequeue = tegra->log.virt_addr;
3510         tegra->log.seq = 0;
3511
3512 done:
3513         /* pads are disabled only if usb2 root hub in xusb is idle */
3514         /* pads will actually be disabled only when all usb2 ports are idle */
3515         if (xhci->main_hcd == hcd) {
3516                 utmi_phy_pad_disable();
3517                 utmi_phy_iddq_override(true);
3518         }
3519         mutex_unlock(&tegra->sync_lock);
3520         return 0;
3521
3522 tegra_xhci_host_elpg_entry_failed:
3523
3524 xhci_suspend_failed:
3525         tegra->hc_in_elpg = false;
3526 xhci_bus_suspend_failed:
3527         if (xhci->shared_hcd == hcd)
3528                 tegra->usb3_rh_suspend = false;
3529         else if (xhci->main_hcd == hcd)
3530                 tegra->usb2_rh_suspend = false;
3531
3532         mutex_unlock(&tegra->sync_lock);
3533         return err;
3534 }
3535
3536 /* First, USB2HCD and then USB3HCD resume will be called */
3537 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3538 {
3539         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3540         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3541         int err = 0;
3542
3543         mutex_lock(&tegra->sync_lock);
3544
3545         tegra->host_resume_req = true;
3546
3547         if (xhci->shared_hcd == hcd)
3548                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3549         else if (xhci->main_hcd == hcd)
3550                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3551
3552         /* pads are disabled only if usb2 root hub in xusb is idle */
3553         /* pads will actually be disabled only when all usb2 ports are idle */
3554         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3555                 utmi_phy_pad_enable();
3556                 utmi_phy_iddq_override(false);
3557         }
3558         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3559                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3560                         tegra_xhci_host_partition_elpg_exit(tegra);
3561         }
3562
3563          /* handle remote wakeup before resuming bus */
3564         wait_remote_wakeup_ports(hcd);
3565
3566         err = xhci_bus_resume(hcd);
3567         if (err) {
3568                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3569                                 __func__, err);
3570                 goto xhci_bus_resume_failed;
3571         }
3572
3573         if (xhci->shared_hcd == hcd)
3574                 tegra->usb3_rh_suspend = false;
3575         else if (xhci->main_hcd == hcd)
3576                 tegra->usb2_rh_suspend = false;
3577
3578         mutex_unlock(&tegra->sync_lock);
3579         return 0;
3580
3581 xhci_bus_resume_failed:
3582         /* TODO: reverse elpg? */
3583         mutex_unlock(&tegra->sync_lock);
3584         return err;
3585 }
3586 #endif
3587
3588 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3589 {
3590         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3591         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3592         irqreturn_t iret = IRQ_HANDLED;
3593         u32 status;
3594
3595         spin_lock(&tegra->lock);
3596         if (tegra->hc_in_elpg) {
3597                 spin_lock(&xhci->lock);
3598                 if (HCD_HW_ACCESSIBLE(hcd)) {
3599                         status = xhci_readl(xhci, &xhci->op_regs->status);
3600                         status |= STS_EINT;
3601                         xhci_writel(xhci, status, &xhci->op_regs->status);
3602                 }
3603                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3604                                 __func__);
3605                 schedule_work(&tegra->host_elpg_exit_work);
3606                 spin_unlock(&xhci->lock);
3607         } else
3608                 iret = xhci_irq(hcd);
3609         spin_unlock(&tegra->lock);
3610
3611         wake_up_interruptible(&tegra->log.intr_wait);
3612
3613         return iret;
3614 }
3615
3616
3617 static const struct hc_driver tegra_plat_xhci_driver = {
3618         .description =          "tegra-xhci",
3619         .product_desc =         "Nvidia xHCI Host Controller",
3620         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3621
3622         /*
3623          * generic hardware linkage
3624          */
3625         .irq =                  tegra_xhci_irq,
3626         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3627
3628         /*
3629          * basic lifecycle operations
3630          */
3631         .reset =                xhci_plat_setup,
3632         .start =                xhci_run,
3633         .stop =                 xhci_stop,
3634         .shutdown =             xhci_shutdown,
3635
3636         /*
3637          * managing i/o requests and associated device resources
3638          */
3639         .urb_enqueue =          xhci_urb_enqueue,
3640         .urb_dequeue =          xhci_urb_dequeue,
3641         .alloc_dev =            xhci_alloc_dev,
3642         .free_dev =             xhci_free_dev,
3643         .alloc_streams =        xhci_alloc_streams,
3644         .free_streams =         xhci_free_streams,
3645         .add_endpoint =         xhci_add_endpoint,
3646         .drop_endpoint =        xhci_drop_endpoint,
3647         .endpoint_reset =       xhci_endpoint_reset,
3648         .check_bandwidth =      xhci_check_bandwidth,
3649         .reset_bandwidth =      xhci_reset_bandwidth,
3650         .address_device =       xhci_address_device,
3651         .update_hub_device =    xhci_update_hub_device,
3652         .reset_device =         xhci_discover_or_reset_device,
3653
3654         /*
3655          * scheduling support
3656          */
3657         .get_frame_number =     xhci_get_frame,
3658
3659         /* Root hub support */
3660         .hub_control =          xhci_hub_control,
3661         .hub_status_data =      xhci_hub_status_data,
3662
3663 #ifdef CONFIG_PM
3664         .bus_suspend =          tegra_xhci_bus_suspend,
3665         .bus_resume =           tegra_xhci_bus_resume,
3666 #endif
3667 };
3668
3669 #ifdef CONFIG_PM
3670 static int
3671 tegra_xhci_suspend(struct platform_device *pdev,
3672                                                 pm_message_t state)
3673 {
3674         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3675         struct xhci_hcd *xhci = tegra->xhci;
3676
3677         int ret = 0;
3678
3679         mutex_lock(&tegra->sync_lock);
3680         if (!tegra->init_done) {
3681                 xhci_warn(xhci, "%s: xhci probe not done\n",
3682                                 __func__);
3683                 mutex_unlock(&tegra->sync_lock);
3684                 return -EBUSY;
3685         }
3686         if (!tegra->hc_in_elpg) {
3687                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3688                                 __func__);
3689                 mutex_unlock(&tegra->sync_lock);
3690                 return -EBUSY;
3691         }
3692         mutex_unlock(&tegra->sync_lock);
3693
3694         /* enable_irq_wake for ss ports */
3695         ret = enable_irq_wake(tegra->padctl_irq);
3696         if (ret < 0) {
3697                 xhci_err(xhci,
3698                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3699                 __func__, tegra->padctl_irq, ret);
3700         }
3701
3702         /* enable_irq_wake for utmip/uhisc wakes */
3703         ret = enable_irq_wake(tegra->usb3_irq);
3704         if (ret < 0) {
3705                 xhci_err(xhci,
3706                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3707                 __func__, tegra->usb3_irq, ret);
3708         }
3709
3710         /* enable_irq_wake for utmip/uhisc wakes */
3711         ret = enable_irq_wake(tegra->usb2_irq);
3712         if (ret < 0) {
3713                 xhci_err(xhci,
3714                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3715                 __func__, tegra->usb2_irq, ret);
3716         }
3717
3718         regulator_disable(tegra->xusb_s1p8v_reg);
3719         regulator_disable(tegra->xusb_s1p05v_reg);
3720         tegra_usb2_clocks_deinit(tegra);
3721
3722         return ret;
3723 }
3724
3725 static int
3726 tegra_xhci_resume(struct platform_device *pdev)
3727 {
3728         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3729         struct xhci_hcd *xhci = tegra->xhci;
3730
3731         dev_dbg(&pdev->dev, "%s\n", __func__);
3732
3733         mutex_lock(&tegra->sync_lock);
3734         if (!tegra->init_done) {
3735                 xhci_warn(xhci, "%s: xhci probe not done\n",
3736                                 __func__);
3737                 mutex_unlock(&tegra->sync_lock);
3738                 return -EBUSY;
3739         }
3740         mutex_unlock(&tegra->sync_lock);
3741
3742         tegra->last_jiffies = jiffies;
3743
3744         disable_irq_wake(tegra->padctl_irq);
3745         disable_irq_wake(tegra->usb3_irq);
3746         disable_irq_wake(tegra->usb2_irq);
3747         tegra->lp0_exit = true;
3748
3749         regulator_enable(tegra->xusb_s1p05v_reg);
3750         regulator_enable(tegra->xusb_s1p8v_reg);
3751         tegra_usb2_clocks_init(tegra);
3752
3753         return 0;
3754 }
3755 #endif
3756
3757 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3758 {
3759         struct platform_device *pdev = tegra->pdev;
3760         int ret;
3761
3762         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
3763                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
3764         if (ret < 0) {
3765                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
3766                 return ret;
3767         }
3768
3769         return ret;
3770 }
3771
3772 static void init_filesystem_firmware_done(const struct firmware *fw,
3773                                         void *context)
3774 {
3775         struct tegra_xhci_hcd *tegra = context;
3776         struct platform_device *pdev = tegra->pdev;
3777         struct cfgtbl *fw_cfgtbl;
3778         size_t fw_size;
3779         void *fw_data;
3780         dma_addr_t fw_dma;
3781         int ret;
3782
3783         mutex_lock(&tegra->sync_lock);
3784
3785         if (fw == NULL) {
3786                 dev_err(&pdev->dev,
3787                         "failed to init firmware from filesystem: %s\n",
3788                         firmware_file);
3789                 goto err_firmware_done;
3790         }
3791
3792         fw_cfgtbl = (struct cfgtbl *) fw->data;
3793         fw_size = fw_cfgtbl->fwimg_len;
3794         dev_info(&pdev->dev, "Firmware File: %s (%d Bytes)\n",
3795                         firmware_file, fw_size);
3796
3797         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
3798                         &fw_dma, GFP_KERNEL);
3799         if (!fw_data) {
3800                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
3801                         __func__);
3802                 goto err_firmware_done;
3803         }
3804
3805         memcpy(fw_data, fw->data, fw_size);
3806         dev_info(&pdev->dev,
3807                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%d Bytes)\n",
3808                 (void *) fw_dma, fw_data, fw_size);
3809
3810         /* all set and ready to go */
3811         tegra->firmware.data = fw_data;
3812         tegra->firmware.dma = fw_dma;
3813         tegra->firmware.size = fw_size;
3814
3815         ret = tegra_xhci_probe2(tegra);
3816         if (ret < 0) {
3817                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
3818                 goto err_firmware_done;
3819         }
3820
3821         release_firmware(fw);
3822         mutex_unlock(&tegra->sync_lock);
3823         return;
3824
3825 err_firmware_done:
3826         release_firmware(fw);
3827         mutex_unlock(&tegra->sync_lock);
3828         device_release_driver(&pdev->dev);
3829 }
3830
3831 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3832 {
3833         struct platform_device *pdev = tegra->pdev;
3834
3835         if (tegra->firmware.data) {
3836                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
3837                         tegra->firmware.data, tegra->firmware.dma);
3838         }
3839
3840         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3841 }
3842 static int init_firmware(struct tegra_xhci_hcd *tegra)
3843 {
3844         return init_filesystem_firmware(tegra);
3845 }
3846
3847 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3848 {
3849         return deinit_filesystem_firmware(tegra);
3850 }
3851
3852 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3853                 struct platform_device *pdev)
3854 {
3855         int err = 0;
3856         /* enable ss clock */
3857         err = clk_enable(tegra->host_clk);
3858         if (err) {
3859                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3860                 goto enable_host_clk_failed;
3861         }
3862
3863         err = clk_enable(tegra->ss_clk);
3864         if (err) {
3865                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3866                 goto eanble_ss_clk_failed;
3867         }
3868
3869         err = clk_enable(tegra->emc_clk);
3870         if (err) {
3871                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3872                 goto eanble_emc_clk_failed;
3873         }
3874
3875         return 0;
3876
3877 eanble_emc_clk_failed:
3878         clk_disable(tegra->ss_clk);
3879
3880 eanble_ss_clk_failed:
3881         clk_disable(tegra->host_clk);
3882
3883 enable_host_clk_failed:
3884         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3885                 clk_disable(tegra->pll_re_vco_clk);
3886         return err;
3887 }
3888
3889 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3890         .boot_media_0                   = 0x0,
3891         .usb2_pad_mux_0                 = 0x4,
3892         .usb2_port_cap_0                = 0x8,
3893         .snps_oc_map_0                  = 0xc,
3894         .usb2_oc_map_0                  = 0x10,
3895         .ss_port_map_0                  = 0x14,
3896         .oc_det_0                       = 0x18,
3897         .elpg_program_0                 = 0x1c,
3898         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3899         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3900         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3901         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3902         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3903         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3904         .usb2_bchrg_bias_pad_0          = 0x28,
3905         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3906         .iophy_pll_p0_ctl1_0            = 0x30,
3907         .iophy_pll_p0_ctl2_0            = 0x34,
3908         .iophy_pll_p0_ctl3_0            = 0x38,
3909         .iophy_pll_p0_ctl4_0            = 0x3c,
3910         .iophy_usb3_pad0_ctl1_0         = 0x40,
3911         .iophy_usb3_pad1_ctl1_0         = 0x44,
3912         .iophy_usb3_pad0_ctl2_0         = 0x48,
3913         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3914         .iophy_usb3_pad0_ctl3_0         = 0x50,
3915         .iophy_usb3_pad1_ctl3_0         = 0x54,
3916         .iophy_usb3_pad0_ctl4_0         = 0x58,
3917         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3918         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3919         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3920         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3921         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3922         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3923         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3924         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3925         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3926         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3927         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3928         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3929         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3930         .usb2_otg_pad0_ctl0_0           = 0x90,
3931         .usb2_otg_pad1_ctl0_0           = 0x94,
3932         .usb2_otg_pad2_ctl0_0           = 0xffff,
3933         .usb2_otg_pad0_ctl1_0           = 0x98,
3934         .usb2_otg_pad1_ctl1_0           = 0x9c,
3935         .usb2_otg_pad2_ctl1_0           = 0xffff,
3936         .usb2_bias_pad_ctl0_0           = 0xa0,
3937         .usb2_bias_pad_ctl1_0           = 0xa4,
3938         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3939         .usb2_hsic_pad1_ctl0_0          = 0xac,
3940         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3941         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3942         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3943         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3944         .ulpi_link_trim_ctl0            = 0xc0,
3945         .ulpi_null_clk_trim_ctl0        = 0xc4,
3946         .hsic_strb_trim_ctl0            = 0xc8,
3947         .wake_ctl0                      = 0xcc,
3948         .pm_spare0                      = 0xd0,
3949         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3950         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3951         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3952         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3953         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3954         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3955         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3956         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3957         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3958         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3959         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3960         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3961         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3962         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3963         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3964         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3965         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3966         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3967         .usb3_pad_mux_0                 = 0xffff,
3968         .iophy_pll_s0_ctl1_0            = 0xffff,
3969         .iophy_pll_s0_ctl2_0            = 0xffff,
3970         .iophy_pll_s0_ctl3_0            = 0xffff,
3971         .iophy_pll_s0_ctl4_0            = 0xffff,
3972         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3973         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3974         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3975         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3976         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3977         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3978 };
3979
3980 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3981         .boot_media_0                   = 0x0,
3982         .usb2_pad_mux_0                 = 0x4,
3983         .usb2_port_cap_0                = 0x8,
3984         .snps_oc_map_0                  = 0xc,
3985         .usb2_oc_map_0                  = 0x10,
3986         .ss_port_map_0                  = 0x14,
3987         .oc_det_0                       = 0x18,
3988         .elpg_program_0                 = 0x1c,
3989         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3990         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3991         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3992         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3993         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3994         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3995         .usb2_bchrg_bias_pad_0          = 0x38,
3996         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3997         .iophy_pll_p0_ctl1_0            = 0x40,
3998         .iophy_pll_p0_ctl2_0            = 0x44,
3999         .iophy_pll_p0_ctl3_0            = 0x48,
4000         .iophy_pll_p0_ctl4_0            = 0x4c,
4001         .iophy_usb3_pad0_ctl1_0         = 0x50,
4002         .iophy_usb3_pad1_ctl1_0         = 0x54,
4003         .iophy_usb3_pad0_ctl2_0         = 0x58,
4004         .iophy_usb3_pad1_ctl2_0         = 0x5c,
4005         .iophy_usb3_pad0_ctl3_0         = 0x60,
4006         .iophy_usb3_pad1_ctl3_0         = 0x64,
4007         .iophy_usb3_pad0_ctl4_0         = 0x68,
4008         .iophy_usb3_pad1_ctl4_0         = 0x6c,
4009         .iophy_misc_pad_p0_ctl1_0       = 0x70,
4010         .iophy_misc_pad_p1_ctl1_0       = 0x74,
4011         .iophy_misc_pad_p0_ctl2_0       = 0x78,
4012         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
4013         .iophy_misc_pad_p0_ctl3_0       = 0x80,
4014         .iophy_misc_pad_p1_ctl3_0       = 0x84,
4015         .iophy_misc_pad_p0_ctl4_0       = 0x88,
4016         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
4017         .iophy_misc_pad_p0_ctl5_0       = 0x90,
4018         .iophy_misc_pad_p1_ctl5_0       = 0x94,
4019         .iophy_misc_pad_p0_ctl6_0       = 0x98,
4020         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
4021         .usb2_otg_pad0_ctl0_0           = 0xa0,
4022         .usb2_otg_pad1_ctl0_0           = 0xa4,
4023         .usb2_otg_pad2_ctl0_0           = 0xa8,
4024         .usb2_otg_pad0_ctl1_0           = 0xac,
4025         .usb2_otg_pad1_ctl1_0           = 0xb0,
4026         .usb2_otg_pad2_ctl1_0           = 0xb4,
4027         .usb2_bias_pad_ctl0_0           = 0xb8,
4028         .usb2_bias_pad_ctl1_0           = 0xbc,
4029         .usb2_hsic_pad0_ctl0_0          = 0xc0,
4030         .usb2_hsic_pad1_ctl0_0          = 0xc4,
4031         .usb2_hsic_pad0_ctl1_0          = 0xc8,
4032         .usb2_hsic_pad1_ctl1_0          = 0xcc,
4033         .usb2_hsic_pad0_ctl2_0          = 0xd0,
4034         .usb2_hsic_pad1_ctl2_0          = 0xd4,
4035         .ulpi_link_trim_ctl0            = 0xd8,
4036         .ulpi_null_clk_trim_ctl0        = 0xdc,
4037         .hsic_strb_trim_ctl0            = 0xe0,
4038         .wake_ctl0                      = 0xe4,
4039         .pm_spare0                      = 0xe8,
4040         .iophy_misc_pad_p2_ctl1_0       = 0xec,
4041         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
4042         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
4043         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
4044         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
4045         .iophy_misc_pad_p4_ctl2_0       = 0x100,
4046         .iophy_misc_pad_p2_ctl3_0       = 0x104,
4047         .iophy_misc_pad_p3_ctl3_0       = 0x108,
4048         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
4049         .iophy_misc_pad_p2_ctl4_0       = 0x110,
4050         .iophy_misc_pad_p3_ctl4_0       = 0x114,
4051         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4052         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4053         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4054         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4055         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4056         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4057         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4058         .usb3_pad_mux_0                 = 0x134,
4059         .iophy_pll_s0_ctl1_0            = 0x138,
4060         .iophy_pll_s0_ctl2_0            = 0x13c,
4061         .iophy_pll_s0_ctl3_0            = 0x140,
4062         .iophy_pll_s0_ctl4_0            = 0x144,
4063         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4064         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4065         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4066         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4067         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4068         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4069 };
4070
4071 /* FIXME: using notifier to transfer control to host from suspend
4072  * for otg port when xhci is in elpg. Find  better alternative
4073  */
4074 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4075                                    unsigned long event, void *unused)
4076 {
4077         struct tegra_xhci_hcd *tegra = container_of(nb,
4078                                         struct tegra_xhci_hcd, otgnb);
4079
4080         if ((event == USB_EVENT_ID))
4081                 if (tegra->hc_in_elpg) {
4082                         schedule_work(&tegra->host_elpg_exit_work);
4083                         tegra->host_resume_req = true;
4084         }
4085
4086         return NOTIFY_OK;
4087 }
4088
4089 static void tegra_xusb_read_board_data(struct tegra_xhci_hcd *tegra)
4090 {
4091         struct tegra_xusb_board_data *bdata = tegra->bdata;
4092         struct device_node *node = tegra->pdev->dev.of_node;
4093         int ret;
4094
4095         bdata->uses_external_pmic = of_property_read_bool(node,
4096                                         "nvidia,uses_external_pmic");
4097         bdata->gpio_controls_muxed_ss_lanes = of_property_read_bool(node,
4098                                         "nvidia,gpio_controls_muxed_ss_lanes");
4099         ret = of_property_read_u32(node, "nvidia,gpio_ss1_sata",
4100                                         &bdata->gpio_ss1_sata);
4101         ret = of_property_read_u32(node, "nvidia,portmap",
4102                                         &bdata->portmap);
4103         ret = of_property_read_u32(node, "nvidia,ss_portmap",
4104                                         (u32 *) &bdata->ss_portmap);
4105         ret = of_property_read_u32(node, "nvidia,lane_owner",
4106                                         (u32 *) &bdata->lane_owner);
4107         ret = of_property_read_u32(node, "nvidia,ulpicap",
4108                                         (u32 *) &bdata->ulpicap);
4109         ret = of_property_read_u8_array(node, "nvidia,hsic0",
4110                                         (u8 *) &bdata->hsic[0],
4111                                         sizeof(bdata->hsic[0]));
4112         ret = of_property_read_u8_array(node, "nvidia,hsic1",
4113                                         (u8 *) &bdata->hsic[1],
4114                                         sizeof(bdata->hsic[0]));
4115         /* TODO: Add error conditions check */
4116 }
4117
4118 static void tegra_xusb_read_calib_data(struct tegra_xhci_hcd *tegra)
4119 {
4120         u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
4121         struct tegra_xusb_chip_calib *cdata = tegra->cdata;
4122
4123         pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
4124         /*
4125          * read from usb_calib0 and pass to driver
4126          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
4127          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
4128          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
4129          * set HS_IREF_CAP              = usb_calib0[14:13]
4130          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
4131          */
4132
4133         cdata->hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
4134         cdata->hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
4135         cdata->hs_squelch_level = (usb_calib0 >> 11) & 0x3;
4136         cdata->hs_iref_cap = (usb_calib0 >> 13) & 0x3;
4137         cdata->hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
4138         cdata->hs_curr_level_pad2 = (usb_calib0 >> 15) & 0x3f;
4139 }
4140
4141 static const struct tegra_xusb_soc_config tegra114_soc_config = {
4142         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4143                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 4),
4144         .quirks = TEGRA_XUSB_USE_HS_SRC_CLOCK2,
4145         .rx_wander = (0x3 << 4),
4146         .rx_eq = (0x3928 << 8),
4147         .cdr_cntl = (0x26 << 24),
4148         .dfe_cntl = 0x002008EE,
4149         .hs_slew = (0xE << 6),
4150         .ls_rslew_pad0 = (0x3 << 14),
4151         .ls_rslew_pad1 = (0x0 << 14),
4152         .hs_disc_lvl = (0x7 << 2),
4153         .spare_in = 0x0,
4154         .supply = {
4155                 .utmi_vbuses = {"usb_vbus0", "usb_vbus1", "usb_vbus2",},
4156                 .s3p3v = "hvdd_usb",
4157                 .s1p8v = "avdd_usb_pll",
4158                 .vddio_hsic = "vddio_hsic",
4159                 .s1p05v = "avddio_usb",
4160         },
4161 };
4162
4163 static const struct tegra_xusb_soc_config tegra124_soc_config = {
4164         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4165                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
4166                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
4167         .rx_wander = (0xF << 4),
4168         .rx_eq = (0xF070 << 8),
4169         .cdr_cntl = (0x26 << 24),
4170         .dfe_cntl = 0x002008EE,
4171         .hs_slew = (0xE << 6),
4172         .ls_rslew_pad0 = (0x3 << 14),
4173         .ls_rslew_pad1 = (0x0 << 14),
4174         .ls_rslew_pad2 = (0x0 << 14),
4175         .hs_disc_lvl = (0x7 << 2),
4176         .spare_in = 0x1,
4177         .supply = {
4178                 .utmi_vbuses = {"usb_vbus0", "usb_vbus1", "usb_vbus2",},
4179                 .s3p3v = "hvdd_usb",
4180                 .s1p8v = "avdd_pll_utmip",
4181                 .vddio_hsic = "vddio_hsic",
4182                 .s1p05v = "avddio_usb",
4183         },
4184 };
4185
4186 static struct of_device_id tegra_xhci_of_match[] = {
4187         { .compatible = "nvidia,tegra114-xhci", .data = &tegra114_soc_config },
4188         { .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_config },
4189         { },
4190 };
4191
4192 static ssize_t hsic_power_show(struct device *dev,
4193                         struct kobj_attribute *attr, char *buf)
4194 {
4195         struct platform_device *pdev = to_platform_device(dev);
4196         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4197         int pad;
4198
4199         for_each_enabled_hsic_pad(pad, tegra) {
4200                 if (&tegra->hsic_power_attr[pad] == attr)
4201                         return sprintf(buf, "%d\n", pad);
4202         }
4203
4204         return sprintf(buf, "-1\n");
4205 }
4206
4207 static ssize_t hsic_power_store(struct device *dev,
4208                         struct kobj_attribute *attr, const char *buf, size_t n)
4209 {
4210         struct platform_device *pdev = to_platform_device(dev);
4211         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4212         enum MBOX_CMD_TYPE msg;
4213         unsigned int on;
4214         int pad, port;
4215         int ret;
4216
4217         if (sscanf(buf, "%u", &on) != 1)
4218                 return -EINVAL;
4219
4220         if (on)
4221                 msg = MBOX_CMD_AIRPLANE_MODE_DISABLED;
4222         else
4223                 msg = MBOX_CMD_AIRPLANE_MODE_ENABLED;
4224
4225         for_each_enabled_hsic_pad(pad, tegra) {
4226                 port = hsic_pad_to_port(pad);
4227
4228                 if (&tegra->hsic_power_attr[pad] == attr) {
4229                         hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
4230                         ret = fw_message_send(tegra, msg, BIT(port + 1));
4231                 }
4232         }
4233
4234         return n;
4235 }
4236
4237 static void hsic_power_remove_file(struct tegra_xhci_hcd *tegra)
4238 {
4239         struct device *dev = &tegra->pdev->dev;
4240         int p;
4241
4242         for_each_enabled_hsic_pad(p, tegra) {
4243                 if (attr_name(tegra->hsic_power_attr[p])) {
4244                         device_remove_file(dev, &tegra->hsic_power_attr[p]);
4245                         kzfree(attr_name(tegra->hsic_power_attr[p]));
4246                 }
4247         }
4248
4249 }
4250
4251 static int hsic_power_create_file(struct tegra_xhci_hcd *tegra)
4252 {
4253         struct device *dev = &tegra->pdev->dev;
4254         int p;
4255         int err;
4256
4257         for_each_enabled_hsic_pad(p, tegra) {
4258                 attr_name(tegra->hsic_power_attr[p]) = kzalloc(16, GFP_KERNEL);
4259                 if (!attr_name(tegra->hsic_power_attr[p]))
4260                         return -ENOMEM;
4261
4262                 snprintf(attr_name(tegra->hsic_power_attr[p]), 16,
4263                         "hsic%d_power", p);
4264                 tegra->hsic_power_attr[p].show = hsic_power_show;
4265                 tegra->hsic_power_attr[p].store = hsic_power_store;
4266                 tegra->hsic_power_attr[p].attr.mode = (S_IRUGO | S_IWUSR);
4267                 sysfs_attr_init(&tegra->hsic_power_attr[p]);
4268
4269                 err = device_create_file(dev, &tegra->hsic_power_attr[p]);
4270                 if (err) {
4271                         kzfree(attr_name(tegra->hsic_power_attr[p]));
4272                         attr_name(tegra->hsic_power_attr[p]) = 0;
4273                         return err;
4274                 }
4275         }
4276
4277         return 0;
4278 }
4279
4280 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4281 static int tegra_xhci_probe(struct platform_device *pdev)
4282 {
4283         struct tegra_xhci_hcd *tegra;
4284         struct resource *res;
4285         unsigned pad;
4286         u32 val;
4287         int ret;
4288         int irq;
4289         const struct tegra_xusb_soc_config *soc_config;
4290         const struct of_device_id *match;
4291
4292         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4293
4294         if (usb_disabled())
4295                 return -ENODEV;
4296
4297         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4298         if (!tegra) {
4299                 dev_err(&pdev->dev, "memory alloc failed\n");
4300                 return -ENOMEM;
4301         }
4302         mutex_init(&tegra->sync_lock);
4303         spin_lock_init(&tegra->lock);
4304         mutex_init(&tegra->mbox_lock);
4305
4306         tegra->init_done = false;
4307
4308         tegra->bdata = devm_kzalloc(&pdev->dev, sizeof(
4309                                         struct tegra_xusb_board_data),
4310                                         GFP_KERNEL);
4311         if (!tegra->bdata) {
4312                 dev_err(&pdev->dev, "memory alloc failed\n");
4313                 return -ENOMEM;
4314         }
4315         tegra->cdata = devm_kzalloc(&pdev->dev, sizeof(
4316                                         struct tegra_xusb_chip_calib),
4317                                         GFP_KERNEL);
4318         if (!tegra->cdata) {
4319                 dev_err(&pdev->dev, "memory alloc failed\n");
4320                 return -ENOMEM;
4321         }
4322         match = of_match_device(tegra_xhci_of_match, &pdev->dev);
4323         if (!match) {
4324                 dev_err(&pdev->dev, "Error: No device match found\n");
4325                 return -ENODEV;
4326         }
4327         soc_config = match->data;
4328         /* Right now device-tree probed devices don't get dma_mask set.
4329          * Since shared usb code relies on it, set it here for now.
4330          * Once we have dma capability bindings this can go away.
4331          */
4332         tegra->tegra_xusb_dmamask = DMA_BIT_MASK(64);
4333         if (!pdev->dev.dma_mask)
4334                 pdev->dev.dma_mask = &tegra->tegra_xusb_dmamask;
4335
4336         tegra->pdev = pdev;
4337         tegra_xusb_read_calib_data(tegra);
4338         tegra_xusb_read_board_data(tegra);
4339         tegra->pdata = dev_get_platdata(&pdev->dev);
4340         tegra->bdata->portmap = tegra->pdata->portmap;
4341         tegra->bdata->hsic[0].pretend_connect =
4342                                 tegra->pdata->pretend_connect_0;
4343         if (tegra->bdata->portmap == NULL)
4344                 return -ENODEV;
4345         tegra->bdata->lane_owner = tegra->pdata->lane_owner;
4346         tegra->soc_config = soc_config;
4347         tegra->ss_pwr_gated = false;
4348         tegra->host_pwr_gated = false;
4349         tegra->hc_in_elpg = false;
4350         tegra->hs_wake_event = false;
4351         tegra->host_resume_req = false;
4352         tegra->lp0_exit = false;
4353
4354         /* request resource padctl base address */
4355         ret = tegra_xhci_request_mem_region(pdev, 3, &tegra->padctl_base);
4356         if (ret) {
4357                 dev_err(&pdev->dev, "failed to map padctl\n");
4358                 return ret;
4359         }
4360
4361         /* request resource fpci base address */
4362         ret = tegra_xhci_request_mem_region(pdev, 1, &tegra->fpci_base);
4363         if (ret) {
4364                 dev_err(&pdev->dev, "failed to map fpci\n");
4365                 return ret;
4366         }
4367
4368         /* request resource ipfs base address */
4369         ret = tegra_xhci_request_mem_region(pdev, 2, &tegra->ipfs_base);
4370         if (ret) {
4371                 dev_err(&pdev->dev, "failed to map ipfs\n");
4372                 return ret;
4373         }
4374
4375         ret = tegra_xusb_partitions_clk_init(tegra);
4376         if (ret) {
4377                 dev_err(&pdev->dev,
4378                         "failed to initialize xusb partitions clocks\n");
4379                 return ret;
4380         }
4381
4382         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4383                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4384                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4385                         dev_err(&pdev->dev, "failed to get usb phy\n");
4386                         tegra->transceiver = NULL;
4387                 }
4388         }
4389
4390         /* Enable power rails to the PAD,VBUS
4391          * and pull-up voltage.Initialize the regulators
4392          */
4393         ret = tegra_xusb_regulator_init(tegra, pdev);
4394         if (ret) {
4395                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4396                 if (ret == -ENODEV) {
4397                         ret = -EPROBE_DEFER;
4398                         dev_err(&pdev->dev, "Retry at a later stage\n");
4399                 }
4400                 goto err_deinit_xusb_partition_clk;
4401         }
4402
4403         /* Enable UTMIP, PLLU and PLLE */
4404         ret = tegra_usb2_clocks_init(tegra);
4405         if (ret) {
4406                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4407                 goto err_deinit_tegra_xusb_regulator;
4408         }
4409
4410         /* tegra_unpowergate_partition also does partition reset deassert */
4411         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4412         if (ret)
4413                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4414
4415         /* tegra_unpowergate_partition also does partition reset deassert */
4416         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4417         if (ret)
4418                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4419
4420         ret = tegra_enable_xusb_clk(tegra, pdev);
4421         if (ret)
4422                 dev_err(&pdev->dev, "could not enable partition clock\n");
4423
4424         /* reset the pointer back to NULL. driver uses it */
4425         /* platform_set_drvdata(pdev, NULL); */
4426
4427         /* request resource host base address */
4428         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4429         if (!res) {
4430                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4431                 ret = -ENODEV;
4432                 goto err_deinit_usb2_clocks;
4433         }
4434         tegra->host_phy_base = res->start;
4435         tegra->host_phy_size = resource_size(res);
4436
4437         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4438                                 res->start, resource_size(res));
4439         if (!tegra->host_phy_virt_base) {
4440                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4441                 ret = -ENOMEM;
4442                 goto err_deinit_usb2_clocks;
4443         }
4444
4445         /* Setup IPFS access and BAR0 space */
4446         tegra_xhci_cfg(tegra);
4447
4448         val = readl(tegra->fpci_base + XUSB_CFG_0);
4449         tegra->device_id = (val >> 16) & 0xffff;
4450
4451         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4452                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4453
4454         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4455                 tegra->padregs = &t114_padregs_offset;
4456         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4457                 tegra->padregs = &t124_padregs_offset;
4458         } else {
4459                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4460                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4461                 tegra->padregs = &t124_padregs_offset;
4462         }
4463
4464         /* calculate rctrl_val and tctrl_val once at boot time */
4465         /* Issue is only applicable for T114 */
4466         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4467                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4468
4469         for_each_enabled_hsic_pad(pad, tegra)
4470                 hsic_power_rail_enable(tegra);
4471
4472         /* Program the XUSB pads to take ownership of ports */
4473         tegra_xhci_padctl_portmap_and_caps(tegra);
4474
4475         /* Release XUSB wake logic state latching */
4476         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4477         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4478
4479         /* Deassert reset to XUSB host, ss, dev clocks */
4480         tegra_periph_reset_deassert(tegra->host_clk);
4481         tegra_periph_reset_deassert(tegra->ss_clk);
4482
4483         platform_set_drvdata(pdev, tegra);
4484         fw_log_init(tegra);
4485         ret = init_firmware(tegra);
4486         if (ret < 0) {
4487                 dev_err(&pdev->dev, "failed to init firmware\n");
4488                 ret = -ENODEV;
4489                 goto err_deinit_firmware_log;
4490         }
4491
4492         return 0;
4493
4494 err_deinit_firmware_log:
4495         fw_log_deinit(tegra);
4496 err_deinit_usb2_clocks:
4497         tegra_usb2_clocks_deinit(tegra);
4498 err_deinit_tegra_xusb_regulator:
4499         tegra_xusb_regulator_deinit(tegra);
4500 err_deinit_xusb_partition_clk:
4501         if (tegra->transceiver)
4502                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4503
4504         tegra_xusb_partitions_clk_deinit(tegra);
4505
4506         return ret;
4507 }
4508
4509 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
4510 {
4511         struct platform_device *pdev = tegra->pdev;
4512         const struct hc_driver *driver;
4513         int ret;
4514         struct resource *res;
4515         int irq;
4516         struct xhci_hcd *xhci;
4517         struct usb_hcd  *hcd;
4518         unsigned port;
4519
4520
4521         ret = load_firmware(tegra, false /* do reset ARU */);
4522         if (ret < 0) {
4523                 dev_err(&pdev->dev, "failed to load firmware\n");
4524                 return -ENODEV;
4525         }
4526         pmc_init(tegra);
4527
4528         device_init_wakeup(&pdev->dev, 1);
4529         driver = &tegra_plat_xhci_driver;
4530
4531         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4532         if (!hcd) {
4533                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4534                 return -ENOMEM;
4535         }
4536
4537         /* request resource host base address */
4538         ret = tegra_xhci_request_mem_region(pdev, 0, &hcd->regs);
4539         if (ret) {
4540                 dev_err(&pdev->dev, "failed to map host\n");
4541                 goto err_put_usb2_hcd;
4542         }
4543         hcd->rsrc_start = tegra->host_phy_base;
4544         hcd->rsrc_len = tegra->host_phy_size;
4545
4546         /* Register interrupt handler for HOST */
4547         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4548         if (!res) {
4549                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4550                 ret = -ENODEV;
4551                 goto err_put_usb2_hcd;
4552         }
4553
4554         irq = res->start;
4555         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4556         if (ret) {
4557                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4558                 goto err_put_usb2_hcd;
4559         }
4560
4561         /* USB 2.0 roothub is stored in the platform_device now. */
4562         hcd = dev_get_drvdata(&pdev->dev);
4563         xhci = hcd_to_xhci(hcd);
4564         tegra->xhci = xhci;
4565         platform_set_drvdata(pdev, tegra);
4566
4567         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4568                 if (!IS_ERR_OR_NULL(tegra->transceiver)) {
4569                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4570                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4571                         usb_register_notifier(tegra->transceiver,
4572                                 &tegra->otgnb);
4573                 }
4574         }
4575
4576         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4577                                                 dev_name(&pdev->dev), hcd);
4578         if (!xhci->shared_hcd) {
4579                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4580                 ret = -ENOMEM;
4581                 goto err_remove_usb2_hcd;
4582         }
4583
4584         /*
4585          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4586          * is called by usb_add_hcd().
4587          */
4588         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4589
4590         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4591         if (ret) {
4592                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4593                 goto err_put_usb3_hcd;
4594         }
4595
4596         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4597         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4598
4599         /* do mailbox related initializations */
4600         tegra->mbox_owner = 0xffff;
4601         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4602
4603         /* do ss partition elpg exit related initialization */
4604         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4605
4606         /* do host partition elpg exit related initialization */
4607         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4608
4609         /* Register interrupt handler for SMI line to handle mailbox
4610          * interrupt from firmware
4611          */
4612
4613         ret = tegra_xhci_request_irq(pdev, 1, tegra_xhci_smi_irq,
4614                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4615         if (ret != 0)
4616                 goto err_remove_usb3_hcd;
4617
4618         /* Register interrupt handler for PADCTRL line to
4619          * handle wake on connect irqs interrupt from
4620          * firmware
4621          */
4622         ret = tegra_xhci_request_irq(pdev, 2, tegra_xhci_padctl_irq,
4623                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4624                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4625         if (ret != 0)
4626                 goto err_remove_usb3_hcd;
4627
4628         /* Register interrupt wake handler for USB2 */
4629         ret = tegra_xhci_request_irq(pdev, 4, pmc_usb_phy_wake_isr,
4630                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4631                 &tegra->usb2_irq);
4632         if (ret != 0)
4633                 goto err_remove_usb3_hcd;
4634
4635         /* Register interrupt wake handler for USB3 */
4636         ret = tegra_xhci_request_irq(pdev, 3, pmc_usb_phy_wake_isr,
4637                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4638                 &tegra->usb3_irq);
4639         if (ret != 0)
4640                 goto err_remove_usb3_hcd;
4641
4642         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4643                 tegra->ctle_ctx_saved[port] = false;
4644                 tegra->dfe_ctx_saved[port] = false;
4645         }
4646
4647         tegra_xhci_enable_fw_message(tegra);
4648         hsic_pad_pretend_connect(tegra);
4649
4650         tegra_xhci_debug_read_pads(tegra);
4651         utmi_phy_pad_enable();
4652         utmi_phy_iddq_override(false);
4653
4654         tegra_pd_add_device(&pdev->dev);
4655         pm_runtime_enable(&pdev->dev);
4656
4657         hsic_power_create_file(tegra);
4658         tegra->init_done = true;
4659
4660         return 0;
4661
4662 err_remove_usb3_hcd:
4663         usb_remove_hcd(xhci->shared_hcd);
4664 err_put_usb3_hcd:
4665         usb_put_hcd(xhci->shared_hcd);
4666 err_remove_usb2_hcd:
4667         kfree(tegra->xhci);
4668         usb_remove_hcd(hcd);
4669 err_put_usb2_hcd:
4670         usb_put_hcd(hcd);
4671
4672         return ret;
4673 }
4674
4675 static int tegra_xhci_remove(struct platform_device *pdev)
4676 {
4677         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4678         unsigned pad;
4679
4680         if (tegra == NULL)
4681                 return -EINVAL;
4682
4683         mutex_lock(&tegra->sync_lock);
4684
4685         for_each_enabled_hsic_pad(pad, tegra) {
4686                 hsic_pad_disable(tegra, pad);
4687                 hsic_power_rail_disable(tegra);
4688         }
4689
4690         if (tegra->init_done) {
4691                 struct xhci_hcd *xhci = NULL;
4692                 struct usb_hcd *hcd = NULL;
4693
4694                 xhci = tegra->xhci;
4695                 hcd = xhci_to_hcd(xhci);
4696
4697                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4698                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4699                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4700                 usb_remove_hcd(xhci->shared_hcd);
4701                 usb_put_hcd(xhci->shared_hcd);
4702                 usb_remove_hcd(hcd);
4703                 usb_put_hcd(hcd);
4704                 kfree(xhci);
4705         }
4706
4707         deinit_firmware(tegra);
4708         fw_log_deinit(tegra);
4709
4710         tegra_xusb_regulator_deinit(tegra);
4711
4712         if (tegra->transceiver)
4713                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4714
4715         tegra_usb2_clocks_deinit(tegra);
4716         if (!tegra->hc_in_elpg)
4717                 tegra_xusb_partitions_clk_deinit(tegra);
4718
4719         utmi_phy_pad_disable();
4720         utmi_phy_iddq_override(true);
4721
4722         tegra_pd_remove_device(&pdev->dev);
4723         platform_set_drvdata(pdev, NULL);
4724
4725         hsic_power_remove_file(tegra);
4726         mutex_unlock(&tegra->sync_lock);
4727
4728         return 0;
4729 }
4730
4731 static void tegra_xhci_shutdown(struct platform_device *pdev)
4732 {
4733         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4734         struct xhci_hcd *xhci = NULL;
4735         struct usb_hcd *hcd = NULL;
4736
4737         if (tegra == NULL)
4738                 return;
4739
4740         if (tegra->hc_in_elpg) {
4741                 pmc_disable_bus_ctrl(tegra);
4742         } else {
4743                 xhci = tegra->xhci;
4744                 hcd = xhci_to_hcd(xhci);
4745                 xhci_shutdown(hcd);
4746         }
4747 }
4748
4749 static struct platform_driver tegra_xhci_driver = {
4750         .probe  = tegra_xhci_probe,
4751         .remove = tegra_xhci_remove,
4752         .shutdown = tegra_xhci_shutdown,
4753 #ifdef CONFIG_PM
4754         .suspend = tegra_xhci_suspend,
4755         .resume  = tegra_xhci_resume,
4756 #endif
4757         .driver = {
4758                 .name = "tegra-xhci",
4759                 .of_match_table = tegra_xhci_of_match,
4760         },
4761 };
4762 MODULE_ALIAS("platform:tegra-xhci");
4763
4764 int tegra_xhci_register_plat(void)
4765 {
4766         return platform_driver_register(&tegra_xhci_driver);
4767 }
4768
4769 void tegra_xhci_unregister_plat(void)
4770 {
4771         platform_driver_unregister(&tegra_xhci_driver);
4772 }