drivers/iio/imu/nvi_mpu/nvi_icm.c

   1 /* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   2  *
   3  * This software is licensed under the terms of the GNU General Public
   4  * License version 2, as published by the Free Software Foundation, and
   5  * may be copied, distributed, and modified under those terms.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/time.h>
  15 #include <linux/delay.h>
  16 #include "nvi.h"
  17 #include "nvi_dmp_icm.h"
  18
  19 #define BYTES_PER_SENSOR                6
  20 /* full scale and LPF setting */
  21 #define ICM_SELFTEST_GYRO_FS            ((0 << 3) | 1)
  22 #define ICM_SELFTEST_ACCEL_FS           ((7 << 3) | 1)
  23 /* register settings */
  24 #define ICM_SELFTEST_GYRO_SMPLRT_DIV    10
  25 #define ICM_SELFTEST_GYRO_AVGCFG        3
  26 #define ICM_SELFTEST_ACCEL_SMPLRT_DIV   10
  27 #define ICM_SELFTEST_ACCEL_DEC3_CFG     2
  28 #define ICM_SELFTEST_GYRO_SENS          (32768 / 250)
  29 #define BIT_ACCEL_CTEN                  0x1C
  30 #define BIT_GYRO_CTEN                   0x38
  31 /* wait time before collecting data */
  32 #define ICM_MAX_PACKETS                 20
  33 #define ICM_SELFTEST_WAIT_TIME          (ICM_MAX_PACKETS * 10)
  34 #define ICM_GYRO_ENGINE_UP_TIME         50
  35 #define ICM_ST_STABLE_TIME              20
  36 #define ICM_GYRO_SCALE                  131
  37 #define ICM_ST_PRECISION                1000
  38 #define ICM_ST_ACCEL_FS_MG              2000UL
  39 #define ICM_ST_SCALE                    32768
  40 #define ICM_ST_TRY_TIMES                2
  41 #define ICM_ST_SAMPLES                  200
  42 #define ICM_ACCEL_ST_SHIFT_DELTA_MIN    500
  43 #define ICM_ACCEL_ST_SHIFT_DELTA_MAX    1500
  44 #define ICM_GYRO_CT_SHIFT_DELTA         500
  45 /* Gyro Offset Max Value (dps) */
  46 #define ICM_GYRO_OFFSET_MAX             20
  47 /* Gyro Self Test Absolute Limits ST_AL (dps) */
  48 #define ICM_GYRO_ST_AL                  60
  49 /* Accel Self Test Absolute Limits ST_AL (mg) */
  50 #define ICM_ACCEL_ST_AL_MIN ((225 * ICM_ST_SCALE \
  51                               / ICM_ST_ACCEL_FS_MG) * ICM_ST_PRECISION)
  52 #define ICM_ACCEL_ST_AL_MAX ((675 * ICM_ST_SCALE \
  53                               / ICM_ST_ACCEL_FS_MG) * ICM_ST_PRECISION)
  54
  55
  56 static const u16 icm_st_tb[256] = {
  57         2620, 2646, 2672, 2699, 2726, 2753, 2781, 2808,
  58         2837, 2865, 2894, 2923, 2952, 2981, 3011, 3041,
  59         3072, 3102, 3133, 3165, 3196, 3228, 3261, 3293,
  60         3326, 3359, 3393, 3427, 3461, 3496, 3531, 3566,
  61         3602, 3638, 3674, 3711, 3748, 3786, 3823, 3862,
  62         3900, 3939, 3979, 4019, 4059, 4099, 4140, 4182,
  63         4224, 4266, 4308, 4352, 4395, 4439, 4483, 4528,
  64         4574, 4619, 4665, 4712, 4759, 4807, 4855, 4903,
  65         4953, 5002, 5052, 5103, 5154, 5205, 5257, 5310,
  66         5363, 5417, 5471, 5525, 5581, 5636, 5693, 5750,
  67         5807, 5865, 5924, 5983, 6043, 6104, 6165, 6226,
  68         6289, 6351, 6415, 6479, 6544, 6609, 6675, 6742,
  69         6810, 6878, 6946, 7016, 7086, 7157, 7229, 7301,
  70         7374, 7448, 7522, 7597, 7673, 7750, 7828, 7906,
  71         7985, 8065, 8145, 8227, 8309, 8392, 8476, 8561,
  72         8647, 8733, 8820, 8909, 8998, 9088, 9178, 9270,
  73         9363, 9457, 9551, 9647, 9743, 9841, 9939, 10038,
  74         10139, 10240, 10343, 10446, 10550, 10656, 10763, 10870,
  75         10979, 11089, 11200, 11312, 11425, 11539, 11654, 11771,
  76         11889, 12008, 12128, 12249, 12371, 12495, 12620, 12746,
  77         12874, 13002, 13132, 13264, 13396, 13530, 13666, 13802,
  78         13940, 14080, 14221, 14363, 14506, 14652, 14798, 14946,
  79         15096, 15247, 15399, 15553, 15709, 15866, 16024, 16184,
  80         16346, 16510, 16675, 16842, 17010, 17180, 17352, 17526,
  81         17701, 17878, 18057, 18237, 18420, 18604, 18790, 18978,
  82         19167, 19359, 19553, 19748, 19946, 20145, 20347, 20550,
  83         20756, 20963, 21173, 21385, 21598, 21814, 22033, 22253,
  84         22475, 22700, 22927, 23156, 23388, 23622, 23858, 24097,
  85         24338, 24581, 24827, 25075, 25326, 25579, 25835, 26093,
  86         26354, 26618, 26884, 27153, 27424, 27699, 27976, 28255,
  87         28538, 28823, 29112, 29403, 29697, 29994, 30294, 30597,
  88         30903, 31212, 31524, 31839, 32157, 32479, 32804
  89 };
  90
  91 /**
  92 * inv_icm_st_gyr_chk() - check gyro self test.
  93 *  this function returns zero as success. A non-zero return
  94 *  value indicates failure in self test.
  95 *  @*st: main data structure.
  96 *  @*reg_avg: average value of normal test.
  97 *  @*st_avg: average value of self test
  98 */
  99 static int inv_icm_st_gyr_chk(struct nvi_state *st, int *reg_avg, int *st_avg)
 100 {
 101         u8 *regs;
 102         int ret = 0;
 103         int otp_value_zero = 0;
 104         int st_shift_prod[AXIS_N];
 105         int st_shift_cust[AXIS_N];
 106         int i;
 107
 108         regs = &st->st_data[DEV_GYR][0];
 109         if (st->sts & NVI_DBG_SPEW_MSG)
 110                 dev_info(&st->i2c->dev, "%s data: %02x %02x %02x\n",
 111                          __func__, regs[0], regs[1], regs[2]);
 112         for (i = 0; i < AXIS_N; i++) {
 113                 if (regs[i] != 0) {
 114                         st_shift_prod[i] = icm_st_tb[regs[i] - 1];
 115                 } else {
 116                         st_shift_prod[i] = 0;
 117                         otp_value_zero = 1;
 118                 }
 119         }
 120         if (st->sts & NVI_DBG_SPEW_MSG)
 121                 dev_info(&st->i2c->dev,
 122                          "%s st_shift_prod: %+d %+d %+d\n", __func__,
 123                          st_shift_prod[0], st_shift_prod[1], st_shift_prod[2]);
 124         for (i = 0; i < AXIS_N; i++) {
 125                 st_shift_cust[i] = st_avg[i] - reg_avg[i];
 126                 if (!otp_value_zero) {
 127                         /* Self Test Pass/Fail Criteria A */
 128                         if (st_shift_cust[i] < (ICM_GYRO_CT_SHIFT_DELTA *
 129                                                 st_shift_prod[i])) {
 130                                 ret = 1;
 131                                 if (st->sts & NVI_DBG_SPEW_MSG)
 132                                         dev_info(&st->i2c->dev,
 133                                                  "%s FAIL A axis %d\n",
 134                                                  __func__, i);
 135                         }
 136                 } else {
 137                         /* Self Test Pass/Fail Criteria B */
 138                         if (st_shift_cust[i] < (ICM_GYRO_ST_AL *
 139                                                 ICM_SELFTEST_GYRO_SENS *
 140                                                 ICM_ST_PRECISION)) {
 141                                 ret = 1;
 142                                 if (st->sts & NVI_DBG_SPEW_MSG)
 143                                         dev_info(&st->i2c->dev,
 144                                                  "%s FAIL B axis %d\n",
 145                                                  __func__, i);
 146                         }
 147                 }
 148         }
 149
 150         if (st->sts & NVI_DBG_SPEW_MSG)
 151                 dev_info(&st->i2c->dev, "%s st_shift_cust: %+d %+d %+d\n",
 152                          __func__,
 153                          st_shift_cust[0], st_shift_cust[1], st_shift_cust[2]);
 154         if (ret == 0) {
 155                 /* Self Test Pass/Fail Criteria C */
 156                 for (i = 0; i < AXIS_N; i++) {
 157                         if (abs(reg_avg[i]) > (ICM_GYRO_OFFSET_MAX *
 158                                                ICM_SELFTEST_GYRO_SENS *
 159                                                ICM_ST_PRECISION)) {
 160                                 ret = 1;
 161                                 if (st->sts & NVI_DBG_SPEW_MSG)
 162                                         dev_info(&st->i2c->dev,
 163                                                  "%s FAIL C axis %d\n",
 164                                                  __func__, i);
 165                         }
 166                 }
 167         }
 168
 169         return ret;
 170 }
 171
 172 /**
 173 * inv_icm_st_acc_chk() - check accel self test.
 174 *  this function returns zero as success. A non-zero return
 175 *  value indicates failure in self test.
 176 *  @*st: main data structure.
 177 *  @*reg_avg: average value of normal test.
 178 *  @*st_avg: average value of self test
 179 */
 180 static int inv_icm_st_acc_chk(struct nvi_state *st, int *reg_avg, int *st_avg)
 181 {
 182         u8 *regs;
 183         int i;
 184         int st_shift_prod[AXIS_N];
 185         int st_shift_cust[AXIS_N];
 186         int otp_value_zero = 0;
 187         int ret = 0;
 188
 189         regs = &st->st_data[DEV_ACC][0];
 190         if (st->sts & NVI_DBG_SPEW_MSG)
 191                 dev_info(&st->i2c->dev, "%s data: %02x %02x %02x\n",
 192                          __func__, regs[0], regs[1], regs[2]);
 193         for (i = 0; i < AXIS_N; i++) {
 194                 if (regs[i] != 0) {
 195                         st_shift_prod[i] = icm_st_tb[regs[i] - 1];
 196                 } else {
 197                         st_shift_prod[i] = 0;
 198                         otp_value_zero = 1;
 199                 }
 200         }
 201
 202         if (st->sts & NVI_DBG_SPEW_MSG)
 203                 dev_info(&st->i2c->dev,
 204                          "%s st_shift_prod: %+d %+d %+d\n", __func__,
 205                          st_shift_prod[0], st_shift_prod[1], st_shift_prod[2]);
 206         if (!otp_value_zero) {
 207                 /* Self Test Pass/Fail Criteria A */
 208                 for (i = 0; i < AXIS_N; i++) {
 209                         st_shift_cust[i] = st_avg[i] - reg_avg[i];
 210                         if (st_shift_cust[i] < (ICM_ACCEL_ST_SHIFT_DELTA_MIN *
 211                                                 st_shift_prod[i])) {
 212                                 ret = 1;
 213                                 if (st->sts & NVI_DBG_SPEW_MSG)
 214                                         dev_info(&st->i2c->dev,
 215                                                  "%s FAIL A (min) axis %d\n",
 216                                                  __func__, i);
 217                         }
 218                         if (st_shift_cust[i] > (ICM_ACCEL_ST_SHIFT_DELTA_MAX *
 219                                                 st_shift_prod[i])) {
 220                                 ret = 1;
 221                                 if (st->sts & NVI_DBG_SPEW_MSG)
 222                                         dev_info(&st->i2c->dev,
 223                                                  "%s FAIL A (max) axis %d\n",
 224                                                  __func__, i);
 225                         }
 226                 }
 227         } else {
 228                 /* Self Test Pass/Fail Criteria B */
 229                 for (i = 0; i < AXIS_N; i++) {
 230                         st_shift_cust[i] = abs(st_avg[i] - reg_avg[i]);
 231                         if ((st_shift_cust[i] < ICM_ACCEL_ST_AL_MIN) ||
 232                                     (st_shift_cust[i] > ICM_ACCEL_ST_AL_MAX)) {
 233                                 ret = 1;
 234                                 if (st->sts & NVI_DBG_SPEW_MSG)
 235                                         dev_info(&st->i2c->dev,
 236                                                  "%s FAIL B axis %d\n",
 237                                                  __func__, i);
 238                         }
 239                 }
 240         }
 241
 242         if (st->sts & NVI_DBG_SPEW_MSG)
 243                 dev_info(&st->i2c->dev, "%s st_shift_cust: %+d %+d %+d\n",
 244                          __func__,
 245                          st_shift_cust[0], st_shift_cust[1], st_shift_cust[2]);
 246         return ret;
 247 }
 248
 249 static int inv_icm_st_setup(struct nvi_state *st)
 250 {
 251         int axis;
 252         int ret;
 253
 254         /* Wake up and stop sensors */
 255         ret = nvi_pm_wr(st, __func__, INV_CLK_PLL, BIT_PWR_PRESSURE_STBY |
 256                         BIT_PWR_ACCEL_STBY | BIT_PWR_GYRO_STBY, 0);
 257         /* Perform a soft-reset of the chip
 258          * This will clear any prior states in the chip
 259          */
 260         ret |= nvi_wr_pm1(st, __func__, BIT_H_RESET);
 261         if (ret)
 262                 return ret;
 263
 264         msleep(POWER_UP_TIME);
 265         /* Wake up */
 266         ret = nvi_wr_pm1(st, __func__, INV_CLK_PLL);
 267         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->user_ctrl, BIT_FIFO_EN,
 268                             __func__, &st->rc.user_ctrl);
 269         /* Configure FIFO */
 270         ret |= nvi_wr_fifo_cfg(st, -1);
 271         /* Set cycle mode */
 272         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->lp_config, 0x70,
 273                             __func__, &st->rc.lp_config);
 274         /* Configure FSR and DLPF */
 275         ret |= nvi_i2c_write_rc(st, &st->hal->reg->smplrt[DEV_GYR],
 276                                 ICM_SELFTEST_GYRO_SMPLRT_DIV, __func__,
 277                                 (u8 *)&st->rc.smplrt[DEV_GYR], true);
 278         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1,
 279                              ICM_SELFTEST_GYRO_FS,
 280                              __func__, &st->rc.gyro_config1);
 281         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2,
 282                              ICM_SELFTEST_GYRO_AVGCFG,
 283                              __func__, &st->rc.gyro_config2);
 284         ret |= nvi_i2c_write_rc(st, &st->hal->reg->smplrt[DEV_ACC],
 285                                 ICM_SELFTEST_ACCEL_SMPLRT_DIV, __func__,
 286                                 (u8 *)&st->rc.smplrt[DEV_ACC], true);
 287         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config,
 288                              ICM_SELFTEST_ACCEL_FS,
 289                              __func__, &st->rc.accel_config);
 290         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2,
 291                              ICM_SELFTEST_ACCEL_DEC3_CFG,
 292                              __func__, &st->rc.accel_config2);
 293         if (ret)
 294                 return ret;
 295
 296         /* Read selftest values */
 297         for (axis = 0; axis < AXIS_N; axis++)
 298                 ret |= nvi_i2c_rd(st, &st->hal->reg->self_test_g[axis],
 299                                   &st->st_data[DEV_GYR][axis]);
 300
 301         for (axis = 0; axis < AXIS_N; axis++)
 302                 ret |= nvi_i2c_rd(st, &st->hal->reg->self_test_a[axis],
 303                                   &st->st_data[DEV_ACC][axis]);
 304
 305         ret |= nvi_pm_wr(st, __func__, INV_CLK_PLL,
 306                          BIT_PWR_PRESSURE_STBY, 0x70);
 307         if (ret)
 308                 return ret;
 309
 310         msleep(ICM_GYRO_ENGINE_UP_TIME);
 311         return ret;
 312 }
 313
 314 static int inv_icm_st_rd(struct nvi_state *st, int dev,
 315                          int *sum_result, int *s)
 316 {
 317         u16 fifo_count;
 318         s16 vals[AXIS_N];
 319         u8 d[ICM_MAX_PACKETS * BYTES_PER_SENSOR];
 320         int packet_count;
 321         int i;
 322         int j;
 323         int t;
 324         int ret;
 325
 326         ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en, 0,
 327                                __func__, (u8 *)&st->rc.fifo_en, false);
 328         /* Reset FIFO */
 329         ret |= nvi_i2c_wr(st, &st->hal->reg->fifo_rst,
 330                           0x1F, __func__);
 331         ret |= nvi_i2c_wr(st, &st->hal->reg->fifo_rst,
 332                           0x1E, __func__);
 333         if (ret)
 334                 return ret;
 335
 336         while (*s < ICM_ST_SAMPLES) {
 337                 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en,
 338                                        st->hal->dev[dev]->fifo_en_msk,
 339                                        __func__, (u8 *)&st->rc.fifo_en, false);
 340                 if (ret)
 341                         return ret;
 342
 343                 msleep(ICM_SELFTEST_WAIT_TIME);
 344                 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en, 0,
 345                                        __func__, (u8 *)&st->rc.fifo_en, false);
 346                 if (ret)
 347                         return ret;
 348
 349                 ret = nvi_i2c_rd(st, &st->hal->reg->fifo_count_h, d);
 350                 if (ret)
 351                         return ret;
 352
 353                 fifo_count = be16_to_cpup((__be16 *)(&d[0]));
 354                 if (st->sts & NVI_DBG_SPEW_MSG)
 355                         dev_info(&st->i2c->dev, "%s fifo_count=%d\n",
 356                                  __func__, fifo_count);
 357                 if (ICM_MAX_PACKETS * BYTES_PER_SENSOR < fifo_count) {
 358                         ret = nvi_i2c_r(st, st->hal->reg->fifo_rw.bank,
 359                                         st->hal->reg->fifo_rw.reg,
 360                                         ICM_MAX_PACKETS * BYTES_PER_SENSOR, d);
 361                         packet_count = ICM_MAX_PACKETS;
 362                 } else {
 363                         ret = nvi_i2c_r(st, st->hal->reg->fifo_rw.bank,
 364                                         st->hal->reg->fifo_rw.reg,
 365                                         fifo_count, d);
 366                         packet_count = fifo_count / BYTES_PER_SENSOR;
 367                 }
 368                 if (ret)
 369                         return ret;
 370
 371                 i = 0;
 372                 while (i < packet_count) {
 373                         for (j = 0; j < AXIS_N; j++) {
 374                                 t = 2 * j + i * BYTES_PER_SENSOR;
 375                                 vals[j] = (s16)be16_to_cpup((__be16 *)(&d[t]));
 376                                 sum_result[j] += vals[j];
 377                         }
 378                         if (st->sts & NVI_DBG_SPEW_MSG)
 379                                 dev_info(&st->i2c->dev,
 380                                          "%s %s %d: %+d %+d %+d\n",
 381                                          __func__, st->snsr[dev].cfg.name,
 382                                          *s, vals[0], vals[1], vals[2]);
 383                         (*s)++;
 384                         i++;
 385                 }
 386         }
 387
 388         return 0;
 389 }
 390
 391 /*
 392  *  inv_icm_st_acc_do() - do the actual test of self testing
 393  */
 394 static int inv_icm_st_acc_do(struct nvi_state *st,
 395                              int *accel_result, int *accel_st_result)
 396 {
 397         int accel_s;
 398         int i;
 399         int j;
 400         int ret;
 401
 402         for (i = 0; i < AXIS_N; i++) {
 403                 accel_result[i] = 0;
 404                 accel_st_result[i] = 0;
 405         }
 406         accel_s = 0;
 407         ret = inv_icm_st_rd(st, DEV_ACC, accel_result, &accel_s);
 408         if (ret || accel_s <= 0)
 409                 return -1;
 410
 411         for (j = 0; j < AXIS_N; j++) {
 412                 accel_result[j] = accel_result[j] / accel_s;
 413                 accel_result[j] *= ICM_ST_PRECISION;
 414         }
 415         /* Set Self-Test Bit */
 416         ret = nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2,
 417                             BIT_ACCEL_CTEN | ICM_SELFTEST_ACCEL_DEC3_CFG,
 418                             __func__, &st->rc.accel_config2);
 419         if (ret)
 420                 return ret;
 421
 422         msleep(ICM_ST_STABLE_TIME);
 423         accel_s = 0;
 424         ret = inv_icm_st_rd(st, DEV_ACC, accel_st_result, &accel_s);
 425         if (ret || accel_s <= 0)
 426                 return -1;
 427
 428         for (j = 0; j < AXIS_N; j++) {
 429                 accel_st_result[j] = accel_st_result[j] / accel_s;
 430                 accel_st_result[j] *= ICM_ST_PRECISION;
 431         }
 432         if (st->sts & NVI_DBG_SPEW_MSG)
 433                 dev_info(&st->i2c->dev, "%s %d, %d, %d\n", __func__,
 434                          accel_result[0], accel_result[1], accel_result[2]);
 435
 436         return 0;
 437 }
 438
 439 /*
 440  *  inv_icm_st_gyr_do() - do the actual test of self testing
 441  */
 442 static int inv_icm_st_gyr_do(struct nvi_state *st,
 443                              int *gyro_result, int *gyro_st_result)
 444 {
 445         int gyro_s;
 446         int i;
 447         int j;
 448         int ret;
 449
 450         for (i = 0; i < AXIS_N; i++) {
 451                 gyro_result[i] = 0;
 452                 gyro_st_result[i] = 0;
 453         }
 454         gyro_s = 0;
 455         ret = inv_icm_st_rd(st, DEV_GYR, gyro_result, &gyro_s);
 456         if (ret || gyro_s <= 0)
 457                 return -1;
 458
 459         for (j = 0; j < AXIS_N; j++) {
 460                 gyro_result[j] = gyro_result[j] / gyro_s;
 461                 gyro_result[j] *= ICM_ST_PRECISION;
 462         }
 463         /* Set Self-Test Bit */
 464         ret = nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2,
 465                             BIT_GYRO_CTEN | ICM_SELFTEST_GYRO_AVGCFG,
 466                             __func__, &st->rc.gyro_config2);
 467         if (ret)
 468                 return ret;
 469
 470         msleep(ICM_ST_STABLE_TIME);
 471         gyro_s = 0;
 472         ret = inv_icm_st_rd(st, DEV_GYR, gyro_st_result, &gyro_s);
 473         if (ret || gyro_s <= 0)
 474                 return -1;
 475
 476         for (j = 0; j < AXIS_N; j++) {
 477                 gyro_st_result[j] = gyro_st_result[j] / gyro_s;
 478                 gyro_st_result[j] *= ICM_ST_PRECISION;
 479         }
 480         if (st->sts & NVI_DBG_SPEW_MSG)
 481                 dev_info(&st->i2c->dev, "%s %d, %d, %d\n", __func__,
 482                          gyro_result[0], gyro_result[1], gyro_result[2]);
 483         return 0;
 484 }
 485
 486 static int inv_st_gyr_icm(struct nvi_state *st)
 487 {
 488         int ret;
 489         int gyr_bias_st[AXIS_N];
 490         int gyr_bias_regular[AXIS_N];
 491         int test_times;
 492         int i;
 493         char gyro_result;
 494
 495         ret = inv_icm_st_setup(st);
 496         if (ret)
 497                 return ret;
 498
 499         test_times = ICM_ST_TRY_TIMES;
 500         while (test_times > 0) {
 501                 ret = inv_icm_st_gyr_do(st, gyr_bias_regular, gyr_bias_st);
 502                 if (ret == -EAGAIN)
 503                         test_times--;
 504                 else
 505                         test_times = 0;
 506         }
 507         if (ret)
 508                 return ret;
 509
 510         if (st->sts & NVI_DBG_SPEW_MSG) {
 511                 dev_info(&st->i2c->dev, "%s gyro bias_regular: %+d %+d %+d\n",
 512                          __func__, gyr_bias_regular[0], gyr_bias_regular[1],
 513                          gyr_bias_regular[2]);
 514                 dev_info(&st->i2c->dev, "%s gyro bias_st: %+d %+d %+d\n",
 515                          __func__, gyr_bias_st[0], gyr_bias_st[1],
 516                          gyr_bias_st[2]);
 517         }
 518         for (i = 0; i < AXIS_N; i++)
 519                 st->bias[DEV_GYR][i] = (gyr_bias_regular[i] /
 520                                         ICM_ST_PRECISION);
 521         gyro_result = inv_icm_st_gyr_chk(st, gyr_bias_regular, gyr_bias_st);
 522         if (st->sts & NVI_DBG_SPEW_MSG)
 523                 dev_info(&st->i2c->dev, "%s gyro_result %hhd\n",
 524                          __func__, gyro_result);
 525
 526         return gyro_result;
 527 }
 528
 529 static int inv_st_acc_icm(struct nvi_state *st)
 530 {
 531         int ret;
 532         int acc_bias_st[AXIS_N];
 533         int acc_bias_regular[AXIS_N];
 534         int test_times;
 535         int i;
 536         char accel_result;
 537
 538         ret = inv_icm_st_setup(st);
 539         if (ret)
 540                 return ret;
 541
 542         test_times = ICM_ST_TRY_TIMES;
 543         while (test_times > 0) {
 544                 ret = inv_icm_st_acc_do(st, acc_bias_regular, acc_bias_st);
 545                 if (ret == -EAGAIN)
 546                         test_times--;
 547                 else
 548                         break;
 549         }
 550         if (ret)
 551                 return ret;
 552
 553         if (st->sts & NVI_DBG_SPEW_MSG) {
 554                 dev_info(&st->i2c->dev, "%s acc_bias_regular: %+d %+d %+d\n",
 555                          __func__, acc_bias_regular[0],
 556                          acc_bias_regular[1], acc_bias_regular[2]);
 557                 dev_info(&st->i2c->dev, "%s acc_bias_st: %+d %+d %+d\n",
 558                          __func__, acc_bias_st[0], acc_bias_st[1],
 559                          acc_bias_st[2]);
 560         }
 561         for (i = 0; i < AXIS_N; i++)
 562                 st->bias[DEV_ACC][i] = (acc_bias_regular[i] /
 563                                         ICM_ST_PRECISION);
 564         accel_result = inv_icm_st_acc_chk(st, acc_bias_regular, acc_bias_st);
 565         if (st->sts & NVI_DBG_SPEW_MSG)
 566                 dev_info(&st->i2c->dev, "%s accel_result %hhd\n",
 567                          __func__, accel_result);
 568         return accel_result;
 569 }
 570
 571 static int nvi_pm_icm(struct nvi_state *st, u8 pm1, u8 pm2, u8 lp)
 572 {
 573         int ret;
 574
 575         ret = nvi_i2c_wr_rc(st, &st->hal->reg->lp_config, 0x70,
 576                             __func__, &st->rc.lp_config);
 577         /* the DMP changes pm2 so we can't use the cache */
 578         ret |= nvi_i2c_wr(st, &st->hal->reg->pm2, pm2, __func__);
 579         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->pm1, pm1,
 580                              __func__, &st->rc.pm1);
 581         return ret;
 582 }
 583
 584 static int nvi_en_gyr_icm(struct nvi_state *st)
 585 {
 586         u8 val;
 587         int i;
 588         int ret = 0;
 589
 590         st->snsr[DEV_GYR].buf_n = 6;
 591         for (i = 0; i < AXIS_N; i++)
 592                 ret |= nvi_wr_gyro_offset(st, i,
 593                                           (u16)(st->rom_offset[DEV_GYR][i] +
 594                                                 st->dev_offset[DEV_GYR][i]));
 595         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2, 0,
 596                              __func__, &st->rc.gyro_config2);
 597         val = (st->snsr[DEV_GYR].usr_cfg << 1) | 0x01;
 598         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1, val,
 599                              __func__, &st->rc.gyro_config1);
 600         return ret;
 601 }
 602
 603 static int nvi_en_acc_icm(struct nvi_state *st)
 604 {
 605         u8 val;
 606         int i;
 607         int ret = 0;
 608
 609         st->snsr[DEV_ACC].buf_n = 6;
 610         st->snsr[DEV_ACC].buf_shft = 0;
 611         for (i = 0; i < AXIS_N; i++)
 612                 ret |= nvi_wr_accel_offset(st, i,
 613                                            (u16)(st->rom_offset[DEV_ACC][i] +
 614                                           (st->dev_offset[DEV_ACC][i] << 1)));
 615         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2, 0,
 616                              __func__, &st->rc.accel_config2);
 617         val = (st->snsr[DEV_ACC].usr_cfg << 1);
 618         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config, val,
 619                              __func__, &st->rc.accel_config);
 620         return ret;
 621 }
 622
 623 static int nvi_init_icm(struct nvi_state *st)
 624 {
 625         u8 val;
 626         s8 t;
 627         unsigned int src;
 628         int ret;
 629
 630         st->snsr[DEV_ACC].cfg.thresh_hi = 0; /* no ACC LP on ICM */
 631         st->snsr[DEV_SM].cfg.thresh_hi = ICM_SMD_TIMER_THLD_INIT;
 632         ret = nvi_i2c_rd(st, &st->hal->reg->tbc_pll, &val);
 633         if (ret)
 634                 return ret;
 635
 636         t = abs(val & 0x7F);
 637         if (val & 0x80)
 638                 t = -t;
 639         st->src[SRC_GYR].base_t = NSEC_PER_SEC - t * 769903 + ((t * 769903) /
 640                                                                1270) * t;
 641         st->src[SRC_ACC].base_t = NSEC_PER_SEC;
 642         st->src[SRC_AUX].base_t = NSEC_PER_SEC;
 643         for (src = 0; src < st->hal->src_n; src++)
 644                 st->src[src].base_t /= ICM_BASE_SAMPLE_RATE;
 645
 646         nvi_en_gyr_icm(st);
 647         nvi_en_acc_icm(st);
 648         return 0;
 649 }
 650
 651 struct nvi_fn nvi_fn_icm = {
 652         .pm                             = nvi_pm_icm,
 653         .init                           = nvi_init_icm,
 654         .st_acc                         = inv_st_acc_icm,
 655         .st_gyr                         = inv_st_gyr_icm,
 656         .en_acc                         = nvi_en_acc_icm,
 657         .en_gyr                         = nvi_en_gyr_icm,
 658 };
 659
 660
 661 static int nvi_src(struct nvi_state *st, unsigned int src)
 662 {
 663         unsigned int rate;
 664         int ret;
 665
 666         rate = st->src[src].period_us_req / ICM_BASE_SAMPLE_RATE;
 667         if (rate)
 668                 rate--;
 669         ret = nvi_i2c_write_rc(st, &st->hal->reg->smplrt[src], rate,
 670                                __func__, (u8 *)&st->rc.smplrt[src], true);
 671         if (!ret)
 672                 st->src[src].period_us_src = (rate + 1) * ICM_BASE_SAMPLE_RATE;
 673         if (st->sts & (NVS_STS_SPEW_MSG | NVI_DBG_SPEW_MSG))
 674                 dev_info(&st->i2c->dev,
 675                          "%s src[%u] period_req=%u period_src=%u err=%d\n",
 676                          __func__, src, st->src[src].period_us_req,
 677                          st->src[src].period_us_src, ret);
 678         return ret;
 679 }
 680
 681 static int nvi_src_gyr(struct nvi_state *st)
 682 {
 683         return nvi_src(st, SRC_GYR);
 684 }
 685
 686 static int nvi_src_acc(struct nvi_state *st)
 687 {
 688         return nvi_src(st, SRC_ACC);
 689 }
 690
 691 static unsigned int nvi_aux_period_us[] = {
 692         29127111,
 693         14563556,
 694         7281778,
 695         3640889,
 696         1820444,
 697         910222,
 698         455111,
 699         227556,
 700         113778,
 701         56889,
 702         28444,
 703         14222,
 704 };
 705
 706 static int nvi_src_aux(struct nvi_state *st)
 707 {
 708         u8 val;
 709         unsigned int i;
 710         int ret;
 711
 712         for (i = 0; i < ARRAY_SIZE(nvi_aux_period_us); i++) {
 713                 if (st->src[SRC_AUX].period_us_req >= nvi_aux_period_us[i])
 714                         break;
 715         }
 716         if (i >= ARRAY_SIZE(nvi_aux_period_us))
 717                 i = ARRAY_SIZE(nvi_aux_period_us) - 1;
 718         val = 0x0F - i;
 719         ret = nvi_i2c_wr_rc(st, &st->hal->reg->i2c_mst_odr_config, val,
 720                             __func__, &st->rc.i2c_mst_odr_config);
 721         if (!ret) {
 722                 st->src[SRC_AUX].period_us_src = nvi_aux_period_us[i];
 723                 ret = nvi_aux_delay(st, __func__);
 724         }
 725         if (st->sts & (NVS_STS_SPEW_MSG | NVI_DBG_SPEW_MSG))
 726                 dev_info(&st->i2c->dev, "%s src[SRC_AUX]: period=%u err=%d\n",
 727                          __func__, st->src[SRC_AUX].period_us_req, ret);
 728         return ret;
 729 }
 730
 731 static const struct nvi_hal_src src[] = {
 732         [SRC_GYR]                       {
 733                 .dev_msk                = (1 << DEV_GYR) | (1 << DEV_GYU),
 734                 .period_us_min          = 10000,
 735                 .period_us_max          = 256000,
 736                 .fn_period              = nvi_src_gyr,
 737         },
 738         [SRC_ACC]                       {
 739                 .dev_msk                = (1 << DEV_ACC),
 740                 .period_us_min          = 10000,
 741                 .period_us_max          = 256000,
 742                 .fn_period              = nvi_src_acc,
 743         },
 744         [SRC_AUX]                       {
 745                 .dev_msk                = (1 << DEV_AUX),
 746                 .period_us_min          = 14222,
 747                 .period_us_max          = 29127111,
 748                 .fn_period              = nvi_src_aux,
 749         },
 750 };
 751
 752 static int nvi_fifo_devs[] = {
 753         DEV_GYR,
 754         DEV_ACC,
 755         -1,
 756         DEV_AUX,
 757 };
 758
 759 static const unsigned long nvi_lp_dly_us_tbl[] = {
 760         4096000,/* 4096ms */
 761         2048000,/* 2048ms */
 762         1024000,/* 1024ms */
 763         512000, /* 512ms */
 764         256000, /* 256ms */
 765         128000, /* 128ms */
 766         64000,  /* 64ms */
 767         32000,  /* 32ms */
 768         16000,  /* 16ms */
 769         8000,   /* 8ms */
 770         4000,   /* 4ms */
 771         /* 2000, 2ms */
 772 };
 773
 774 static struct nvi_rr nvi_rr_acc[] = {
 775         /* all accelerometer values are in g's  fval = NVS_FLOAT_NANO */
 776         {
 777                 .max_range              = {
 778                         .ival           = 19,
 779                         .fval           = 613300000,
 780                 },
 781                 .resolution             = {
 782                         .ival           = 0,
 783                         .fval           = 598550,
 784                 },
 785         },
 786         {
 787                 .max_range              = {
 788                         .ival           = 39,
 789                         .fval           = 226600000,
 790                 },
 791                 .resolution             = {
 792                         .ival           = 0,
 793                         .fval           = 1197101,
 794                 },
 795         },
 796         {
 797                 .max_range              = {
 798                         .ival           = 78,
 799                         .fval           = 453200000,
 800                 },
 801                 .resolution             = {
 802                         .ival           = 0,
 803                         .fval           = 2394202,
 804                 },
 805         },
 806         {
 807                 .max_range              = {
 808                         .ival           = 156,
 809                         .fval           = 906400000,
 810                 },
 811                 .resolution             = {
 812                         .ival           = 0,
 813                         .fval           = 4788403,
 814                 },
 815         },
 816 };
 817
 818 static struct nvi_rr nvi_rr_gyr[] = {
 819         /* rad / sec  fval = NVS_FLOAT_NANO */
 820         {
 821                 .max_range              = {
 822                         .ival           = 4,
 823                         .fval           = 363323130,
 824                 },
 825                 .resolution             = {
 826                         .ival           = 0,
 827                         .fval           = 133231,
 828                 },
 829         },
 830         {
 831                 .max_range              = {
 832                         .ival           = 8,
 833                         .fval           = 726646260,
 834                 },
 835                 .resolution             = {
 836                         .ival           = 0,
 837                         .fval           = 266462,
 838                 },
 839         },
 840         {
 841                 .max_range              = {
 842                         .ival           = 17,
 843                         .fval           = 453292520,
 844                 },
 845                 .resolution             = {
 846                         .ival           = 0,
 847                         .fval           = 532113,
 848                 },
 849         },
 850         {
 851                 .max_range              = {
 852                         .ival           = 34,
 853                         .fval           = 906585040,
 854                 },
 855                 .resolution             = {
 856                         .ival           = 0,
 857                         .fval           = 1064225,
 858                 },
 859         },
 860 };
 861
 862 static struct nvi_rr nvi_rr_tmp[] = {
 863         {
 864                 .max_range              = {
 865                         .ival           = 125,
 866                         .fval           = 0,
 867                 },
 868                 .resolution             = {
 869                         .ival           = 1,
 870                         .fval           = 0,
 871                 },
 872         },
 873 };
 874
 875 static struct nvi_rr nvi_rr_dmp[] = {
 876         {
 877                 .max_range              = {
 878                         .ival           = 1,
 879                         .fval           = 0,
 880                 },
 881                 .resolution             = {
 882                         .ival           = 1,
 883                         .fval           = 0,
 884                 },
 885         },
 886 };
 887
 888 static const struct nvi_hal_dev nvi_hal_acc = {
 889         .version                        = 3,
 890         .src                            = SRC_ACC,
 891         .rr_0n                          = ARRAY_SIZE(nvi_rr_acc) - 1,
 892         .rr                             = nvi_rr_acc,
 893         .milliamp                       = {
 894                 .ival                   = 0,
 895                 .fval                   = 500000000, /* NVS_FLOAT_NANO */
 896         },
 897         .fifo_en_msk                    = 0x1000,
 898         .fifo                           = 1,
 899         .fifo_data_n                    = 6,
 900 };
 901
 902 static const struct nvi_hal_dev nvi_hal_gyr = {
 903         .version                        = 3,
 904         .src                            = SRC_GYR,
 905         .rr_0n                          = ARRAY_SIZE(nvi_rr_gyr) - 1,
 906         .rr                             = nvi_rr_gyr,
 907         .milliamp                       = {
 908                 .ival                   = 3,
 909                 .fval                   = 700000000, /* NVS_FLOAT_NANO */
 910         },
 911         .fifo_en_msk                    = 0x0E00,
 912         .fifo                           = 0,
 913         .fifo_data_n                    = 6,
 914 };
 915
 916 static const struct nvi_hal_dev nvi_hal_tmp = {
 917         .version                        = 2,
 918         .src                            = -1,
 919         .rr_0n                          = ARRAY_SIZE(nvi_rr_tmp) - 1,
 920         .rr                             = nvi_rr_tmp,
 921         .scale                          = {
 922                 .ival                   = 0,
 923                 .fval                   = 334082700, /* NVS_FLOAT_NANO */
 924         },
 925         .offset                         = {
 926                 .ival                   = 0,
 927                 .fval                   = 137625600, /* NVS_FLOAT_NANO */
 928         },
 929         .milliamp                       = {
 930                 .ival                   = 3,
 931                 .fval                   = 700000000, /* NVS_FLOAT_NANO */
 932         },
 933 };
 934
 935 static const struct nvi_hal_dev nvi_hal_aux = {
 936         .src                            = SRC_AUX,
 937         .fifo_en_msk                    = 0x000F,
 938 };
 939
 940 static const struct nvi_hal_dev nvi_hal_dmp = {
 941         .version                        = 1,
 942         .src                            = SRC_GYR,
 943         .rr_0n                          = ARRAY_SIZE(nvi_rr_dmp) - 1,
 944         .rr                             = nvi_rr_dmp,
 945         .milliamp                       = {
 946                 .ival                   = 0,
 947                 .fval                   = 500000, /* NVS_FLOAT_MICRO */
 948         },
 949 };
 950
 951
 952 static const struct nvi_hal_reg nvi_hal_reg_icm = {
 953 /* register bank 0 */
 954         .lp_config                      = {
 955                 .bank                   = 0,
 956                 .reg                    = 0x05,
 957                 .dflt                   = 0x70,
 958         },
 959         .i2c_mst_status                 = {
 960                 .bank                   = 0,
 961                 .reg                    = 0x17,
 962         },
 963         .int_pin_cfg                    = {
 964                 .bank                   = 0,
 965                 .reg                    = 0x0F,
 966         },
 967         .int_enable                     = {
 968                 .bank                   = 0,
 969                 .reg                    = 0x10,
 970                 .len                    = 4,
 971         },
 972         .int_dmp                        = {
 973                 .bank                   = 0,
 974                 .reg                    = 0x18,
 975         },
 976         .int_status                     = {
 977                 .bank                   = 0,
 978                 .reg                    = 0x19,
 979                 .len                    = 4,
 980         },
 981         .out_h[DEV_ACC]         = {
 982                 .bank                   = 0,
 983                 .reg                    = 0x2D,
 984         },
 985         .out_h[DEV_GYR]         = {
 986                 .bank                   = 0,
 987                 .reg                    = 0x33,
 988         },
 989         .out_h[DEV_TMP]         = {
 990                 .bank                   = 0,
 991                 .reg                    = 0x39,
 992         },
 993         .ext_sens_data_00               = {
 994                 .bank                   = 0,
 995                 .reg                    = 0x3B,
 996         },
 997         .signal_path_reset              = {
 998                 .bank                   = 0,
 999                 .reg                    = 0x04,
1000         },
1001         .user_ctrl                      = {
1002                 .bank                   = 0,
1003                 .reg                    = 0x03,
1004         },
1005         .pm1                            = {
1006                 .bank                   = 0,
1007                 .reg                    = 0x06,
1008                 .dflt                   = 0x01,
1009         },
1010         .pm2                            = {
1011                 .bank                   = 0,
1012                 .reg                    = 0x07,
1013                 .dflt                   = 0x40,
1014         },
1015         .fifo_en                        = {
1016                 .bank                   = 0,
1017                 .reg                    = 0x66,
1018                 .len                    = 2,
1019         },
1020         .fifo_rst                       = {
1021                 .bank                   = 0,
1022                 .reg                    = 0x68,
1023         },
1024         .fifo_sz                        = {
1025                 .bank                   = 0,
1026                 .reg                    = 0x6E,
1027         },
1028         .fifo_count_h                   = {
1029                 .bank                   = 0,
1030                 .reg                    = 0x70,
1031                 .len                    = 2,
1032         },
1033         .fifo_rw                        = {
1034                 .bank                   = 0,
1035                 .reg                    = 0x72,
1036         },
1037         .fifo_cfg                       = {
1038                 .bank                   = 0,
1039                 .reg                    = 0x76,
1040         },
1041         .who_am_i                       = {
1042                 .bank                   = 0,
1043                 .reg                    = 0x00,
1044         },
1045         .mem_addr                       = {
1046                 .bank                   = 0,
1047                 .reg                    = 0x7C,
1048         },
1049         .mem_rw                         = {
1050                 .bank                   = 0,
1051                 .reg                    = 0x7D,
1052         },
1053         .mem_bank                       = {
1054                 .bank                   = 0,
1055                 .reg                    = 0x7E,
1056         },
1057         .reg_bank                       = {
1058                 .bank                   = 0,
1059                 .reg                    = 0x7F,
1060         },
1061 /* register bank 1 */
1062         .self_test_g[AXIS_X]            = {
1063                 .bank                   = 1,
1064                 .reg                    = 0x02,
1065         },
1066         .self_test_g[AXIS_Y]            = {
1067                 .bank                   = 1,
1068                 .reg                    = 0x03,
1069         },
1070         .self_test_g[AXIS_Z]            = {
1071                 .bank                   = 1,
1072                 .reg                    = 0x04,
1073         },
1074         .self_test_a[AXIS_X]    = {
1075                 .bank                   = 1,
1076                 .reg                    = 0x0E,
1077         },
1078         .self_test_a[AXIS_Y]    = {
1079                 .bank                   = 1,
1080                 .reg                    = 0x0F,
1081         },
1082         .self_test_a[AXIS_Z]    = {
1083                 .bank                   = 1,
1084                 .reg                    = 0x10,
1085         },
1086         .a_offset_h[AXIS_X]             = {
1087                 .bank                   = 1,
1088                 .reg                    = 0x14,
1089                 .len                    = 2,
1090         },
1091         .a_offset_h[AXIS_Y]             = {
1092                 .bank                   = 1,
1093                 .reg                    = 0x17,
1094                 .len                    = 2,
1095         },
1096         .a_offset_h[AXIS_Z]             = {
1097                 .bank                   = 1,
1098                 .reg                    = 0x1A,
1099                 .len                    = 2,
1100         },
1101         .tbc_pll                        = {
1102                 .bank                   = 1,
1103                 .reg                    = 0x28,
1104         },
1105         .tbc_rcosc                      = {
1106                 .bank                   = 1,
1107                 .reg                    = 0x29,
1108         },
1109 /* register bank 2 */
1110         .smplrt[SRC_GYR]                = {
1111                 .bank                   = 2,
1112                 .reg                    = 0x00,
1113         },
1114         .gyro_config1                   = {
1115                 .bank                   = 2,
1116                 .reg                    = 0x01,
1117                 .dflt                   = 0x01,
1118         },
1119         .gyro_config2                   = {
1120                 .bank                   = 2,
1121                 .reg                    = 0x02,
1122         },
1123         .g_offset_h[AXIS_X]             = {
1124                 .bank                   = 2,
1125                 .reg                    = 0x03,
1126                 .len                    = 2,
1127         },
1128         .g_offset_h[AXIS_Y]             = {
1129                 .bank                   = 2,
1130                 .reg                    = 0x05,
1131                 .len                    = 2,
1132         },
1133         .g_offset_h[AXIS_Z]             = {
1134                 .bank                   = 2,
1135                 .reg                    = 0x07,
1136                 .len                    = 2,
1137         },
1138         .smplrt[SRC_ACC]                = {
1139                 .bank                   = 2,
1140                 .reg                    = 0x10,
1141                 .len                    = 2,
1142         },
1143         .accel_config                   = {
1144                 .bank                   = 2,
1145                 .reg                    = 0x14,
1146         },
1147         .accel_config2                  = {
1148                 .bank                   = 2,
1149                 .reg                    = 0x15,
1150         },
1151         .fw_start                       = {
1152                 .bank                   = 2,
1153                 .reg                    = 0x50,
1154                 .len                    = 2,
1155         },
1156 /* register bank 3 */
1157         .i2c_mst_odr_config             = {
1158                 .bank                   = 3,
1159                 .reg                    = 0x00,
1160         },
1161         .i2c_mst_ctrl                   = {
1162                 .bank                   = 3,
1163                 .reg                    = 0x01,
1164         },
1165         .i2c_mst_delay_ctrl             = {
1166                 .bank                   = 3,
1167                 .reg                    = 0x02,
1168         },
1169         .i2c_slv_addr[0]                = {
1170                 .bank                   = 3,
1171                 .reg                    = 0x03,
1172         },
1173         .i2c_slv_addr[1]                = {
1174                 .bank                   = 3,
1175                 .reg                    = 0x07,
1176         },
1177         .i2c_slv_addr[2]                = {
1178                 .bank                   = 3,
1179                 .reg                    = 0x0B,
1180         },
1181         .i2c_slv_addr[3]                = {
1182                 .bank                   = 3,
1183                 .reg                    = 0x0F,
1184         },
1185         .i2c_slv_addr[4]                = {
1186                 .bank                   = 3,
1187                 .reg                    = 0x13,
1188         },
1189         .i2c_slv_reg[0]                 = {
1190                 .bank                   = 3,
1191                 .reg                    = 0x04,
1192         },
1193         .i2c_slv_reg[1]                 = {
1194                 .bank                   = 3,
1195                 .reg                    = 0x08,
1196         },
1197         .i2c_slv_reg[2]                 = {
1198                 .bank                   = 3,
1199                 .reg                    = 0x0C,
1200         },
1201         .i2c_slv_reg[3]                 = {
1202                 .bank                   = 3,
1203                 .reg                    = 0x10,
1204         },
1205         .i2c_slv_reg[4]                 = {
1206                 .bank                   = 3,
1207                 .reg                    = 0x14,
1208         },
1209         .i2c_slv_ctrl[0]                = {
1210                 .bank                   = 3,
1211                 .reg                    = 0x05,
1212         },
1213         .i2c_slv_ctrl[1]                = {
1214                 .bank                   = 3,
1215                 .reg                    = 0x09,
1216         },
1217         .i2c_slv_ctrl[2]                = {
1218                 .bank                   = 3,
1219                 .reg                    = 0x0D,
1220         },
1221         .i2c_slv_ctrl[3]                = {
1222                 .bank                   = 3,
1223                 .reg                    = 0x11,
1224         },
1225         .i2c_slv4_ctrl                  = {
1226                 .bank                   = 3,
1227                 .reg                    = 0x15,
1228         },
1229         .i2c_slv_do[0]                  = {
1230                 .bank                   = 3,
1231                 .reg                    = 0x06,
1232         },
1233         .i2c_slv_do[1]                  = {
1234                 .bank                   = 3,
1235                 .reg                    = 0x0A,
1236         },
1237         .i2c_slv_do[2]                  = {
1238                 .bank                   = 3,
1239                 .reg                    = 0x0E,
1240         },
1241         .i2c_slv_do[3]                  = {
1242                 .bank                   = 3,
1243                 .reg                    = 0x12,
1244         },
1245         .i2c_slv_do[4]                  = {
1246                 .bank                   = 3,
1247                 .reg                    = 0x16,
1248         },
1249         .i2c_slv4_di                    = {
1250                 .bank                   = 3,
1251                 .reg                    = 0x17,
1252         },
1253 };
1254
1255 static const struct nvi_hal_bit nvi_hal_bit_icm = {
1256         .dmp_int_sm                     = 2,
1257         .dmp_int_stp                    = 3,
1258         .int_i2c_mst                    = 0,
1259         .int_dmp                        = 1,
1260         .int_pll_rdy                    = 2,
1261         .int_wom                        = 3,
1262         .int_wof                        = 7,
1263         .int_data_rdy_0                 = 8,
1264         .int_data_rdy_1                 = 9,
1265         .int_data_rdy_2                 = 10,
1266         .int_data_rdy_3                 = 11,
1267         .int_fifo_ovrflw_0              = 16,
1268         .int_fifo_ovrflw_1              = 17,
1269         .int_fifo_ovrflw_2              = 18,
1270         .int_fifo_ovrflw_3              = 19,
1271         .int_fifo_wm_0                  = 24,
1272         .int_fifo_wm_1                  = 25,
1273         .int_fifo_wm_2                  = 26,
1274         .int_fifo_wm_3                  = 27,
1275         .slv_fifo_en[0]                 = 0,
1276         .slv_fifo_en[1]                 = 1,
1277         .slv_fifo_en[2]                 = 2,
1278         .slv_fifo_en[3]                 = 3,
1279 };
1280
1281 const struct nvi_hal nvi_hal_20628 = {
1282         .regs_n                         = 128,
1283         .reg_bank_n                     = 4,
1284         .src                            = src,
1285         .src_n                          = ARRAY_SIZE(src),
1286         .fifo_dev                       = nvi_fifo_devs,
1287         .fifo_n                         = ARRAY_SIZE(nvi_fifo_devs),
1288         .lp_tbl                         = nvi_lp_dly_us_tbl,
1289         .lp_tbl_n                       = ARRAY_SIZE(nvi_lp_dly_us_tbl),
1290         .dev[DEV_ACC]                   = &nvi_hal_acc,
1291         .dev[DEV_GYR]                   = &nvi_hal_gyr,
1292         .dev[DEV_TMP]                   = &nvi_hal_tmp,
1293         .dev[DEV_SM]                    = &nvi_hal_dmp,
1294         .dev[DEV_STP]                   = &nvi_hal_dmp,
1295         .dev[DEV_QTN]                   = &nvi_hal_dmp,
1296         .dev[DEV_GMR]                   = &nvi_hal_dmp,
1297         .dev[DEV_GYU]                   = &nvi_hal_gyr,
1298         .dev[DEV_AUX]                   = &nvi_hal_aux,
1299         .reg                            = &nvi_hal_reg_icm,
1300         .bit                            = &nvi_hal_bit_icm,
1301         .fn                             = &nvi_fn_icm,
1302         .dmp                            = &nvi_dmp_icm,
1303 };
1304 EXPORT_SYMBOL(nvi_hal_20628);
1305