2 * drivers/usb/phy/tegra11x_usb_phy.c
4 * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/clk/tegra.h>
30 #include <linux/tegra-soc.h>
31 #include <linux/tegra-fuse.h>
32 #include <mach/pinmux.h>
33 #include <mach/tegra_usb_pmc.h>
34 #include <mach/tegra_usb_pad_ctrl.h>
36 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
37 #include <mach/pinmux-t14.h>
39 #include <mach/pinmux-t11.h>
41 #include "tegra_usb_phy.h"
42 #include "../../../arch/arm/mach-tegra/gpio-names.h"
44 /* HACK! This needs to come from DT */
45 #include "../../../arch/arm/mach-tegra/iomap.h"
47 #define USB_USBCMD 0x130
48 #define USB_USBCMD_RS (1 << 0)
49 #define USB_CMD_RESET (1<<1)
51 #define USB_USBSTS 0x134
52 #define USB_USBSTS_PCI (1 << 2)
53 #define USB_USBSTS_SRI (1 << 7)
54 #define USB_USBSTS_HCH (1 << 12)
56 #define USB_TXFILLTUNING 0x154
57 #define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
58 #define USB_FIFO_TXFILL_MASK 0x1f0000
60 #define USB_ASYNCLISTADDR 0x148
62 #define ICUSB_CTRL 0x15c
64 #define USB_USBMODE 0x1f8
65 #define USB_USBMODE_MASK (3 << 0)
66 #define USB_USBMODE_HOST (3 << 0)
67 #define USB_USBMODE_DEVICE (2 << 0)
69 #define USB_SUSP_CTRL 0x400
70 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
71 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
72 #define USB_SUSP_CLR (1 << 5)
73 #define USB_CLKEN (1 << 6)
74 #define USB_PHY_CLK_VALID (1 << 7)
75 #define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
76 #define USB_PHY_CLK_VALID_INT_STS (1 << 8)
77 #define UTMIP_RESET (1 << 11)
78 #define UTMIP_PHY_ENABLE (1 << 12)
79 #define UHSIC_RESET (1 << 14)
80 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
81 #define UHSIC_PHY_ENABLE (1 << 19)
83 #define USB_PHY_VBUS_WAKEUP_ID 0x408
84 #define DIV_DET_EN (1 << 31)
85 #define VDCD_DET_STS (1 << 26)
86 #define VDCD_DET_CHG_DET (1 << 25)
87 #define VOP_DIV2P7_DET (1 << 23)
88 #define VOP_DIV2P0_DET (1 << 22)
89 #define VON_DIV2P7_DET (1 << 15)
90 #define VON_DIV2P0_DET (1 << 14)
91 #define VDAT_DET_INT_EN (1 << 16)
92 #define VDAT_DET_CHG_DET (1 << 17)
93 #define VDAT_DET_STS (1 << 18)
94 #define USB_ID_STATUS (1 << 2)
96 #define USB_IF_SPARE 0x498
97 #define USB_HS_RSM_EOP_EN (1 << 4)
98 #define USB_PORT_SUSPEND_EN (1 << 5)
100 #define USB_NEW_CONTROL 0x4c0
101 #define USB_COHRENCY_EN (1 << 0)
102 #define USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
104 #define UTMIP_XCVR_CFG0 0x808
105 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
106 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
107 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
108 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
109 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
110 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
111 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
112 #define UTMIP_XCVR_SETUP_MSB(x) (((x) & 0x7) << 22)
113 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
114 #define UTMIP_XCVR_HSSLEW_LSB(x) (((x) & 0x3) << 4)
115 #define UTMIP_XCVR_MAX_OFFSET 2
116 #define UTMIP_XCVR_SETUP_MAX_VALUE 0x7f
117 #define UTMIP_XCVR_SETUP_MIN_VALUE 0
118 #define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
120 #define UTMIP_HSRX_CFG0 0x810
121 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
122 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
124 #define UTMIP_HSRX_CFG1 0x814
125 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
127 #define UTMIP_TX_CFG0 0x820
128 #define UTMIP_FS_PREABMLE_J (1 << 19)
129 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
131 #define UTMIP_DEBOUNCE_CFG0 0x82c
132 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
134 #define UTMIP_BAT_CHRG_CFG0 0x830
135 #define UTMIP_PD_CHRG (1 << 0)
136 #define UTMIP_OP_SINK_EN (1 << 1)
137 #define UTMIP_ON_SINK_EN (1 << 2)
138 #define UTMIP_OP_SRC_EN (1 << 3)
139 #define UTMIP_ON_SRC_EN (1 << 4)
140 #define UTMIP_OP_I_SRC_EN (1 << 5)
142 #define UTMIP_XCVR_CFG1 0x838
143 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
144 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
145 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
146 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
148 #define UTMIP_MISC_CFG0 0x824
149 #define UTMIP_DPDM_OBSERVE (1 << 26)
150 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
151 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
152 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
153 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
154 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
155 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
156 #define DISABLE_PULLUP_DP (1 << 15)
157 #define DISABLE_PULLUP_DM (1 << 14)
158 #define DISABLE_PULLDN_DP (1 << 13)
159 #define DISABLE_PULLDN_DM (1 << 12)
160 #define FORCE_PULLUP_DP (1 << 11)
161 #define FORCE_PULLUP_DM (1 << 10)
162 #define FORCE_PULLDN_DP (1 << 9)
163 #define FORCE_PULLDN_DM (1 << 8)
164 #define COMB_TERMS (1 << 0)
165 #define ALWAYS_FREE_RUNNING_TERMS (1 << 1)
166 #define MASK_ALL_PULLUP_PULLDOWN (0xff << 8)
168 #define UTMIP_SPARE_CFG0 0x834
169 #define FUSE_SETUP_SEL (1 << 3)
170 #define FUSE_ATERM_SEL (1 << 4)
172 #define UHSIC_PLL_CFG1 0xc04
173 #define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
174 #define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
176 #define UHSIC_HSRX_CFG0 0xc08
177 #define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
178 #define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
179 #define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
181 #define UHSIC_HSRX_CFG1 0xc0c
182 #define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
184 #define UHSIC_TX_CFG0 0xc10
185 #define UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9)
186 #define UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 6)
189 #define UHSIC_MISC_CFG0 0xc14
190 #define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7)
191 #define UHSIC_DETECT_SHORT_CONNECT (1 << 8)
192 #define UHSIC_FORCE_XCVR_MODE (1 << 15)
193 #define UHSIC_DISABLE_BUSRESET (1 << 20)
195 #define UHSIC_MISC_CFG1 0xc18
196 #define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
198 #define UHSIC_PADS_CFG0 0xc1c
199 #define UHSIC_TX_RTUNEN 0xf000
200 #define UHSIC_TX_RTUNEP 0xf00
201 #define UHSIC_TX_RTUNE_P(x) (((x) & 0xf) << 8)
202 #define UHSIC_TX_SLEWP (0xf << 16)
203 #define UHSIC_TX_SLEWN (0xf << 20)
205 #define UHSIC_PADS_CFG1 0xc20
206 #define UHSIC_AUTO_RTERM_EN (1 << 0)
207 #define UHSIC_PD_BG (1 << 2)
208 #define UHSIC_PD_TX (1 << 3)
209 #define UHSIC_PD_TRK (1 << 4)
210 #define UHSIC_PD_RX (1 << 5)
211 #define UHSIC_PD_ZI (1 << 6)
212 #define UHSIC_RX_SEL (1 << 7)
213 #define UHSIC_RPD_DATA (1 << 9)
214 #define UHSIC_RPD_STROBE (1 << 10)
215 #define UHSIC_RPU_DATA (1 << 11)
216 #define UHSIC_RPU_STROBE (1 << 12)
218 #define UHSIC_SPARE_CFG0 0xc2c
219 #define FORCE_BK_ON (1 << 12)
221 #define UHSIC_STAT_CFG0 0xc28
222 #define UHSIC_CONNECT_DETECT (1 << 0)
224 #define UHSIC_STATUS(inst) UHSIC_INST(inst, 0x214, 0x290)
225 #define UHSIC_WAKE_ALARM(inst) (1 << UHSIC_INST(inst, 19, 4))
226 #define UHSIC_WALK_PTR_VAL(inst) (0x3 << UHSIC_INST(inst, 6, 0))
227 #define UHSIC_DATA_VAL(inst) (1 << UHSIC_INST(inst, 15, 3))
228 #define UHSIC_STROBE_VAL(inst) (1 << UHSIC_INST(inst, 14, 2))
230 #define UHSIC_CMD_CFG0 0xc24
231 #define UHSIC_PRETEND_CONNECT_DETECT (1 << 5)
233 #define USB_USBINTR 0x138
235 #define UTMIP_STATUS 0x214
236 #define UTMIP_WALK_PTR_VAL(inst) (0x3 << ((inst)*2))
237 #define UTMIP_USBOP_VAL(inst) (1 << ((2*(inst)) + 8))
238 #define UTMIP_USBOP_VAL_P2 (1 << 12)
239 #define UTMIP_USBOP_VAL_P1 (1 << 10)
240 #define UTMIP_USBOP_VAL_P0 (1 << 8)
241 #define UTMIP_USBON_VAL(inst) (1 << ((2*(inst)) + 9))
242 #define UTMIP_USBON_VAL_P2 (1 << 13)
243 #define UTMIP_USBON_VAL_P1 (1 << 11)
244 #define UTMIP_USBON_VAL_P0 (1 << 9)
245 #define UTMIP_WAKE_ALARM(inst) (1 << ((inst) + 16))
246 #define UTMIP_WAKE_ALARM_P2 (1 << 18)
247 #define UTMIP_WAKE_ALARM_P1 (1 << 17)
248 #define UTMIP_WAKE_ALARM_P0 (1 << 16)
249 #define UTMIP_WALK_PTR(inst) (1 << ((inst)*2))
250 #define UTMIP_WALK_PTR_P2 (1 << 4)
251 #define UTMIP_WALK_PTR_P1 (1 << 2)
252 #define UTMIP_WALK_PTR_P0 (1 << 0)
254 #define USB1_PREFETCH_ID 6
255 #define USB2_PREFETCH_ID 18
256 #define USB3_PREFETCH_ID 17
258 #define FUSE_USB_CALIB_0 0x1F0
259 #define XCVR_SETUP(x) (((x) & 0x7F) << 0)
260 #define XCVR_SETUP_LSB_MASK 0xF
261 #define XCVR_SETUP_MSB_MASK 0x70
262 #define XCVR_SETUP_LSB_MAX_VAL 0xF
264 #define APB_MISC_GP_OBSCTRL_0 0x818
265 #define APB_MISC_GP_OBSDATA_0 0x81c
267 #define PADCTL_SNPS_OC_MAP 0xC
268 #define CONTROLLER_OC(inst, x) (((x) & 0x7) << (3 * (inst)))
269 #define CONTROLLER_OC_P0(x) (((x) & 0x7) << 0)
270 #define CONTROLLER_OC_P1(x) (((x) & 0x7) << 3)
271 #define CONTROLLER_OC_P2(x) (((x) & 0x7) << 6)
273 #define PADCTL_OC_DET 0x18
274 #define ENABLE0_OC_MAP(x) (((x) & 0x7) << 10)
275 #define ENABLE1_OC_MAP(x) (((x) & 0x7) << 13)
277 #define TEGRA_STREAM_DISABLE 0x1f8
278 #define TEGRA_STREAM_DISABLE_OFFSET (1 << 4)
280 /* These values (in milli second) are taken from the battery charging spec */
281 #define TDP_SRC_ON_MS 100
282 #define TDPSRC_CON_MS 40
284 /* Maxim Debounce Timer */
285 #define MAXIM_DEBOUNCE_TIME 120
287 /* Force port resume wait time in micro second on remote resume */
288 #define FPR_WAIT_TIME_US 25000
290 /* define HSIC phy params */
291 #define HSIC_SYNC_START_DELAY 9
292 #define HSIC_IDLE_WAIT_DELAY 17
293 #define HSIC_ELASTIC_UNDERRUN_LIMIT 16
294 #define HSIC_ELASTIC_OVERRUN_LIMIT 16
296 struct tegra_usb_pmc_data pmc_data[3];
298 static struct tegra_xtal_freq utmip_freq_table[] = {
301 .enable_delay = 0x02,
302 .stable_count = 0x2F,
303 .active_delay = 0x04,
304 .xtal_freq_count = 0x76,
310 .enable_delay = 0x02,
311 .stable_count = 0x33,
312 .active_delay = 0x05,
313 .xtal_freq_count = 0x7F,
319 .enable_delay = 0x03,
320 .stable_count = 0x4B,
321 .active_delay = 0x06,
322 .xtal_freq_count = 0xBB,
328 .enable_delay = 0x04,
329 .stable_count = 0x66,
330 .active_delay = 0x09,
331 .xtal_freq_count = 0xFE,
337 static struct tegra_xtal_freq uhsic_freq_table[] = {
340 .enable_delay = 0x02,
341 .stable_count = 0x2F,
343 .xtal_freq_count = 0x1CA,
347 .enable_delay = 0x02,
348 .stable_count = 0x33,
350 .xtal_freq_count = 0x1F0,
354 .enable_delay = 0x03,
355 .stable_count = 0x4B,
357 .xtal_freq_count = 0x2DD,
361 .enable_delay = 0x04,
362 .stable_count = 0x66,
364 .xtal_freq_count = 0x3E0,
368 static void pmc_init(struct tegra_usb_phy *phy)
370 pmc_data[phy->inst].instance = phy->inst;
371 pmc_data[phy->inst].phy_type = phy->pdata->phy_intf;
372 pmc_data[phy->inst].controller_type = TEGRA_USB_2_0;
373 pmc_data[phy->inst].usb_base = phy->regs;
374 tegra_usb_pmc_init(&pmc_data[phy->inst]);
377 static int _usb_phy_init(struct tegra_usb_phy *phy)
380 void __iomem *base = phy->regs;
382 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
384 val = readl(base + HOSTPC1_DEVLC);
385 val &= ~HOSTPC1_DEVLC_STS;
386 writel(val, base + HOSTPC1_DEVLC);
388 val = readl(base + USB_IF_SPARE);
389 val |= USB_HS_RSM_EOP_EN;
390 val |= USB_PORT_SUSPEND_EN;
391 writel(val, base + USB_IF_SPARE);
393 if (phy->pdata->unaligned_dma_buf_supported == true) {
394 val = readl(base + USB_NEW_CONTROL);
395 val |= USB_COHRENCY_EN;
396 val |= USB_MEM_ALLIGNMENT_MUX_EN;
397 writel(val, base + USB_NEW_CONTROL);
399 val = readl(base + TEGRA_STREAM_DISABLE);
400 if (!tegra_platform_is_silicon())
401 val |= TEGRA_STREAM_DISABLE_OFFSET;
403 val &= ~TEGRA_STREAM_DISABLE_OFFSET;
404 writel(val , base + TEGRA_STREAM_DISABLE);
409 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
411 /* Fence read for coherency of AHB master intiated writes */
413 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
414 else if (phy->inst == 1)
415 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
416 else if (phy->inst == 2)
417 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
421 static int usb_phy_reset(struct tegra_usb_phy *phy)
424 void __iomem *base = phy->regs;
426 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
428 if (!tegra_platform_is_silicon()) {
429 val = readl(base + TEGRA_STREAM_DISABLE);
430 val |= TEGRA_STREAM_DISABLE_OFFSET;
431 writel(val , base + TEGRA_STREAM_DISABLE);
433 val = readl(base + USB_TXFILLTUNING);
434 if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
435 val = USB_FIFO_TXFILL_THRES(0x10);
436 writel(val, base + USB_TXFILLTUNING);
442 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
444 void __iomem *base = phy->regs;
445 unsigned int inst = phy->inst;
448 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
449 val = readl(base + UTMIP_PMC_WAKEUP0);
450 if (val & EVENT_INT_ENB) {
451 val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
452 if (UTMIP_WAKE_ALARM(inst) & val) {
453 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG,
454 UTMIP_WAKE_VAL(inst, 0xF),
455 UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE));
457 tegra_usb_pmc_reg_update(PMC_TRIGGERS, 0,
458 UTMIP_CLR_WAKE_ALARM(inst));
460 val = readl(base + UTMIP_PMC_WAKEUP0);
461 val &= ~EVENT_INT_ENB;
462 writel(val, base + UTMIP_PMC_WAKEUP0);
464 val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
465 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN)
466 phy->pmc_remote_wakeup = true;
468 phy->pmc_hotplug_wakeup = true;
470 DBG("%s: utmip PMC interrupt detected\n", __func__);
477 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
480 void __iomem *base = phy->regs;
482 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
483 PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
484 __LINE__, readl(base + USB_USBSTS), readl(base + USB_PORTSC),
487 /* Device is plugged in when system is in LP0 */
488 /* Bring up the controller from LP0*/
489 val = readl(base + USB_USBCMD);
490 val |= USB_CMD_RESET;
491 writel(val, base + USB_USBCMD);
493 if (usb_phy_reg_status_wait(base + USB_USBCMD,
494 USB_CMD_RESET, 0, 2500) < 0) {
495 pr_err("%s: timeout waiting for reset\n", __func__);
498 val = readl(base + USB_USBMODE);
499 val &= ~USB_USBMODE_MASK;
500 val |= USB_USBMODE_HOST;
501 writel(val, base + USB_USBMODE);
502 val = readl(base + HOSTPC1_DEVLC);
503 val &= ~HOSTPC1_DEVLC_PTS(~0);
505 if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
506 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
508 val |= HOSTPC1_DEVLC_STS;
509 writel(val, base + HOSTPC1_DEVLC);
511 /* Enable Port Power */
512 val = readl(base + USB_PORTSC);
513 val |= USB_PORTSC_PP;
514 writel(val, base + USB_PORTSC);
517 /* Check if the phy resume from LP0. When the phy resume from LP0
518 * USB register will be reset.to zero */
519 if (!readl(base + USB_ASYNCLISTADDR)) {
520 /* Program the field PTC based on the saved speed mode */
521 val = readl(base + USB_PORTSC);
522 val &= ~USB_PORTSC_PTC(~0);
523 if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) ||
524 (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC))
525 val |= USB_PORTSC_PTC(5);
526 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
527 val |= USB_PORTSC_PTC(6);
528 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
529 val |= USB_PORTSC_PTC(7);
530 writel(val, base + USB_PORTSC);
533 /* Disable test mode by setting PTC field to NORMAL_OP */
534 val = readl(base + USB_PORTSC);
535 val &= ~USB_PORTSC_PTC(~0);
536 writel(val, base + USB_PORTSC);
540 /* Poll until CCS is enabled */
541 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
542 USB_PORTSC_CCS, 2000)) {
543 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
546 /* Poll until PE is enabled */
547 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
548 USB_PORTSC_PE, 2000)) {
549 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
552 /* Clear the PCI status, to avoid an interrupt taken upon resume */
553 val = readl(base + USB_USBSTS);
554 val |= USB_USBSTS_PCI;
555 writel(val, base + USB_USBSTS);
557 phy->ctrlr_suspended = false;
558 if (!phy->pmc_remote_wakeup) {
559 /* Put controller in suspend mode by writing 1
560 * to SUSP bit of PORTSC */
561 val = readl(base + USB_PORTSC);
562 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
563 val |= USB_PORTSC_SUSP;
564 writel(val, base + USB_PORTSC);
565 phy->ctrlr_suspended = true;
566 /* Wait until port suspend completes */
567 if (usb_phy_reg_status_wait(base + USB_PORTSC,
568 USB_PORTSC_SUSP, USB_PORTSC_SUSP, 4000)) {
569 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
574 PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
575 __LINE__, readl(base + USB_USBSTS), readl(base + USB_PORTSC),
578 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
579 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
583 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
585 struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
588 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
590 if (cfg->xcvr_use_fuses) {
591 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
592 if (cfg->xcvr_use_lsb) {
593 val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
594 + cfg->xcvr_setup_offset),
595 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
596 val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
598 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
599 val = val + cfg->xcvr_setup_offset;
601 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
602 val = UTMIP_XCVR_SETUP_MAX_VALUE;
603 pr_info("%s: reset XCVR_SETUP to max value\n",
605 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
606 val = UTMIP_XCVR_SETUP_MIN_VALUE;
607 pr_info("%s: reset XCVR_SETUP to min value\n",
612 val = cfg->xcvr_setup;
615 return (unsigned int) val;
618 static int utmi_phy_open(struct tegra_usb_phy *phy)
620 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
622 unsigned long parent_rate;
625 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
627 phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
628 if (IS_ERR(phy->utmi_pad_clk)) {
629 pr_err("%s: can't get utmip pad clock\n", __func__);
630 return PTR_ERR(phy->utmi_pad_clk);
634 phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
636 if (tegra_platform_is_silicon()) {
637 parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
638 for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
639 if (utmip_freq_table[i].freq == parent_rate) {
640 phy->freq = &utmip_freq_table[i];
645 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
650 /* Power-up the VBUS, ID detector for UTMIP PHY */
651 if (phy->pdata->id_det_type == TEGRA_USB_ID)
652 tegra_usb_pmc_reg_update(PMC_USB_AO,
653 PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0, 0);
655 tegra_usb_pmc_reg_update(PMC_USB_AO,
656 PMC_USB_AO_VBUS_WAKEUP_PD_P0, PMC_USB_AO_ID_PD_P0);
658 pmc->pmc_ops->powerup_pmc_wake_detect(pmc);
663 static void utmi_phy_close(struct tegra_usb_phy *phy)
666 void __iomem *base = phy->regs;
667 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
669 DBG("%s inst:[%d]\n", __func__, phy->inst);
671 /* Disable PHY clock valid interrupts while going into suspend*/
673 val = readl(base + USB_SUSP_CTRL);
674 val &= ~USB_PHY_CLK_VALID_INT_ENB;
675 writel(val, base + USB_SUSP_CTRL);
678 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
679 if (val & UTMIP_MASTER_ENABLE(phy->inst)) {
680 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
682 phy->pmc_remote_wakeup = false;
683 phy->pmc_hotplug_wakeup = false;
684 PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, phy->inst);
687 clk_put(phy->utmi_pad_clk);
690 static int utmi_phy_irq(struct tegra_usb_phy *phy)
692 void __iomem *base = phy->regs;
693 unsigned long val = 0;
694 bool remote_wakeup = false;
695 int irq_status = IRQ_HANDLED;
697 if (phy->phy_clk_on) {
698 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
699 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
700 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
701 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
702 readl(base + USB_USBMODE), readl(base + USB_USBCMD));
704 if (!phy->pdata->unaligned_dma_buf_supported)
705 usb_phy_fence_read(phy);
706 /* check if it is pmc wake event */
707 if (utmi_phy_remotewake_detected(phy))
708 remote_wakeup = phy->pmc_remote_wakeup;
711 val = readl(base + USB_SUSP_CTRL);
712 if ((val & USB_PHY_CLK_VALID_INT_STS) &&
713 (val & USB_PHY_CLK_VALID_INT_ENB)) {
714 val &= ~USB_PHY_CLK_VALID_INT_ENB |
715 USB_PHY_CLK_VALID_INT_STS;
716 writel(val , (base + USB_SUSP_CTRL));
718 /* In case of remote wakeup PHY clock will not up
719 * immediately, so should not access any controller
720 * register but normal plug-in/plug-out should be
723 if (!remote_wakeup) {
724 val = readl(base + USB_USBSTS);
725 if (!(val & USB_USBSTS_PCI)) {
726 irq_status = IRQ_NONE;
730 val = readl(base + USB_PORTSC);
731 if (val & USB_PORTSC_CCS)
732 val &= ~USB_PORTSC_WKCN;
734 val &= ~USB_PORTSC_WKDS;
735 val &= ~USB_PORTSC_RWC_BITS;
736 writel(val , (base + USB_PORTSC));
738 } else if (!phy->phy_clk_on) {
740 irq_status = IRQ_HANDLED;
742 irq_status = IRQ_NONE;
750 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
753 void __iomem *base = phy->regs;
755 /* (2LS WAR)is not required for LS and FS devices and is only for HS */
756 /* Force DP/DM pulldown active for Host mode */
757 val = readl(base + UTMIP_MISC_CFG0);
758 val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
759 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
760 writel(val, base + UTMIP_MISC_CFG0);
761 val = readl(base + UTMIP_MISC_CFG0);
762 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
763 if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
764 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
766 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
767 writel(val, base + UTMIP_MISC_CFG0);
770 val = readl(base + UTMIP_MISC_CFG0);
771 val |= UTMIP_DPDM_OBSERVE;
772 writel(val, base + UTMIP_MISC_CFG0);
774 DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
775 PHY_DBG("ENABLE_OBS_BUS\n");
778 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
780 void __iomem *base = phy->regs;
781 unsigned long val, port_speed;
783 /* check if OBS bus is already enabled */
784 val = readl(base + UTMIP_MISC_CFG0);
785 if (val & UTMIP_DPDM_OBSERVE) {
786 PHY_DBG("DISABLE_OBS_BUS\n");
788 /* disable ALL interrupts on current CPU */
789 local_irq_save(flags);
791 /* Change the UTMIP OBS bus to drive SE0 */
792 val = readl(base + UTMIP_MISC_CFG0);
793 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
794 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
795 writel(val, base + UTMIP_MISC_CFG0);
797 port_speed = (readl(base + USB_PORTSC) >> 26) &
798 USB_PORTSC_PSPD_MASK;
799 if (port_speed == USB_PHY_PORT_SPEED_FULL) {
800 val = readl(base + UTMIP_MISC_CFG0);
801 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
802 writel(val, base + UTMIP_MISC_CFG0);
805 /* Release UTMIP OBS bus */
806 val = readl(base + UTMIP_MISC_CFG0);
807 val &= ~UTMIP_DPDM_OBSERVE;
808 writel(val, base + UTMIP_MISC_CFG0);
810 /* Release DP/DM pulldown for Host mode */
811 val = readl(base + UTMIP_MISC_CFG0);
812 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
813 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
814 writel(val, base + UTMIP_MISC_CFG0);
816 val = readl(base + USB_USBCMD);
817 val |= USB_USBCMD_RS;
818 writel(val, base + USB_USBCMD);
819 /* restore ALL interrupts on current CPU */
820 local_irq_restore(flags);
822 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
823 USB_USBCMD_RS, 2000)) {
824 pr_err("%s: timeout waiting for USB_USBCMD_RS\n",
832 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
835 unsigned int inst = phy->inst;
836 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
838 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
839 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL) {
840 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
841 /* if PMC is not disabled by now then disable it */
842 if (val & UTMIP_MASTER_ENABLE(inst))
843 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
845 utmi_phy_disable_obs_bus(phy);
850 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
853 unsigned int inst = phy->inst;
854 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
856 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
857 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
858 if (val & UTMIP_MASTER_ENABLE(inst)) {
859 if (!remote_wakeup) {
860 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
861 phy->pmc_remote_wakeup = false;
862 phy->pmc_hotplug_wakeup = false;
863 PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
866 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
867 utmi_phy_enable_obs_bus(phy);
873 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
876 void __iomem *base = phy->regs;
877 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
879 PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
880 if (!phy->phy_clk_on) {
881 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
882 __func__, __LINE__, phy->inst);
886 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
887 pmc_data[phy->inst].is_xhci = phy->pdata->u_data.dev.is_xhci;
888 pmc->pmc_ops->powerdown_pmc_wake_detect(pmc);
889 val = readl(base + USB_SUSP_CTRL);
890 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
891 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
892 writel(val, base + USB_SUSP_CTRL);
894 val = readl(base + UTMIP_BAT_CHRG_CFG0);
895 val |= UTMIP_PD_CHRG;
896 writel(val, base + UTMIP_BAT_CHRG_CFG0);
898 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
899 HOSTPC1_DEVLC_PSPD_MASK;
901 /* Disable interrupts */
902 writel(0, base + USB_USBINTR);
904 /* Clear the run bit to stop SOFs when USB is suspended */
905 val = readl(base + USB_USBCMD);
906 val &= ~USB_USBCMD_RS;
907 writel(val, base + USB_USBCMD);
909 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
910 USB_USBSTS_HCH, 2000)) {
911 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n"
915 pmc_data[phy->inst].port_speed = (readl(base +
916 HOSTPC1_DEVLC) >> 25) &
917 HOSTPC1_DEVLC_PSPD_MASK;
919 if (pmc_data[phy->inst].port_speed <
920 USB_PMC_PORT_SPEED_UNKNOWN)
921 phy->pmc_remote_wakeup = false;
923 phy->pmc_hotplug_wakeup = false;
925 if (phy->pdata->port_otg) {
926 bool id_present = false;
927 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
928 id_present = (val & USB_ID_STATUS) ? false : true;
930 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
932 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
935 val = readl(base + UTMIP_PMC_WAKEUP0);
936 val |= EVENT_INT_ENB;
937 writel(val, base + UTMIP_PMC_WAKEUP0);
938 PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, phy->inst);
940 val = readl(base + USB_SUSP_CTRL);
941 val &= ~USB_WAKE_ON_CNNT_EN_DEV;
942 writel(val, base + USB_SUSP_CTRL);
945 if (!phy->hot_plug) {
946 val = readl(base + UTMIP_XCVR_CFG0);
947 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
948 UTMIP_FORCE_PDZI_POWERDOWN);
949 writel(val, base + UTMIP_XCVR_CFG0);
952 val = readl(base + UTMIP_XCVR_CFG1);
953 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
954 UTMIP_FORCE_PDDR_POWERDOWN;
955 writel(val, base + UTMIP_XCVR_CFG1);
957 val = readl(base + UTMIP_BIAS_CFG1);
958 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
959 writel(val, base + UTMIP_BIAS_CFG1);
962 bool enable_hotplug = true;
963 /* if it is OTG port then make sure to enable hot-plug feature
964 only if host adaptor is connected, i.e id is low */
965 if (phy->pdata->port_otg) {
966 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
967 enable_hotplug = (val & USB_ID_STATUS) ? false : true;
969 if (enable_hotplug) {
970 /* Enable wakeup event of device plug-in/plug-out */
971 val = readl(base + USB_PORTSC);
972 if (val & USB_PORTSC_CCS)
973 val |= USB_PORTSC_WKDS;
975 val |= USB_PORTSC_WKCN;
976 writel(val, base + USB_PORTSC);
978 if (val & USB_PORTSC_CCS) {
979 val = readl(base + USB_SUSP_CTRL);
980 val &= ~USB_PHY_CLK_VALID_INT_ENB;
982 val = readl(base + USB_SUSP_CTRL);
983 val |= USB_PHY_CLK_VALID_INT_ENB;
985 writel(val, base + USB_SUSP_CTRL);
987 /* Disable PHY clock valid interrupts while going into suspend*/
988 val = readl(base + USB_SUSP_CTRL);
989 val &= ~USB_PHY_CLK_VALID_INT_ENB;
990 writel(val, base + USB_SUSP_CTRL);
994 /* Disable PHY clock */
995 val = readl(base + HOSTPC1_DEVLC);
996 val |= HOSTPC1_DEVLC_PHCD;
997 writel(val, base + HOSTPC1_DEVLC);
999 if (!phy->hot_plug) {
1000 val = readl(base + USB_SUSP_CTRL);
1002 writel(val, base + USB_SUSP_CTRL);
1005 utmi_phy_pad_disable();
1006 utmi_phy_iddq_override(true);
1008 phy->phy_clk_on = false;
1009 phy->hw_accessible = false;
1011 PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1017 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1020 void __iomem *base = phy->regs;
1021 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1022 void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1024 struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1025 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1027 PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1028 if (phy->phy_clk_on) {
1029 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1030 __func__, __LINE__, phy->inst);
1033 val = readl(base + USB_SUSP_CTRL);
1035 writel(val, base + USB_SUSP_CTRL);
1037 val = readl(base + UTMIP_TX_CFG0);
1038 val |= UTMIP_FS_PREABMLE_J;
1039 writel(val, base + UTMIP_TX_CFG0);
1041 val = readl(base + USB_USBMODE);
1042 val &= ~USB_USBMODE_MASK;
1043 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1044 val |= USB_USBMODE_HOST;
1046 val |= USB_USBMODE_DEVICE;
1047 writel(val, base + USB_USBMODE);
1049 val = readl(base + UTMIP_HSRX_CFG0);
1050 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1051 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1052 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1053 writel(val, base + UTMIP_HSRX_CFG0);
1055 val = readl(base + UTMIP_HSRX_CFG1);
1056 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1057 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1058 writel(val, base + UTMIP_HSRX_CFG1);
1060 if (tegra_platform_is_silicon()) {
1061 val = readl(base + UTMIP_DEBOUNCE_CFG0);
1062 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1063 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1064 writel(val, base + UTMIP_DEBOUNCE_CFG0);
1067 val = readl(base + UTMIP_MISC_CFG0);
1068 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1069 writel(val, base + UTMIP_MISC_CFG0);
1071 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1072 val = readl(base + USB_SUSP_CTRL);
1073 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1074 writel(val, base + USB_SUSP_CTRL);
1076 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1077 val &= ~UTMIP_PD_CHRG;
1078 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1080 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1081 val |= UTMIP_PD_CHRG;
1082 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1085 utmi_phy_pad_enable();
1087 val = readl(base + UTMIP_XCVR_CFG0);
1088 val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1089 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1090 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1091 UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1092 val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1093 val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1094 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1095 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1096 if (!config->xcvr_use_lsb) {
1097 if (!config->xcvr_hsslew_msb)
1098 val |= UTMIP_XCVR_HSSLEW_MSB(3);
1100 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew_msb);
1102 if (config->xcvr_hsslew_lsb)
1103 val |= UTMIP_XCVR_HSSLEW_LSB(config->xcvr_hsslew_lsb);
1104 writel(val, base + UTMIP_XCVR_CFG0);
1106 val = readl(base + UTMIP_XCVR_CFG1);
1107 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1108 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1109 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1110 writel(val, base + UTMIP_XCVR_CFG1);
1112 if (tegra_platform_is_silicon()) {
1113 val = readl(base + UTMIP_BIAS_CFG1);
1114 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1115 val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1116 writel(val, base + UTMIP_BIAS_CFG1);
1119 val = readl(base + UTMIP_SPARE_CFG0);
1120 val &= ~FUSE_SETUP_SEL;
1121 val |= FUSE_ATERM_SEL;
1122 writel(val, base + UTMIP_SPARE_CFG0);
1124 val = readl(base + USB_SUSP_CTRL);
1125 val |= UTMIP_PHY_ENABLE;
1126 writel(val, base + USB_SUSP_CTRL);
1128 val = readl(base + USB_SUSP_CTRL);
1129 val &= ~UTMIP_RESET;
1130 writel(val, base + USB_SUSP_CTRL);
1132 /* Bring UTMIPLL out of IDDQ mode while exiting from reset/suspend */
1133 utmi_phy_iddq_override(false);
1135 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1136 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2600))
1137 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1139 val = readl(base + HOSTPC1_DEVLC);
1140 val &= ~HOSTPC1_DEVLC_PHCD;
1141 writel(val, base + HOSTPC1_DEVLC);
1143 utmi_phy_set_snps_trking_data();
1146 writel(0, base + ICUSB_CTRL);
1148 val = readl(base + USB_USBMODE);
1149 val &= ~USB_USBMODE_MASK;
1150 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1151 val |= USB_USBMODE_HOST;
1153 val |= USB_USBMODE_DEVICE;
1154 writel(val, base + USB_USBMODE);
1156 val = readl(base + HOSTPC1_DEVLC);
1157 val &= ~HOSTPC1_DEVLC_PTS(~0);
1158 val |= HOSTPC1_DEVLC_STS;
1159 writel(val, base + HOSTPC1_DEVLC);
1161 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1162 pmc_data[phy->inst].is_xhci = phy->pdata->u_data.dev.is_xhci;
1163 pmc->pmc_ops->powerup_pmc_wake_detect(pmc);
1166 if (!readl(base + USB_ASYNCLISTADDR))
1168 val = readl(base + USB_TXFILLTUNING);
1169 if ((val & USB_FIFO_TXFILL_MASK) !=
1170 USB_FIFO_TXFILL_THRES(0x10)) {
1171 val = USB_FIFO_TXFILL_THRES(0x10);
1172 writel(val, base + USB_TXFILLTUNING);
1175 phy->phy_clk_on = true;
1176 phy->hw_accessible = true;
1178 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1179 val = readl(padctl_base + PADCTL_SNPS_OC_MAP);
1180 val |= CONTROLLER_OC(phy->inst, 0x4);
1181 writel(val, padctl_base + PADCTL_SNPS_OC_MAP);
1183 val = readl(padctl_base + PADCTL_OC_DET);
1185 val |= ENABLE0_OC_MAP(config->vbus_oc_map);
1187 val |= ENABLE1_OC_MAP(config->vbus_oc_map);
1188 writel(val, padctl_base + PADCTL_OC_DET);
1191 PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1195 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1198 int inst = phy->inst;
1199 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1201 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1202 val = tegra_usb_pmc_reg_read(UTMIP_STATUS);
1203 /* Check whether we wake up from the remote resume.
1204 For lp1 case, pmc is not responsible for waking the
1205 system, it's the flow controller and hence
1206 UTMIP_WALK_PTR_VAL(inst) will return 0.
1207 Also, for lp1 case phy->pmc_remote_wakeup will already be set
1208 to true by utmi_phy_irq() when the remote wakeup happens.
1209 Hence change the logic in the else part to enter only
1210 if phy->pmc_remote_wakeup is not set to true by the
1212 if (UTMIP_WALK_PTR_VAL(inst) & val) {
1213 phy->pmc_remote_wakeup = true;
1214 } else if (!phy->pmc_remote_wakeup) {
1215 val = tegra_usb_pmc_reg_read(PMC_SLEEP_CFG);
1216 if (val & UTMIP_MASTER_ENABLE(inst))
1217 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1219 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1220 utmi_phy_enable_obs_bus(phy);
1224 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1226 unsigned long val, flags = 0;
1227 void __iomem *base = phy->regs;
1228 int wait_time_us = 25000; /* FPR should be set by this time */
1229 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1231 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1232 /* check whether we wake up from the remote resume */
1233 if (phy->pmc_remote_wakeup) {
1234 /* wait until SUSPEND and RESUME bit
1235 * is cleared on remote resume */
1237 val = readl(base + USB_PORTSC);
1239 if (wait_time_us == 0) {
1240 PHY_DBG("%s PMC FPR" \
1241 "timeout val = 0x%x instance = %d\n", \
1242 __func__, (u32)val, phy->inst);
1243 if (phy->port_speed ==
1244 USB_PHY_PORT_SPEED_FULL) {
1245 val = readl(base + UTMIP_PMC_WAKEUP0);
1246 val &= ~EVENT_INT_ENB;
1247 writel(val, base + UTMIP_PMC_WAKEUP0);
1249 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1250 phy->pmc_remote_wakeup = false;
1251 phy->pmc_hotplug_wakeup = false;
1253 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1254 utmi_phy_post_resume(phy);
1258 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1260 /* Add delay sothat resume will be driven for more than 20 ms */
1261 if (phy->port_speed != USB_PHY_PORT_SPEED_FULL) {
1262 usleep_range(10000, 11000);
1263 local_irq_save(flags);
1264 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 1);
1265 phy->pmc_remote_wakeup = false;
1266 phy->pmc_hotplug_wakeup = false;
1267 local_irq_restore(flags);
1269 usleep_range(25000, 26000);
1270 local_irq_save(flags);
1271 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1272 phy->pmc_remote_wakeup = false;
1273 phy->pmc_hotplug_wakeup = false;
1274 local_irq_restore(flags);
1277 PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, phy->inst);
1279 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1280 USB_USBCMD_RS, 2000)) {
1281 pr_err("%s: timeout waiting for USB_USBCMD_RS\n",\
1285 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1286 val = readl(base + USB_USBSTS);
1287 writel(val, base + USB_USBSTS);
1288 /* wait to avoid SOF if there is any */
1289 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1290 USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1291 pr_err("%s: timeout waiting for SOF\n", __func__);
1294 if (phy->port_speed != USB_PHY_PORT_SPEED_FULL) {
1295 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1296 phy->pmc_remote_wakeup = false;
1297 phy->pmc_hotplug_wakeup = false;
1298 PHY_DBG("%s DISABLE_PMC inst = %d\n",
1299 __func__, phy->inst);
1302 if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1303 utmi_phy_post_resume(phy);
1306 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1310 int port_connected = 0;
1312 void __iomem *base = phy->regs;
1313 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1315 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1316 if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1317 if (readl(base + USB_ASYNCLISTADDR) &&
1318 !phy->pdata->u_data.host.power_off_on_suspend)
1321 val = readl(base + USB_PORTSC);
1322 port_connected = val & USB_PORTSC_CCS;
1323 is_lp0 = !(readl(base + USB_ASYNCLISTADDR));
1325 if ((phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) &&
1326 (port_connected ^ is_lp0)) {
1327 utmi_phy_restore_start(phy);
1328 usb_phy_bringup_host_controller(phy);
1329 utmi_phy_restore_end(phy);
1331 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1332 phy->pmc_remote_wakeup = false;
1333 phy->pmc_hotplug_wakeup = false;
1335 /* bring up the controller from suspend*/
1336 val = readl(base + USB_USBCMD);
1337 val |= USB_CMD_RESET;
1338 writel(val, base + USB_USBCMD);
1340 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1341 USB_CMD_RESET, 0, 2500) < 0) {
1342 pr_err("%s: timeout waiting for reset\n", __func__);
1345 val = readl(base + USB_USBMODE);
1346 val &= ~USB_USBMODE_MASK;
1347 val |= USB_USBMODE_HOST;
1348 writel(val, base + USB_USBMODE);
1350 val = readl(base + HOSTPC1_DEVLC);
1351 val &= ~HOSTPC1_DEVLC_PTS(~0);
1352 val |= HOSTPC1_DEVLC_STS;
1353 writel(val, base + HOSTPC1_DEVLC);
1355 writel(USB_USBCMD_RS, base + USB_USBCMD);
1357 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1358 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1359 pr_err("%s: timeout waiting for run bit\n", __func__);
1362 /* Enable Port Power */
1363 val = readl(base + USB_PORTSC);
1364 val |= USB_PORTSC_PP;
1365 writel(val, base + USB_PORTSC);
1368 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1369 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1371 val = readl(base + USB_TXFILLTUNING);
1372 if ((val & USB_FIFO_TXFILL_MASK) !=
1373 USB_FIFO_TXFILL_THRES(0x10)) {
1374 val = USB_FIFO_TXFILL_THRES(0x10);
1375 writel(val, base + USB_TXFILLTUNING);
1382 static unsigned long utmi_phy_set_dp_dm_pull_up_down(struct tegra_usb_phy *phy,
1383 unsigned long pull_up_down_flags)
1387 void __iomem *base = phy->regs;
1389 org = readl(base + UTMIP_MISC_CFG0);
1391 val = org & ~MASK_ALL_PULLUP_PULLDOWN;
1392 val |= pull_up_down_flags;
1394 writel(val, base + UTMIP_MISC_CFG0);
1396 usleep_range(500, 2000);
1400 unsigned long utmi_phy_get_dp_dm_status(struct tegra_usb_phy *phy,
1401 unsigned long pull_up_down_flags)
1403 void __iomem *base = phy->regs;
1404 unsigned long org_flags;
1407 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy, pull_up_down_flags);
1408 ret = USB_PORTSC_LINE_STATE(readl(base + USB_PORTSC));
1409 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1413 static void disable_charger_detection(void __iomem *base)
1417 /* Disable charger detection logic */
1418 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1419 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1420 val &= ~(UTMIP_ON_SRC_EN | UTMIP_OP_SINK_EN);
1421 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1423 /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1424 msleep(TDPSRC_CON_MS);
1428 * Per Battery Charging Specification 1.2 section 3.2.3:
1429 * We check Data Contact Detect (DCD) before we check the USB cable type.
1431 static bool utmi_phy_dcd_detect(struct tegra_usb_phy *phy)
1433 void __iomem *base = phy->regs;
1435 unsigned long org_flags;
1438 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1439 /* inject IDP_SRC */
1440 val |= UTMIP_OP_I_SRC_EN;
1441 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1442 /* enable pull down resistor RDM_DWN on D- */
1443 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1444 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1445 DISABLE_PULLDN_DP | FORCE_PULLDN_DM);
1446 usleep_range(20000, 30000);
1449 if (0 == USB_PORTSC_LINE_STATE(readl(base + USB_PORTSC))) {
1450 /* minimum debounce time is 10mS per TDCD_DBNC */
1451 usleep_range(10000, 12000);
1452 if (0 == USB_PORTSC_LINE_STATE(readl(base + USB_PORTSC)))
1456 val &= ~UTMIP_OP_I_SRC_EN;
1457 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1458 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1462 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1465 void __iomem *base = phy->regs;
1469 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1470 if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1471 /* Charger detection is not there for ULPI
1472 * return Charger not available */
1476 /* ensure we start from an initial state */
1477 writel(0, base + UTMIP_BAT_CHRG_CFG0);
1478 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1480 /* log initial values */
1481 DBG("%s(%d) inst:[%d], UTMIP_BAT_CHRG_CFG0 = %08X\n",
1483 phy->inst, readl(base + UTMIP_BAT_CHRG_CFG0));
1484 DBG("%s(%d) inst:[%d], UTMIP_MISC_CFG0 = %08X\n",
1486 phy->inst, readl(base + UTMIP_MISC_CFG0));
1488 /* DCD timeout max value is 900mS */
1490 while (dcd_timeout_ms < 900) {
1491 /* standard DCD detect for SDP/DCP/CDP */
1492 if (utmi_phy_dcd_detect(phy))
1494 /* for NV-charger, we wait D+/D- both set */
1495 if ((USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET) ==
1496 utmi_phy_get_dp_dm_status(phy,
1497 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1498 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM))
1500 usleep_range(20000, 22000);
1501 dcd_timeout_ms += 22;
1504 /* Enable charger detection logic */
1505 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1506 val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1507 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1509 /* Source should be on for 100 ms as per USB charging spec */
1510 msleep(TDP_SRC_ON_MS);
1512 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1513 /* If charger is not connected disable the interrupt */
1514 val &= ~VDAT_DET_INT_EN;
1515 val |= VDAT_DET_CHG_DET;
1516 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1518 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1519 if (val & VDAT_DET_STS)
1523 disable_charger_detection(base);
1525 DBG("%s(%d) inst:[%d], UTMIP_BAT_CHRG_CFG0 = %08X\n",
1527 phy->inst, readl(base + UTMIP_BAT_CHRG_CFG0));
1528 DBG("%s(%d) inst:[%d], UTMIP_MISC_CFG0 = %08X\n",
1530 phy->inst, readl(base + UTMIP_MISC_CFG0));
1532 DBG("%s(%d) inst:[%d] DONE Status = %d\n",
1533 __func__, __LINE__, phy->inst, status);
1538 static bool cdp_charger_detection(struct tegra_usb_phy *phy)
1542 void __iomem *base = phy->regs;
1545 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1546 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1547 val |= UTMIP_ON_SRC_EN | UTMIP_OP_SINK_EN;
1548 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1550 DBG("%s(%d) UTMIP_BAT_CHRG_CFG0 = %08x\n",
1552 readl(base + UTMIP_BAT_CHRG_CFG0));
1556 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1557 if (val & VDAT_DET_STS) {
1559 DBG("%s: DCP detected\n", __func__);
1562 disable_charger_detection(base);
1563 DBG("%s: No voltage from D- to D+ found\n", __func__);
1569 static bool maxim_charger_detection(struct tegra_usb_phy *phy)
1571 void __iomem *base = phy->regs;
1573 unsigned long org_flags;
1577 * Enable charger detection logic
1578 * 3.3V on D+, Sink D- (high speed usb)
1579 * Maxim charger will remove short !! -- DCP will not
1581 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1582 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1583 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1584 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1585 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1586 val &= ~(UTMIP_ON_SRC_EN | UTMIP_OP_SINK_EN);
1587 val |= UTMIP_ON_SINK_EN;
1588 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1590 /* Source should be on at least 120 ms per Maxim spec */
1591 msleep(MAXIM_DEBOUNCE_TIME);
1593 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1594 if (val & VDAT_DET_STS) {
1596 DBG("%s: Maxim charger not found\n", __func__);
1597 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1600 DBG("%s: Maxim Charger detected\n", __func__);
1603 disable_charger_detection(base);
1607 static bool utmi_phy_qc2_charger_detect(struct tegra_usb_phy *phy,
1611 void __iomem *base = phy->regs;
1615 unsigned long org_flags;
1616 #ifdef QC_MEASURE_VOLTAGES
1620 DBG("%s(%d) inst:[%d] max_voltage = %d\n",
1621 __func__, __LINE__, phy->inst, max_voltage);
1624 /* no need to detect qc2 if operating at 5V */
1625 switch (max_voltage) {
1626 case TEGRA_USB_QC2_5V:
1627 case TEGRA_USB_QC2_9V:
1628 case TEGRA_USB_QC2_12V:
1629 case TEGRA_USB_QC2_20V:
1632 disable_charger_detection(base);
1636 /* Ensure we start from an initial state */
1637 writel(0, base + UTMIP_BAT_CHRG_CFG0);
1638 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1641 * The QC2 charger can be inserted when the system is
1642 * powered down. In this case it will act as a DCP unless
1643 * it is forced to negotiate voltage. This is because
1644 * the QC2 charger will not see D+/D- voltage signaling
1645 * with in its negotiation timer window.
1646 * We try to detect this condition. We know that if
1647 * we enter suspend then system must be active before
1648 * the QC2 charger was seen.
1649 * In this case no reset of the charger is needed, otherwise
1650 * we force the D+ and D- Pull Up down which will reset a
1651 * QC2 charger but have no effect on a normal DCP.
1653 if (!phy->qc2_no_reset) {
1654 phy->qc2_no_reset = true;
1655 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1656 FORCE_PULLDN_DP | FORCE_PULLDN_DM);
1659 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1662 /* Enable charger detection logic */
1663 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1664 val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1665 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1667 /* Source should be on for 100 ms as per USB charging spec */
1668 msleep(TDP_SRC_ON_MS);
1670 /* if vbus drops we are connected to quick charge 2 */
1672 while (qc2_timeout_ms < 1500) {
1673 usleep_range(1000, 1200);
1674 qc2_timeout_ms += 1;
1675 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1676 if (!(val & VDAT_DET_STS)) {
1682 if (vbus_stat && qc2_timeout_ms > 100) {
1685 DBG("%s(%d) inst:[%d], QC2 DETECTED !!!",
1686 __func__, __LINE__, phy->inst);
1688 /* Wall charger needs time before setting D+/D- */
1689 usleep_range(25000, 26000);
1691 switch (max_voltage) {
1692 case TEGRA_USB_QC2_9V:
1693 /* Set the input voltage to 9V */
1694 /* D+ 3.3v -- D- 0.6v */
1695 DBG("%s(%d) inst:[%d], QC 9V D+ 3.3v D- 0.6v",
1696 __func__, __LINE__, phy->inst);
1697 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1698 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1699 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1700 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1701 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1702 val |= UTMIP_ON_SRC_EN;
1703 val &= ~UTMIP_OP_SRC_EN;
1704 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1707 case TEGRA_USB_QC2_12V:
1708 /* 0.6v v on D+ and D- */
1709 DBG("%s(%d) inst:[%d], QC 12V D+ 0.6v D- 0.6v",
1710 __func__, __LINE__, phy->inst);
1711 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1712 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1713 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1714 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1715 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1716 val |= (UTMIP_OP_SRC_EN | UTMIP_ON_SRC_EN);
1717 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1720 case TEGRA_USB_QC2_20V:
1721 /* 3.3 v on D+ and D- */
1722 DBG("%s(%d) inst:[%d], QC 20V D+ 3.3v D- 3.3v",
1723 __func__, __LINE__, phy->inst);
1724 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1725 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1726 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1727 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1728 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1729 val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SRC_EN);
1730 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1733 case TEGRA_USB_QC2_5V:
1735 DBG("%s(%d) inst:[%d], QC 5V D+ 0.6v D- GND",
1736 __func__, __LINE__, phy->inst);
1737 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1738 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1739 DISABLE_PULLDN_DP | FORCE_PULLDN_DM);
1740 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1741 val &= ~(UTMIP_OP_SINK_EN | UTMIP_ON_SINK_EN);
1742 val |= UTMIP_OP_SRC_EN;
1743 val &= ~UTMIP_ON_SRC_EN;
1744 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1748 #ifdef QC_MEASURE_VOLTAGES
1750 DBG("%s(%d) MEASURE VOLTAGES -- you have %d seconds",
1751 __func__, __LINE__, timeout);
1752 while (timeout-- > 0) {
1753 DBG("%s(%d) COUNT = %d",
1754 __func__, __LINE__, timeout);
1761 * If QC2 charger detected do not disable the charger
1762 * detection voltage on D- and D+. Doing this will
1763 * cause it to move to 5V
1766 disable_charger_detection(base);
1768 DBG("%s(%d) inst:[%d] DONE Status = %d\n",
1769 __func__, __LINE__, phy->inst, status);
1773 static bool utmi_phy_is_non_std_charger(struct tegra_usb_phy *phy)
1776 * non std charger has D+/D- line float, we can apply pull up/down on
1777 * each line and verify if line status change.
1779 /* pull up DP only */
1780 if (USB_PORTSC_LINE_DP_SET != utmi_phy_get_dp_dm_status(phy,
1781 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1782 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM))
1783 goto NOT_NON_STD_CHARGER;
1785 /* pull down DP only */
1786 if (0x0 != utmi_phy_get_dp_dm_status(phy,
1787 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1788 FORCE_PULLDN_DP | DISABLE_PULLDN_DM))
1789 goto NOT_NON_STD_CHARGER;
1791 /* pull up DM only */
1792 if (USB_PORTSC_LINE_DM_SET != utmi_phy_get_dp_dm_status(phy,
1793 DISABLE_PULLUP_DP | FORCE_PULLUP_DM |
1794 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM))
1795 goto NOT_NON_STD_CHARGER;
1797 /* pull down DM only */
1798 if (0x0 != utmi_phy_get_dp_dm_status(phy,
1799 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1800 DISABLE_PULLDN_DP | FORCE_PULLDN_DM))
1801 goto NOT_NON_STD_CHARGER;
1803 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1806 NOT_NON_STD_CHARGER:
1807 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1812 static void utmi_phy_pmc_disable(struct tegra_usb_phy *phy)
1814 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
1815 if (phy->pdata->u_data.host.turn_off_vbus_on_lp0 &&
1816 phy->pdata->port_otg) {
1817 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
1818 pmc->pmc_ops->powerdown_pmc_wake_detect(pmc);
1821 static bool utmi_phy_nv_charger_detect(struct tegra_usb_phy *phy)
1828 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1830 if (utmi_phy_is_non_std_charger(phy))
1834 /* Turn off all terminations except DP pulldown */
1835 status1 = utmi_phy_get_dp_dm_status(phy,
1836 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1837 FORCE_PULLDN_DP | DISABLE_PULLDN_DM);
1839 /* Turn off all terminations except for DP pullup */
1840 status2 = utmi_phy_get_dp_dm_status(phy,
1841 FORCE_PULLUP_DP | DISABLE_PULLUP_DM |
1842 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1844 /* Check for NV charger DISABLE all terminations */
1845 status3 = utmi_phy_get_dp_dm_status(phy,
1846 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1847 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1849 if ((status1 == (USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET)) &&
1850 (status2 == (USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET)) &&
1851 (status3 == (USB_PORTSC_LINE_DP_SET | USB_PORTSC_LINE_DM_SET)))
1854 /* Restore standard termination by hardware. */
1855 utmi_phy_set_dp_dm_pull_up_down(phy, 0);
1859 static bool utmi_phy_apple_charger_1000ma_detect(struct tegra_usb_phy *phy)
1863 void __iomem *base = phy->regs;
1864 unsigned long org_flags;
1866 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1869 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1870 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1871 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1872 usleep_range(20000, 30000);
1873 utmi_phy_set_dp_dm_pull_up_down(phy,
1874 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1875 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1877 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1879 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1881 usleep_range(10000, 20000);
1883 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1885 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1887 if ((val & VOP_DIV2P0_DET) && (val & VON_DIV2P7_DET))
1890 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1895 static bool utmi_phy_apple_charger_2000ma_detect(struct tegra_usb_phy *phy)
1899 void __iomem *base = phy->regs;
1900 unsigned long org_flags;
1902 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1905 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1906 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1907 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1908 usleep_range(20000, 30000);
1909 utmi_phy_set_dp_dm_pull_up_down(phy,
1910 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1911 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1913 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1915 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1917 usleep_range(10000, 20000);
1919 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1921 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1923 if ((val & VOP_DIV2P7_DET) && (val & VON_DIV2P0_DET))
1926 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1931 static bool utmi_phy_apple_charger_500ma_detect(struct tegra_usb_phy *phy)
1935 void __iomem *base = phy->regs;
1936 unsigned long org_flags;
1938 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1941 org_flags = utmi_phy_set_dp_dm_pull_up_down(phy,
1942 FORCE_PULLUP_DP | FORCE_PULLUP_DM |
1943 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1944 usleep_range(20000, 30000);
1945 utmi_phy_set_dp_dm_pull_up_down(phy,
1946 DISABLE_PULLUP_DP | DISABLE_PULLUP_DM |
1947 DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1949 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1951 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1953 usleep_range(10000, 20000);
1955 val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1957 writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1959 if ((val & VOP_DIV2P0_DET) && (val & VON_DIV2P0_DET))
1962 utmi_phy_set_dp_dm_pull_up_down(phy, org_flags);
1967 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1969 void __iomem *base = phy->regs;
1971 unsigned int inst = phy->inst;
1973 val = readl(base + UHSIC_PMC_WAKEUP0);
1974 if (!(val & EVENT_INT_ENB))
1976 val = tegra_usb_pmc_reg_read(UHSIC_STATUS(inst));
1977 if (!(UHSIC_WAKE_ALARM(inst) & val))
1979 tegra_usb_pmc_reg_update(PMC_UHSIC_SLEEP_CFG(inst),
1980 UHSIC_WAKE_VAL(inst, WAKE_VAL_ANY),
1981 UHSIC_WAKE_VAL(inst, WAKE_VAL_NONE));
1983 tegra_usb_pmc_reg_update(PMC_UHSIC_TRIGGERS(inst),
1984 0, UHSIC_CLR_WAKE_ALARM(inst));
1986 val = readl(base + UHSIC_PMC_WAKEUP0);
1987 val &= ~EVENT_INT_ENB;
1988 writel(val, base + UHSIC_PMC_WAKEUP0);
1989 phy->pmc_remote_wakeup = true;
1990 DBG("%s:PMC interrupt detected for HSIC\n", __func__);
1994 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1997 void __iomem *base = phy->regs;
1999 if (remote_wakeup) {
2001 val = readl(base + USB_USBCMD);
2002 val |= USB_USBCMD_RS;
2003 writel(val, base + USB_USBCMD);
2006 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2011 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2014 void __iomem *base = phy->regs;
2015 unsigned int inst = phy->inst;
2016 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2018 val = tegra_usb_pmc_reg_read(UHSIC_STATUS(inst));
2020 /* check whether we wake up from the remote resume */
2021 if (UHSIC_WALK_PTR_VAL(inst) & val) {
2022 phy->pmc_remote_wakeup = true;
2023 DBG("%s: uhsic remote wakeup detected\n", __func__);
2025 if (!((UHSIC_STROBE_VAL(inst) | UHSIC_DATA_VAL(inst)) & val)) {
2028 * If pmc wakeup is detected after putting controller
2029 * in suspend in usb_phy_bringup_host_cotroller,
2030 * restart bringing up host controller as
2031 * in case of only pmc wakeup.
2033 if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2034 usb_phy_bringup_host_controller(phy);
2035 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2036 (USB_PORTSC_RESUME | USB_PORTSC_SUSP),
2037 0, FPR_WAIT_TIME_US) < 0)
2038 pr_err("%s: timeout waiting" \
2039 "for SUSPEND to clear\n",
2041 phy->ctrlr_suspended = false;
2044 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
2045 phy->pmc_remote_wakeup = false;
2047 DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2048 val = readl(base + UHSIC_CMD_CFG0);
2049 val |= UHSIC_PRETEND_CONNECT_DETECT;
2050 writel(val, base + UHSIC_CMD_CFG0);
2055 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2058 unsigned long val, flags = 0;
2059 void __iomem *base = phy->regs;
2060 int wait_time_us = FPR_WAIT_TIME_US; /* FPR should be set by this time */
2061 bool irq_disabled = false;
2062 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2063 bool remote_wakeup_detected;
2065 DBG("%s(%d)\n", __func__, __LINE__);
2067 remote_wakeup_detected = phy->pmc_remote_wakeup;
2069 * check whether we wake up from the remote wake detected before putting
2070 * controller in suspend in usb_phy_bringup_host_controller.
2072 if (!phy->ctrlr_suspended) {
2073 /* wait until FPR bit is set automatically on remote resume */
2075 val = readl(base + USB_PORTSC);
2077 if (wait_time_us == 0) {
2079 * If pmc wakeup is detected after putting controller
2080 * in suspend in usb_phy_bringup_host_cotroller,
2081 * restart bringing up host controller as
2082 * in case of only pmc wakeup.
2084 if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2085 usb_phy_bringup_host_controller(phy);
2086 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2087 (USB_PORTSC_RESUME | USB_PORTSC_SUSP),
2088 0, FPR_WAIT_TIME_US) < 0)
2089 pr_err("%s: timeout waiting" \
2090 " for SUSPEND to clear\n",
2092 phy->ctrlr_suspended = false;
2095 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
2096 phy->pmc_remote_wakeup = false;
2100 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
2101 /* In case of remote wakeup, disable local irq to prevent
2102 * context switch b/t disable PMC and set RUN bit ops */
2103 local_irq_save(flags);
2104 irq_disabled = true;
2107 /* Disable PMC remote wake-up detection */
2108 val = readl(base + UHSIC_PMC_WAKEUP0);
2109 val &= ~EVENT_INT_ENB;
2110 writel(val, base + UHSIC_PMC_WAKEUP0);
2113 * If pmc wakeup is detected after putting controller in suspend
2114 * in usb_phy_bringup_host_cotroller, restart bringing up host
2115 * controller as in case of only pmc wakeup.
2117 if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2118 usb_phy_bringup_host_controller(phy);
2119 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2120 (USB_PORTSC_RESUME | USB_PORTSC_SUSP), 0,
2121 FPR_WAIT_TIME_US) < 0)
2122 pr_err("%s: timeout waiting for SUSPEND to clear\n",
2124 phy->ctrlr_suspended = false;
2127 val = tegra_usb_pmc_reg_read(PMC_UHSIC_SLEEP_CFG(phy->inst));
2128 if (val & UHSIC_MASTER_ENABLE(phy->inst)) {
2129 val = readl(base + UHSIC_PADS_CFG1);
2130 val &= ~(UHSIC_PD_TX);
2131 writel(val, base + UHSIC_PADS_CFG1);
2135 local_irq_restore(flags);
2136 usleep_range(25000, 26000);
2137 local_irq_save(flags);
2139 usleep_range(10000, 11000);
2141 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 1);
2142 phy->pmc_remote_wakeup = false;
2144 /* Restore local irq if disabled before */
2146 local_irq_restore(flags);
2147 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2148 USB_USBCMD_RS, 2000)) {
2149 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2152 if (remote_wakeup_detected && phy->pdata->ops &&
2153 phy->pdata->ops->post_remote_wakeup)
2154 phy->pdata->ops->post_remote_wakeup();
2157 static int uhsic_rail_enable(struct tegra_usb_phy *phy)
2161 if (phy->hsic_reg == NULL) {
2162 phy->hsic_reg = regulator_get(&phy->pdev->dev, "vddio_hsic");
2163 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2164 pr_err("UHSIC: Could not get regulator vddio_hsic\n");
2165 ret = PTR_ERR(phy->hsic_reg);
2166 phy->hsic_reg = NULL;
2171 ret = regulator_enable(phy->hsic_reg);
2173 pr_err("%s vddio_hsic could not be enabled\n", __func__);
2180 static int uhsic_rail_disable(struct tegra_usb_phy *phy)
2184 if (phy->hsic_reg == NULL) {
2185 pr_warn("%s: unbalanced disable\n", __func__);
2189 ret = regulator_disable(phy->hsic_reg);
2191 pr_err("HSIC regulator vddio_hsic cannot be disabled\n");
2194 regulator_put(phy->hsic_reg);
2195 phy->hsic_reg = NULL;
2199 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2201 unsigned long parent_rate;
2204 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2206 phy->hsic_reg = NULL;
2207 ret = uhsic_rail_enable(phy);
2209 pr_err("%s vddio_hsic could not be enabled\n", __func__);
2213 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2214 parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2215 for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2216 if (uhsic_freq_table[i].freq == parent_rate) {
2217 phy->freq = &uhsic_freq_table[i];
2222 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2225 /* reset controller for reenumerating hsic device */
2226 tegra_periph_reset_assert(phy->ctrlr_clk);
2228 tegra_periph_reset_deassert(phy->ctrlr_clk);
2232 pmc->pmc_ops->powerup_pmc_wake_detect(pmc);
2237 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2240 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2242 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2243 pmc->pmc_ops->powerdown_pmc_wake_detect(pmc);
2245 ret = uhsic_rail_disable(phy);
2247 pr_err("%s vddio_hsic could not be disabled\n", __func__);
2250 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2253 void __iomem *base = phy->regs;
2254 int irq_status = IRQ_HANDLED;
2256 /* check if there is any remote wake event */
2257 if (!phy->pdata->unaligned_dma_buf_supported)
2258 usb_phy_fence_read(phy);
2259 if (uhsic_phy_remotewake_detected(phy))
2260 DBG("%s: uhsic remote wake detected\n", __func__);
2262 val = readl(base + USB_SUSP_CTRL);
2263 if ((val & USB_PHY_CLK_VALID_INT_STS) &&
2264 (val & USB_PHY_CLK_VALID_INT_ENB)) {
2265 val &= ~USB_PHY_CLK_VALID_INT_ENB |
2266 USB_PHY_CLK_VALID_INT_STS;
2267 writel(val , (base + USB_SUSP_CTRL));
2269 val = readl(base + USB_USBSTS);
2270 if (!(val & USB_USBSTS_PCI)) {
2271 irq_status = IRQ_NONE;
2275 val = readl(base + USB_PORTSC);
2276 if (val & USB_PORTSC_CCS)
2277 val &= ~USB_PORTSC_WKCN;
2278 val &= ~USB_PORTSC_RWC_BITS;
2279 writel(val , (base + USB_PORTSC));
2280 irq_status = IRQ_HANDLED;
2286 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2289 void __iomem *base = phy->regs;
2290 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2291 void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
2294 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2296 if (phy->phy_clk_on) {
2297 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2298 __func__, __LINE__, phy->inst);
2302 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2303 val = readl(padctl_base + PADCTL_SNPS_OC_MAP);
2304 val |= CONTROLLER_OC(phy->inst, 0x7);
2305 writel(val, padctl_base + PADCTL_SNPS_OC_MAP);
2308 val = readl(base + UHSIC_PADS_CFG1);
2309 val &= ~(UHSIC_PD_BG | UHSIC_PD_RX |
2310 UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2311 writel(val, base + UHSIC_PADS_CFG1);
2313 val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2314 val |= UHSIC_AUTO_RTERM_EN;
2315 writel(val, base + UHSIC_PADS_CFG1);
2317 val = readl(base + USB_SUSP_CTRL);
2319 writel(val, base + USB_SUSP_CTRL);
2322 val = readl(base + USB_SUSP_CTRL);
2323 val |= UHSIC_PHY_ENABLE;
2324 writel(val, base + USB_SUSP_CTRL);
2326 val = readl(base + UHSIC_HSRX_CFG0);
2327 val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
2328 val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
2329 val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
2330 writel(val, base + UHSIC_HSRX_CFG0);
2332 val = readl(base + UHSIC_HSRX_CFG1);
2333 val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
2334 writel(val, base + UHSIC_HSRX_CFG1);
2337 val = readl(base + UHSIC_TX_CFG0);
2338 val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2339 writel(val, base + UHSIC_TX_CFG0);
2341 val = readl(base + UHSIC_MISC_CFG0);
2342 val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2343 writel(val, base + UHSIC_MISC_CFG0);
2345 val = readl(base + UHSIC_MISC_CFG1);
2346 val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2347 writel(val, base + UHSIC_MISC_CFG1);
2349 val = readl(base + UHSIC_PLL_CFG1);
2350 val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2351 val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2352 writel(val, base + UHSIC_PLL_CFG1);
2354 val = readl(base + USB_SUSP_CTRL);
2355 val &= ~(UHSIC_RESET);
2356 writel(val, base + USB_SUSP_CTRL);
2359 val = tegra_usb_pmc_reg_read(PMC_UHSIC_SLEEP_CFG(phy->inst));
2360 if (!(val & UHSIC_MASTER_ENABLE(phy->inst))) {
2361 val = readl(base + UHSIC_PADS_CFG1);
2362 val &= ~(UHSIC_PD_TX);
2363 writel(val, base + UHSIC_PADS_CFG1);
2366 /* HSIC pad tracking circuit power down sequence */
2367 val = readl(base + UHSIC_PADS_CFG1);
2368 val &= ~(UHSIC_PD_TRK);
2369 writel(val, base + UHSIC_PADS_CFG1);
2370 /* Wait for 25usec */
2372 val |= UHSIC_PD_TRK;
2373 writel(val, base + UHSIC_PADS_CFG1);
2375 /* Enable bus keepers always */
2376 val = readl(base + UHSIC_SPARE_CFG0);
2378 writel(val, base + UHSIC_SPARE_CFG0);
2380 /*SUSP_CTRL has to be toggled to enable host PHY clock */
2381 val = readl(base + USB_SUSP_CTRL);
2382 val |= USB_SUSP_CLR;
2383 writel(val, base + USB_SUSP_CTRL);
2385 val = readl(base + USB_SUSP_CTRL);
2386 val &= ~USB_SUSP_CLR;
2387 writel(val, base + USB_SUSP_CTRL);
2389 val = readl(base + USB_USBMODE);
2390 val |= USB_USBMODE_HOST;
2391 writel(val, base + USB_USBMODE);
2393 /* Change the USB controller PHY type to HSIC */
2394 val = readl(base + HOSTPC1_DEVLC);
2395 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2396 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2397 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2398 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2399 val &= ~HOSTPC1_DEVLC_STS;
2400 writel(val, base + HOSTPC1_DEVLC);
2402 val = readl(base + USB_PORTSC);
2403 val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS);
2404 writel(val, base + USB_PORTSC);
2406 val = readl(base + UHSIC_TX_CFG0);
2407 val |= UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE;
2408 writel(val, base + UHSIC_TX_CFG0);
2410 val = readl(base + UHSIC_PADS_CFG0);
2411 /* Clear RTUNEP, SLEWP & SLEWN bit fields */
2412 val &= ~(UHSIC_TX_RTUNEP | UHSIC_TX_SLEWP | UHSIC_TX_SLEWN);
2413 /* set Rtune impedance to 50 ohm */
2414 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
2415 val |= UHSIC_TX_RTUNE_P(0xA);
2417 val |= UHSIC_TX_RTUNE_P(0xC);
2419 writel(val, base + UHSIC_PADS_CFG0);
2421 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2422 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2423 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2427 phy->phy_clk_on = true;
2428 phy->hw_accessible = true;
2430 if (!readl(base + USB_ASYNCLISTADDR))
2433 if (phy->pmc_sleepwalk) {
2434 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2436 uhsic_phy_restore_start(phy);
2437 usb_phy_bringup_host_controller(phy);
2438 uhsic_phy_restore_end(phy);
2439 phy->pmc_sleepwalk = false;
2442 val = readl(base + USB_TXFILLTUNING);
2443 if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2444 val = USB_FIFO_TXFILL_THRES(0x10);
2445 writel(val, base + USB_TXFILLTUNING);
2451 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2454 void __iomem *base = phy->regs;
2455 bool port_connected;
2456 struct tegra_usb_pmc_data *pmc = &pmc_data[phy->inst];
2458 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2459 if (!phy->phy_clk_on) {
2460 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2461 __func__, __LINE__, phy->inst);
2465 /* Disable interrupts */
2466 writel(0, base + USB_USBINTR);
2468 /* check for port connect status */
2469 val = readl(base + USB_PORTSC);
2470 port_connected = val & USB_PORTSC_CCS;
2472 if (phy->pmc_sleepwalk == false && port_connected) {
2473 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
2475 phy->pmc_remote_wakeup = false;
2476 phy->pmc_sleepwalk = true;
2478 val = readl(base + UHSIC_PMC_WAKEUP0);
2479 val |= EVENT_INT_ENB;
2480 writel(val, base + UHSIC_PMC_WAKEUP0);
2482 val = readl(base + USB_SUSP_CTRL);
2483 val &= ~USB_WAKE_ON_CNNT_EN_DEV;
2484 writel(val, base + USB_SUSP_CTRL);
2486 phy->pmc_sleepwalk = true;
2489 val = readl(base + HOSTPC1_DEVLC);
2490 val |= HOSTPC1_DEVLC_PHCD;
2491 writel(val, base + HOSTPC1_DEVLC);
2493 /* Remove power downs for HSIC from PADS CFG1 register */
2494 val = readl(base + UHSIC_PADS_CFG1);
2495 val |= (UHSIC_PD_BG | UHSIC_PD_TRK |
2496 UHSIC_PD_ZI | UHSIC_PD_TX);
2497 writel(val, base + UHSIC_PADS_CFG1);
2499 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2500 USB_PHY_CLK_VALID, 0, 2500))
2501 pr_warn("%s: timeout waiting for phy to disable\n", __func__);
2503 DBG("%s(%d) inst:[%d] End\n", __func__, __LINE__, phy->inst);
2505 phy->phy_clk_on = false;
2506 phy->hw_accessible = false;
2511 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2514 void __iomem *base = phy->regs;
2516 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2518 val = readl(base + USB_USBMODE);
2519 val |= USB_USBMODE_HOST;
2520 writel(val, base + USB_USBMODE);
2522 /* Change the USB controller PHY type to HSIC */
2523 val = readl(base + HOSTPC1_DEVLC);
2524 val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2525 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2526 val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2527 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2528 writel(val, base + HOSTPC1_DEVLC);
2530 val = readl(base + UHSIC_MISC_CFG0);
2531 val |= UHSIC_DETECT_SHORT_CONNECT;
2532 writel(val, base + UHSIC_MISC_CFG0);
2534 if (phy->pdata->ops && phy->pdata->ops->port_power)
2535 phy->pdata->ops->port_power();
2540 static struct tegra_usb_phy_ops utmi_phy_ops = {
2541 .init = _usb_phy_init,
2542 .reset = usb_phy_reset,
2543 .open = utmi_phy_open,
2544 .close = utmi_phy_close,
2545 .irq = utmi_phy_irq,
2546 .power_on = utmi_phy_power_on,
2547 .power_off = utmi_phy_power_off,
2548 .pre_resume = utmi_phy_pre_resume,
2549 .resume = utmi_phy_resume,
2550 .post_resume = utmi_phy_post_resume,
2551 .charger_detect = utmi_phy_charger_detect,
2552 .qc2_charger_detect = utmi_phy_qc2_charger_detect,
2553 .cdp_charger_detect = cdp_charger_detection,
2554 .nv_charger_detect = utmi_phy_nv_charger_detect,
2555 .maxim_charger_14675 = maxim_charger_detection,
2556 .apple_charger_1000ma_detect = utmi_phy_apple_charger_1000ma_detect,
2557 .apple_charger_2000ma_detect = utmi_phy_apple_charger_2000ma_detect,
2558 .apple_charger_500ma_detect = utmi_phy_apple_charger_500ma_detect,
2559 .pmc_disable = utmi_phy_pmc_disable,
2562 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2563 .init = _usb_phy_init,
2564 .reset = usb_phy_reset,
2565 .open = uhsic_phy_open,
2566 .close = uhsic_phy_close,
2567 .irq = uhsic_phy_irq,
2568 .power_on = uhsic_phy_power_on,
2569 .power_off = uhsic_phy_power_off,
2570 .pre_resume = uhsic_phy_pre_resume,
2571 .port_power = uhsic_phy_bus_port_power,
2574 static struct tegra_usb_phy_ops *phy_ops[] = {
2575 [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2576 [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2579 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
2581 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2583 phy->ops = phy_ops[phy->pdata->phy_intf];
2585 /* FIXME: uncommenting below line to make USB host mode fail*/
2586 /* pmc->pmc_ops->power_down_pmc(pmc); */
projects / sojka / nv-tegra / linux-3.10.git / blob