2 * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
5 * High-speed USB device controller driver.
6 * The driver is based on Freescale driver code from Li Yang and Jiang Bo.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/ioport.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/interrupt.h>
25 #include <linux/proc_fs.h>
27 #include <linux/moduleparam.h>
28 #include <linux/device.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/otg.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/platform_device.h>
34 #include <linux/dmapool.h>
35 #include <linux/delay.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/extcon.h>
38 #include <linux/workqueue.h>
39 #include <linux/err.h>
41 #include <linux/pm_qos.h>
42 #include <linux/usb/tegra_usb_phy.h>
43 #include <linux/platform_data/tegra_usb.h>
44 #include <linux/timer.h>
45 #include <linux/tegra-soc.h>
47 #include <asm/byteorder.h>
49 #include <asm/unaligned.h>
52 /* HACK! This needs to come from DT */
53 #include "../../../arch/arm/mach-tegra/iomap.h"
55 #include "tegra_udc.h"
58 #define DRIVER_DESC "Nvidia Tegra High-Speed USB Device Controller driver"
60 #define DRIVER_AUTHOR "Venkat Moganty/Rakesh Bodla"
61 #define DRIVER_VERSION "Apr 30, 2012"
63 #define USB1_PREFETCH_ID 6
65 #define AHB_PREFETCH_BUFFER SZ_128
67 #define get_ep_by_pipe(udc, pipe) ((pipe == 1) ? &udc->eps[0] : \
69 #define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \
70 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
72 #define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF)
73 #define ep_is_in(EP) ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
74 USB_DIR_IN) : ((EP)->desc->bEndpointAddress \
75 & USB_DIR_IN) == USB_DIR_IN)
78 static const char driver_name[] = "tegra-udc";
79 static const char driver_desc[] = DRIVER_DESC;
81 static void tegra_ep_fifo_flush(struct usb_ep *_ep);
82 static int reset_queues(struct tegra_udc *udc);
85 * High speed test mode packet(53 bytes).
86 * See USB 2.0 spec, section 7.1.20.
88 static const u8 tegra_udc_test_packet[53] = {
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
94 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
95 /* JJJJJJJKKKKKKK x8 */
96 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
98 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
99 /* JKKKKKKK x10, JK */
100 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
103 static struct tegra_udc *the_udc;
105 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
106 static struct pm_qos_request boost_cpu_freq_req;
107 static u32 ep_queue_request_count;
108 static u8 boost_cpufreq_work_flag, set_cpufreq_normal_flag;
109 static struct timer_list boost_timer;
110 static bool boost_enable = true;
111 static int boost_enable_set(const char *arg, const struct kernel_param *kp)
113 bool old_boost = boost_enable;
114 int ret = param_set_bool(arg, kp);
115 if (ret == 0 && old_boost && !boost_enable)
116 pm_qos_update_request(&boost_cpu_freq_req,
117 PM_QOS_DEFAULT_VALUE);
120 static int boost_enable_get(char *buffer, const struct kernel_param *kp)
122 return param_get_bool(buffer, kp);
124 static struct kernel_param_ops boost_enable_ops = {
125 .set = boost_enable_set,
126 .get = boost_enable_get,
128 module_param_cb(boost_enable, &boost_enable_ops, &boost_enable, 0644);
131 static char *const tegra_udc_extcon_cable[] = {
132 [CONNECT_TYPE_NONE] = "",
133 [CONNECT_TYPE_SDP] = "USB",
134 [CONNECT_TYPE_DCP] = "TA",
135 [CONNECT_TYPE_DCP_QC2] = "QC2",
136 [CONNECT_TYPE_DCP_MAXIM] = "MAXIM",
137 [CONNECT_TYPE_CDP] = "Charge-downstream",
138 [CONNECT_TYPE_NV_CHARGER] = "Fast-charger",
139 [CONNECT_TYPE_NON_STANDARD_CHARGER] = "Slow-charger",
140 [CONNECT_TYPE_APPLE_500MA] = "Apple 500mA-charger",
141 [CONNECT_TYPE_APPLE_1000MA] = "Apple 1A-charger",
142 [CONNECT_TYPE_APPLE_2000MA] = "Apple 2A-charger",
146 static inline void udc_writel(struct tegra_udc *udc, u32 val, u32 offset)
148 writel(val, udc->regs + offset);
151 static inline unsigned int udc_readl(struct tegra_udc *udc, u32 offset)
153 return readl(udc->regs + offset);
156 /* checks vbus status */
157 static inline bool vbus_enabled(struct tegra_udc *udc)
160 if (tegra_platform_is_fpga()) {
161 /* On FPGA VBUS is detected through VBUS A Session instead
163 status = (udc_readl(udc, VBUS_SENSOR_REG_OFFSET)
164 & USB_SYS_VBUS_ASESSION);
165 } else if (!udc->support_pmu_vbus) {
166 status = (udc_readl(udc, VBUS_WAKEUP_REG_OFFSET)
167 & USB_SYS_VBUS_STATUS);
174 * done() - retire a request; caller blocked irqs
175 * @status : request status to be set, only works when
176 * request is still in progress.
178 static void done(struct tegra_ep *ep, struct tegra_req *req, int status)
180 struct tegra_udc *udc = NULL;
181 unsigned char stopped = ep->stopped;
182 struct ep_td_struct *curr_td, *next_td = 0;
186 BUG_ON(!(in_irq() || irqs_disabled()));
187 udc = (struct tegra_udc *)ep->udc;
188 /* Removed the req from tegra_ep->queue */
189 list_del_init(&req->queue);
191 /* req.status should be set as -EINPROGRESS in ep_queue() */
192 if (req->req.status == -EINPROGRESS)
193 req->req.status = status;
195 status = req->req.status;
197 /* Free dtd for the request */
200 next_td = ep->last_td;
201 count = ep->last_dtd_count;
203 ep->last_td = req->head;
204 ep->last_dtd_count = req->dtd_count;
206 for (j = 0; j < count; j++) {
208 if (j != count - 1) {
209 next_td = curr_td->next_td_virt;
211 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
215 DEFINE_DMA_ATTRS(attrs);
216 struct device *dev = ep->udc->gadget.dev.parent;
217 size_t orig = req->req.length;
218 size_t ext = orig + AHB_PREFETCH_BUFFER;
219 enum dma_data_direction dir =
220 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
222 dma_sync_single_for_cpu(dev, req->req.dma, orig, dir);
223 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
224 dma_unmap_single_attrs(dev, req->req.dma, ext, dir, &attrs);
226 req->req.dma = DMA_ADDR_INVALID;
229 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
230 req->req.dma, req->req.length,
235 if (status && (status != -ESHUTDOWN))
236 VDBG("complete %s req %p stat %d len %u/%u",
237 ep->ep.name, &req->req, status,
238 req->req.actual, req->req.length);
241 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
242 if (req->req.complete && req->req.length >= BOOST_TRIGGER_SIZE)
243 ep_queue_request_count--;
246 /* complete() is from gadget layer,
247 * eg fsg->bulk_in_complete() */
248 if (req->req.complete) {
249 spin_unlock(&ep->udc->lock);
250 req->req.complete(&ep->ep, &req->req);
251 spin_lock(&ep->udc->lock);
254 ep->stopped = stopped;
258 * nuke(): delete all requests related to this ep
259 * Must be called with spinlock held and interrupt disabled
261 static void nuke(struct tegra_ep *ep, int status)
266 tegra_ep_fifo_flush(&ep->ep);
268 /* Whether this eq has request linked */
269 while (!list_empty(&ep->queue)) {
270 struct tegra_req *req = NULL;
272 req = list_entry(ep->queue.next, struct tegra_req, queue);
273 done(ep, req, status);
277 static int can_pullup(struct tegra_udc *udc)
279 DBG("%s(%d) driver = %d softconnect = %d vbus_active = %d\n", __func__,
280 __LINE__, udc->driver ? 1 : 0, udc->softconnect,
282 return udc->driver && udc->softconnect && udc->vbus_active;
285 static int dr_controller_reset(struct tegra_udc *udc)
288 unsigned long timeout;
289 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
291 /* Stop and reset the usb controller */
292 tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
293 tmp &= ~USB_CMD_RUN_STOP;
294 udc_writel(udc, tmp, USB_CMD_REG_OFFSET);
296 tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
297 tmp |= USB_CMD_CTRL_RESET;
298 udc_writel(udc, tmp, USB_CMD_REG_OFFSET);
300 /* Wait for reset to complete */
301 timeout = jiffies + UDC_RESET_TIMEOUT_MS;
302 while (udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_CTRL_RESET) {
303 if (time_after(jiffies, timeout)) {
304 ERR("udc reset timeout!\n");
310 DBG("%s(%d) END\n", __func__, __LINE__);
314 static int dr_controller_setup(struct tegra_udc *udc)
316 unsigned int tmp, portctrl;
317 unsigned long timeout;
319 unsigned int port_control_reg_offset;
320 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
323 port_control_reg_offset = USB_HOSTPCX_DEVLC_REG_OFFSET;
325 port_control_reg_offset = PORTSCX_REG_OFFSET;
327 /* Config PHY interface */
328 portctrl = udc_readl(udc, port_control_reg_offset);
329 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
330 portctrl |= PORTSCX_PTS_UTMI;
331 udc_writel(udc, portctrl, port_control_reg_offset);
333 status = dr_controller_reset(udc);
337 /* Set the controller as device mode */
338 tmp = udc_readl(udc, USB_MODE_REG_OFFSET);
339 tmp |= USB_MODE_CTRL_MODE_DEVICE;
340 /* Disable Setup Lockout */
341 tmp |= USB_MODE_SETUP_LOCK_OFF;
342 udc_writel(udc, tmp, USB_MODE_REG_OFFSET);
344 /* Wait for controller to switch to device mode */
345 timeout = jiffies + UDC_RESET_TIMEOUT_MS;
346 while ((udc_readl(udc, USB_MODE_REG_OFFSET) &
347 USB_MODE_CTRL_MODE_DEVICE) != USB_MODE_CTRL_MODE_DEVICE) {
348 if (time_after(jiffies, timeout)) {
349 ERR("udc device mode setup timeout!\n");
355 /* Clear the setup status */
356 udc_writel(udc, 0, USB_STS_REG_OFFSET);
358 tmp = udc->ep_qh_dma;
359 tmp &= USB_EP_LIST_ADDRESS_MASK;
360 udc_writel(udc, tmp, USB_EP_LIST_ADDRESS_REG_OFFSET);
362 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
363 udc->ep_qh, (int)tmp,
364 udc_readl(udc, USB_EP_LIST_ADDRESS_REG_OFFSET));
366 DBG("%s(%d) END\n", __func__, __LINE__);
370 /* Enable DR irq and set controller to run state */
371 static void dr_controller_run(struct tegra_udc *udc)
374 unsigned long timeout;
375 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
377 /* Clear stopped bit */
380 /* If OTG transceiver is available, then it handles the VBUS detection*/
381 if (!udc->transceiver) {
382 if (tegra_platform_is_fpga()) {
383 /* On FPGA VBUS is detected through VBUS A Session
384 * instead of VBUS status.*/
385 temp = udc_readl(udc, VBUS_SENSOR_REG_OFFSET);
386 temp |= USB_SYS_VBUS_ASESSION_INT_EN;
387 temp &= ~USB_SYS_VBUS_ASESSION_CHANGED;
388 udc_writel(udc, temp, VBUS_SENSOR_REG_OFFSET);
390 /* Enable cable detection interrupt, without setting the
391 * USB_SYS_VBUS_WAKEUP_INT bit. USB_SYS_VBUS_WAKEUP_INT
392 * is clear on write */
393 temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
394 temp |= (USB_SYS_VBUS_WAKEUP_INT_ENABLE
395 | USB_SYS_VBUS_WAKEUP_ENABLE);
396 temp &= ~USB_SYS_VBUS_WAKEUP_INT_STATUS;
397 udc_writel(udc, temp, VBUS_WAKEUP_REG_OFFSET);
400 udc_writel(udc, 0, VBUS_SENSOR_REG_OFFSET);
402 /* Enable DR irq reg */
403 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
404 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
405 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
407 udc_writel(udc, temp, USB_INTR_REG_OFFSET);
409 /* Set the controller as device mode */
410 temp = udc_readl(udc, USB_MODE_REG_OFFSET);
411 temp |= USB_MODE_CTRL_MODE_DEVICE;
412 udc_writel(udc, temp, USB_MODE_REG_OFFSET);
414 if (udc->support_pmu_vbus) {
415 temp = udc_readl(udc, VBUS_SENSOR_REG_OFFSET);
416 temp |= (USB_SYS_VBUS_A_VLD_SW_VALUE |
417 USB_SYS_VBUS_A_VLD_SW_EN |
418 USB_SYS_VBUS_ASESSION_VLD_SW_VALUE |
419 USB_SYS_VBUS_ASESSION_VLD_SW_EN);
420 udc_writel(udc, temp, VBUS_SENSOR_REG_OFFSET);
423 /* set interrupt latency to 125 uS (1 uFrame) */
424 /* Set controller to Run */
425 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
426 temp &= ~USB_CMD_ITC;
427 temp |= USB_CMD_ITC_1_MICRO_FRM;
428 if (can_pullup(udc)) {
429 temp |= USB_CMD_RUN_STOP;
430 if (udc->charging_supported &&
431 (udc->connect_type == CONNECT_TYPE_SDP))
432 schedule_delayed_work(&udc->non_std_charger_work,
433 msecs_to_jiffies(NON_STD_CHARGER_DET_TIME_MS));
436 temp &= ~USB_CMD_RUN_STOP;
437 udc_writel(udc, temp, USB_CMD_REG_OFFSET);
439 if (can_pullup(udc)) {
440 /* Wait for controller to start */
441 timeout = jiffies + UDC_RUN_TIMEOUT_MS;
442 while ((udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_RUN_STOP)
443 != USB_CMD_RUN_STOP) {
444 if (time_after(jiffies, timeout)) {
445 ERR("udc start timeout!\n");
452 DBG("%s(%d) END\n", __func__, __LINE__);
456 static void dr_controller_stop(struct tegra_udc *udc)
459 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
461 /* Clear pending interrupt status bits */
462 tmp = udc_readl(udc, USB_STS_REG_OFFSET);
463 udc_writel(udc, tmp, USB_STS_REG_OFFSET);
465 /* disable all INTR */
466 udc_writel(udc, 0, USB_INTR_REG_OFFSET);
468 /* Set stopped bit for isr */
471 /* set controller to Stop */
472 tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
473 tmp &= ~USB_CMD_RUN_STOP;
474 udc_writel(udc, tmp, USB_CMD_REG_OFFSET);
476 DBG("%s(%d) END\n", __func__, __LINE__);
480 static void dr_ep_setup(struct tegra_udc *udc, unsigned char ep_num,
481 unsigned char dir, unsigned char ep_type)
483 unsigned int tmp_epctrl = 0;
485 tmp_epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
488 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
489 tmp_epctrl |= EPCTRL_TX_ENABLE;
490 tmp_epctrl |= ((unsigned int)(ep_type)
491 << EPCTRL_TX_EP_TYPE_SHIFT);
494 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
495 tmp_epctrl |= EPCTRL_RX_ENABLE;
496 tmp_epctrl |= ((unsigned int)(ep_type)
497 << EPCTRL_RX_EP_TYPE_SHIFT);
500 udc_writel(udc, tmp_epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
503 static void dr_ep_change_stall(struct tegra_udc *udc, unsigned char ep_num,
504 unsigned char dir, int value)
508 tmp_epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
510 /* set the stall bit */
512 tmp_epctrl |= EPCTRL_TX_EP_STALL;
514 tmp_epctrl |= EPCTRL_RX_EP_STALL;
516 /* clear the stall bit and reset data toggle */
518 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
519 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
521 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
522 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
525 udc_writel(udc, tmp_epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
528 /* Get stall status of a specific ep
529 Return: 0: not stalled; 1:stalled */
530 static int dr_ep_get_stall(struct tegra_udc *udc, unsigned char ep_num,
535 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
537 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
539 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
543 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
544 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
547 static void struct_ep_qh_setup(struct tegra_udc *udc, unsigned char ep_num,
548 unsigned char dir, unsigned char ep_type,
549 unsigned int max_pkt_len, unsigned int zlt, unsigned char mult)
551 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
552 unsigned int tmp = 0;
554 /* set the Endpoint Capabilites in QH */
556 case USB_ENDPOINT_XFER_CONTROL:
557 /* Interrupt On Setup (IOS). for control ep */
558 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
561 case USB_ENDPOINT_XFER_ISOC:
562 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
563 | (mult << EP_QUEUE_HEAD_MULT_POS);
565 case USB_ENDPOINT_XFER_BULK:
566 case USB_ENDPOINT_XFER_INT:
567 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
570 VDBG("error ep type is %d", ep_type);
574 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
576 p_QH->max_pkt_length = cpu_to_le32(tmp);
577 p_QH->next_dtd_ptr = 1;
578 p_QH->size_ioc_int_sts = 0;
583 /* Setup qh structure and ep register for ep0. */
584 static void ep0_setup(struct tegra_udc *udc)
586 /* the intialization of an ep includes: fields in QH, Regs,
588 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
589 USB_MAX_CTRL_PAYLOAD, 1, 0);
590 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
591 USB_MAX_CTRL_PAYLOAD, 1, 0);
592 dr_ep_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
593 dr_ep_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
600 * when configurations are set, or when interface settings change
601 * for example the do_set_interface() in gadget layer,
602 * the driver will enable or disable the relevant endpoints
603 * ep0 doesn't use this routine. It is always enabled.
605 static int tegra_ep_enable(struct usb_ep *_ep,
606 const struct usb_endpoint_descriptor *desc)
608 struct tegra_udc *udc = NULL;
609 struct tegra_ep *ep = NULL;
610 unsigned short max = 0;
611 unsigned char mult = 0, zlt;
612 int retval = -EINVAL;
613 unsigned long flags = 0;
615 ep = container_of(_ep, struct tegra_ep, ep);
617 /* catch various bogus parameters */
618 if (!_ep || !desc || ep->desc
619 || (desc->bDescriptorType != USB_DT_ENDPOINT))
624 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
627 max = le16_to_cpu(desc->wMaxPacketSize);
629 /* Disable automatic zlp generation. Driver is responsible to indicate
630 * explicitly through req->req.zero. This is needed to enable multi-td
635 /* Assume the max packet size from gadget is always correct */
636 switch (desc->bmAttributes & 0x03) {
637 case USB_ENDPOINT_XFER_CONTROL:
638 case USB_ENDPOINT_XFER_BULK:
639 case USB_ENDPOINT_XFER_INT:
640 /* mult = 0. Execute N Transactions as demonstrated by
641 * the USB variable length packet protocol where N is
642 * computed using the Maximum Packet Length (dQH) and
643 * the Total Bytes field (dTD) */
646 case USB_ENDPOINT_XFER_ISOC:
647 /* Calculate transactions needed for high bandwidth iso */
648 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
649 max = max & 0x7ff; /* bit 0~10 */
650 /* 3 transactions at most */
658 spin_lock_irqsave(&udc->lock, flags);
659 ep->ep.maxpacket = max;
663 ep->last_dtd_count = 0;
665 /* Controller related setup
666 * Init EPx Queue Head (Ep Capabilites field in QH
667 * according to max, zlt, mult)
669 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
670 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
671 ? USB_SEND : USB_RECV),
672 (unsigned char) (desc->bmAttributes
673 & USB_ENDPOINT_XFERTYPE_MASK),
676 /* Init endpoint ctrl register */
677 dr_ep_setup(udc, (unsigned char) ep_index(ep),
678 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
679 ? USB_SEND : USB_RECV),
680 (unsigned char) (desc->bmAttributes
681 & USB_ENDPOINT_XFERTYPE_MASK));
683 spin_unlock_irqrestore(&udc->lock, flags);
686 VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
687 ep->desc->bEndpointAddress & 0x0f,
688 (desc->bEndpointAddress & USB_DIR_IN)
689 ? "in" : "out", max);
695 * @ep : the ep being unconfigured. May not be ep0
696 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
698 static int tegra_ep_disable(struct usb_ep *_ep)
700 struct tegra_udc *udc = NULL;
701 struct tegra_ep *ep = NULL;
703 unsigned long flags = 0;
706 struct ep_td_struct *curr_td, *next_td;
709 ep = container_of(_ep, struct tegra_ep, ep);
710 if (!_ep || !ep->desc) {
711 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
714 udc = (struct tegra_udc *)ep->udc;
716 /* disable ep on controller */
717 ep_num = ep_index(ep);
719 /* Touch the registers if cable is connected and phy is on */
720 if (udc->vbus_active) {
721 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
723 epctrl &= ~EPCTRL_TX_ENABLE;
725 epctrl &= ~EPCTRL_RX_ENABLE;
726 udc_writel(udc, epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
729 spin_lock_irqsave(&udc->lock, flags);
731 /* nuke all pending requests (does flush) */
732 nuke(ep, -ESHUTDOWN);
737 next_td = ep->last_td;
738 for (j = 0; j < ep->last_dtd_count; j++) {
740 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
741 if (j != ep->last_dtd_count - 1) {
742 next_td = curr_td->next_td_virt;
747 ep->last_dtd_count = 0;
748 spin_unlock_irqrestore(&udc->lock, flags);
750 VDBG("disabled %s OK", _ep->name);
755 * Allocate a request object used by this endpoint
756 * the main operation is to insert the req->queue to the eq->queue
757 * Returns the request, or null if one could not be allocated
759 static struct usb_request *
760 tegra_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
762 struct tegra_req *req = NULL;
764 req = kzalloc(sizeof *req, gfp_flags);
768 req->req.dma = DMA_ADDR_INVALID;
769 INIT_LIST_HEAD(&req->queue);
774 static void tegra_free_request(struct usb_ep *_ep, struct usb_request *_req)
776 struct tegra_req *req = NULL;
778 req = container_of(_req, struct tegra_req, req);
784 static void tegra_queue_td(struct tegra_ep *ep, struct tegra_req *req)
786 int i = ep_index(ep) * 2 + ep_is_in(ep);
787 u32 temp, bitmask, tmp_stat;
788 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
789 struct tegra_udc *udc = ep->udc;
791 bitmask = ep_is_in(ep)
792 ? (1 << (ep_index(ep) + 16))
793 : (1 << (ep_index(ep)));
795 /* Flush all the dTD structs out to memory */
798 /* check if the pipe is empty */
799 if (!(list_empty(&ep->queue))) {
800 /* Add td to the end */
801 struct tegra_req *lastreq;
802 lastreq = list_entry(ep->queue.prev, struct tegra_req, queue);
803 lastreq->tail->next_td_ptr =
804 cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
806 /* Read prime bit, if 1 goto done */
807 if (udc_readl(udc, EP_PRIME_REG_OFFSET) & bitmask)
811 /* Set ATDTW bit in USBCMD */
812 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
813 temp |= USB_CMD_ATDTW;
814 udc_writel(udc, temp, USB_CMD_REG_OFFSET);
816 /* Read correct status bit */
817 tmp_stat = udc_readl(udc, EP_STATUS_REG_OFFSET)
820 } while (!(udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_ATDTW));
822 /* Write ATDTW bit to 0 */
823 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
824 udc_writel(udc, temp & ~USB_CMD_ATDTW, USB_CMD_REG_OFFSET);
830 /* Write dQH next pointer and terminate bit to 0 */
831 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
832 dQH->next_dtd_ptr = cpu_to_le32(temp);
834 /* Clear active and halt bit */
835 temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
836 | EP_QUEUE_HEAD_STATUS_HALT));
837 dQH->size_ioc_int_sts &= temp;
839 tegra_usb_phy_memory_prefetch_on(udc->phy);
841 /* Ensure that updates to the QH will occur before priming. */
844 /* Prime endpoint by writing 1 to ENDPTPRIME */
846 ? (1 << (ep_index(ep) + 16))
847 : (1 << (ep_index(ep)));
848 udc_writel(udc, temp, EP_PRIME_REG_OFFSET);
854 * Fill in the dTD structure
855 * @req : request that the transfer belongs to
856 * @length : return actually data length of the dTD
857 * @dma : return dma address of the dTD
858 * @is_last : return flag if it is the last dTD of the request
859 * return : pointer to the built dTD
861 static struct ep_td_struct *tegra_build_dtd(struct tegra_req *req,
862 unsigned *length, dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
865 struct ep_td_struct *dtd;
867 /* how big will this transfer be? */
868 *length = min(req->req.length - req->req.actual,
869 (unsigned)EP_MAX_LENGTH_TRANSFER);
871 dtd = dma_pool_alloc(the_udc->td_pool, gfp_flags, dma);
876 /* Clear reserved field */
877 swap_temp = cpu_to_le32(dtd->size_ioc_sts);
878 swap_temp &= ~DTD_RESERVED_FIELDS;
879 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
881 /* Init all of buffer page pointers */
882 swap_temp = (u32) (req->req.dma + req->req.actual);
883 dtd->buff_ptr0 = cpu_to_le32(swap_temp);
884 dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
885 dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
886 dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
887 dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
889 req->req.actual += *length;
891 /* zlp is needed if req->req.zero is set */
893 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
897 } else if (req->req.length == req->req.actual)
903 VDBG("multi-dtd request!");
905 /* Fill in the transfer size; set active bit */
906 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
908 /* Enable interrupt for the last dtd of a request */
909 if (*is_last && !req->req.no_interrupt)
910 swap_temp |= DTD_IOC;
912 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
916 VDBG("length = %d address= 0x%x", *length, (int)*dma);
921 /* Generate dtd chain for a request */
922 static int tegra_req_to_dtd(struct tegra_req *req, gfp_t gfp_flags)
927 struct ep_td_struct *last_dtd = NULL, *dtd;
930 tegra_usb_phy_memory_prefetch_off(the_udc->phy);
933 dtd = tegra_build_dtd(req, &count, &dma, &is_last, gfp_flags);
941 last_dtd->next_td_ptr = cpu_to_le32(dma);
942 last_dtd->next_td_virt = dtd;
949 dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
956 /* queues (submits) an I/O request to an endpoint */
958 tegra_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
960 struct tegra_ep *ep = container_of(_ep, struct tegra_ep, ep);
961 struct tegra_req *req = container_of(_req, struct tegra_req, req);
962 struct tegra_udc *udc = ep->udc;
964 enum dma_data_direction dir;
967 /* catch various bogus parameters */
968 if (!_req || !req->req.complete || !req->req.buf
969 || !list_empty(&req->queue)) {
970 VDBG("%s, bad params", __func__);
974 spin_lock_irqsave(&udc->lock, flags);
976 if (unlikely(!ep->desc)) {
977 VDBG("%s, bad ep", __func__);
978 spin_unlock_irqrestore(&udc->lock, flags);
982 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
983 if (req->req.length > ep->ep.maxpacket) {
984 spin_unlock_irqrestore(&udc->lock, flags);
989 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
990 if (req->req.length >= BOOST_TRIGGER_SIZE) {
991 ep_queue_request_count++;
992 schedule_work(&udc->boost_cpufreq_work);
996 dir = ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
998 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
999 spin_unlock_irqrestore(&udc->lock, flags);
1005 /* map virtual address to hardware */
1006 if (req->req.dma == DMA_ADDR_INVALID) {
1007 DEFINE_DMA_ATTRS(attrs);
1008 struct device *dev = udc->gadget.dev.parent;
1009 size_t orig = req->req.length;
1010 size_t ext = orig + AHB_PREFETCH_BUFFER;
1012 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
1013 req->req.dma = dma_map_single_attrs(dev, req->req.buf, ext, dir,
1015 if (dma_mapping_error(dev, req->req.dma)) {
1016 spin_unlock_irqrestore(&udc->lock, flags);
1020 dma_sync_single_for_device(dev, req->req.dma, orig, dir);
1024 dma_sync_single_for_device(udc->gadget.dev.parent,
1025 req->req.dma, req->req.length, dir);
1029 req->req.status = -EINPROGRESS;
1030 req->req.actual = 0;
1034 /* build dtds and push them to device queue */
1035 status = tegra_req_to_dtd(req, GFP_ATOMIC);
1037 spin_unlock_irqrestore(&udc->lock, flags);
1041 /* re-check if the ep has not been disabled */
1042 if (unlikely(!ep->desc)) {
1043 spin_unlock_irqrestore(&udc->lock, flags);
1048 tegra_queue_td(ep, req);
1050 /* Update ep0 state */
1051 if ((ep_index(ep) == 0))
1052 udc->ep0_state = DATA_STATE_XMIT;
1054 /* irq handler advances the queue */
1055 list_add_tail(&req->queue, &ep->queue);
1056 spin_unlock_irqrestore(&udc->lock, flags);
1062 DEFINE_DMA_ATTRS(attrs);
1063 struct device *dev = udc->gadget.dev.parent;
1064 size_t orig = req->req.length;
1065 size_t ext = orig + AHB_PREFETCH_BUFFER;
1067 dma_sync_single_for_cpu(dev, req->req.dma, orig, dir);
1068 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
1069 dma_unmap_single_attrs(dev, req->req.dma, ext, dir, &attrs);
1071 req->req.dma = DMA_ADDR_INVALID;
1077 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
1078 static int tegra_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1080 struct tegra_ep *ep = container_of(_ep, struct tegra_ep, ep);
1081 struct tegra_req *req;
1082 struct tegra_udc *udc = ep->udc;
1083 unsigned long flags;
1084 int ep_num, stopped, ret = 0;
1090 spin_lock_irqsave(&ep->udc->lock, flags);
1092 spin_unlock_irqrestore(&ep->udc->lock, flags);
1095 stopped = ep->stopped;
1097 /* Stop the ep before we deal with the queue */
1099 ep_num = ep_index(ep);
1101 /* Touch the registers if cable is connected and phy is on */
1102 if (udc->vbus_active) {
1103 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1105 epctrl &= ~EPCTRL_TX_ENABLE;
1107 epctrl &= ~EPCTRL_RX_ENABLE;
1108 udc_writel(udc, epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1111 /* make sure it's actually queued on this endpoint */
1112 list_for_each_entry(req, &ep->queue, queue) {
1113 if (&req->req == _req)
1116 if (&req->req != _req) {
1121 /* The request is in progress, or completed but not dequeued */
1122 if (ep->queue.next == &req->queue) {
1123 _req->status = -ECONNRESET;
1124 tegra_ep_fifo_flush(_ep); /* flush current transfer */
1126 /* The request isn't the last request in this ep queue */
1127 if (req->queue.next != &ep->queue) {
1128 struct ep_queue_head *qh;
1129 struct tegra_req *next_req;
1132 next_req = list_entry(req->queue.next, struct tegra_req,
1135 /* Point the QH to the first TD of next request */
1136 writel((u32) (uintptr_t) next_req->head,
1140 /* The request hasn't been processed, patch up the TD chain */
1142 struct tegra_req *prev_req;
1144 prev_req = list_entry(req->queue.prev, struct tegra_req, queue);
1145 writel(readl(&req->tail->next_td_ptr),
1146 &prev_req->tail->next_td_ptr);
1149 done(ep, req, -ECONNRESET);
1153 /* Touch the registers if cable is connected and phy is on */
1154 if (udc->vbus_active && ep->desc) {
1155 epctrl = udc_readl(udc, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1157 epctrl |= EPCTRL_TX_ENABLE;
1159 epctrl |= EPCTRL_RX_ENABLE;
1160 udc_writel(udc, epctrl, EP_CONTROL_REG_OFFSET + (ep_num * 4));
1162 ep->stopped = stopped;
1164 spin_unlock_irqrestore(&ep->udc->lock, flags);
1169 * modify the endpoint halt feature
1170 * @ep: the non-isochronous endpoint being stalled
1171 * @value: 1--set halt 0--clear halt
1172 * Returns zero, or a negative error code.
1174 static int tegra_ep_set_halt(struct usb_ep *_ep, int value)
1176 struct tegra_ep *ep = NULL;
1177 unsigned long flags = 0;
1178 int status = -EOPNOTSUPP; /* operation not supported */
1179 unsigned char ep_dir = 0, ep_num = 0;
1180 struct tegra_udc *udc = NULL;
1182 ep = container_of(_ep, struct tegra_ep, ep);
1184 if (!_ep || !ep->desc) {
1189 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1190 status = -EOPNOTSUPP;
1194 /* Attempt to halt IN ep will fail if any transfer requests
1195 * are still queue */
1196 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1202 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1203 ep_num = (unsigned char)(ep_index(ep));
1204 spin_lock_irqsave(&ep->udc->lock, flags);
1205 dr_ep_change_stall(udc, ep_num, ep_dir, value);
1206 spin_unlock_irqrestore(&ep->udc->lock, flags);
1208 if (ep_index(ep) == 0) {
1209 udc->ep0_state = WAIT_FOR_SETUP;
1213 VDBG(" %s %s halt stat %d", ep->ep.name,
1214 value ? "set" : "clear", status);
1219 static int tegra_ep_fifo_status(struct usb_ep *_ep)
1221 struct tegra_ep *ep;
1222 struct tegra_udc *udc;
1225 struct ep_queue_head *d_qh;
1227 ep = container_of(_ep, struct tegra_ep, ep);
1228 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1231 udc = (struct tegra_udc *)ep->udc;
1233 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1236 d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1238 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1239 (1 << (ep_index(ep)));
1241 if (udc_readl(udc, EP_STATUS_REG_OFFSET) & bitmask)
1242 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1243 >> DTD_LENGTH_BIT_POS;
1245 pr_debug("%s %u\n", __func__, size);
1249 static void tegra_ep_fifo_flush(struct usb_ep *_ep)
1251 struct tegra_ep *ep;
1252 struct tegra_udc *udc;
1255 unsigned long timeout;
1260 ep = container_of(_ep, struct tegra_ep, ep);
1264 ep_num = ep_index(ep);
1265 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1269 bits = (1 << 16) | 1;
1270 else if (ep_dir == USB_SEND)
1271 bits = 1 << (16 + ep_num);
1275 /* Touch the registers if cable is connected and phy is on */
1276 if (!udc->vbus_active)
1279 timeout = jiffies + UDC_FLUSH_TIMEOUT_MS;
1281 udc_writel(udc, bits, EPFLUSH_REG_OFFSET);
1283 /* Wait until flush complete */
1284 while (udc_readl(udc, EPFLUSH_REG_OFFSET)) {
1285 if (time_after(jiffies, timeout)) {
1286 ERR("ep flush timeout\n");
1291 /* See if we need to flush again */
1292 } while (udc_readl(udc, EP_STATUS_REG_OFFSET) & bits);
1295 static struct usb_ep_ops tegra_ep_ops = {
1296 .enable = tegra_ep_enable,
1297 .disable = tegra_ep_disable,
1299 .alloc_request = tegra_alloc_request,
1300 .free_request = tegra_free_request,
1302 .queue = tegra_ep_queue,
1303 .dequeue = tegra_ep_dequeue,
1305 .set_halt = tegra_ep_set_halt,
1306 .fifo_status = tegra_ep_fifo_status,
1307 .fifo_flush = tegra_ep_fifo_flush, /* flush fifo */
1311 static struct usb_phy *get_usb_phy(struct tegra_usb_phy *x)
1313 return (struct usb_phy *)x;
1316 /* Get the current frame number (from DR frame_index Reg ) */
1317 static int tegra_get_frame(struct usb_gadget *gadget)
1319 struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1320 return (int)(udc_readl(udc, USB_FRINDEX_REG_OFFSET)
1321 & USB_FRINDEX_MASKS);
1324 #ifndef CONFIG_USB_ANDROID
1325 /* Tries to wake up the host connected to this gadget */
1326 static int tegra_wakeup(struct usb_gadget *gadget)
1328 struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1331 /* Remote wakeup feature not enabled by host */
1332 if (!udc->remote_wakeup)
1335 portsc = udc_readl(udc, PORTSCX_REG_OFFSET);
1336 /* not suspended? */
1337 if (!(portsc & PORTSCX_PORT_SUSPEND))
1340 /* trigger force resume */
1341 portsc |= PORTSCX_PORT_FORCE_RESUME;
1342 udc_writel(udc, portsc, PORTSCX_REG_OFFSET);
1347 static int tegra_set_selfpowered(struct usb_gadget *gadget, int is_on)
1349 struct tegra_udc *udc;
1350 udc = container_of(gadget, struct tegra_udc, gadget);
1351 udc->selfpowered = (is_on != 0);
1355 static void tegra_udc_set_charger_type(struct tegra_udc *udc,
1356 enum tegra_connect_type type)
1358 udc->prev_connect_type = udc->connect_type;
1359 udc->connect_type = type;
1362 static void tegra_udc_set_extcon_state(struct tegra_udc *udc)
1364 const char **cables;
1365 struct extcon_dev *edev;
1367 if (udc->edev == NULL || udc->edev->supported_cable == NULL)
1370 cables = udc->edev->supported_cable;
1371 /* set previous cable type to false, then set current type to true */
1372 if (udc->prev_connect_type != CONNECT_TYPE_NONE)
1373 extcon_set_state(edev, 0x0);
1374 if (udc->connect_type != udc->connect_type_lp0
1375 && udc->connect_type != CONNECT_TYPE_NONE)
1376 extcon_set_cable_state(edev, cables[udc->connect_type], true);
1379 static void tegra_udc_notify_event(struct tegra_udc *udc, int event)
1381 if (udc->transceiver) {
1382 udc->transceiver->last_event = event;
1383 atomic_notifier_call_chain(&udc->transceiver->notifier,
1384 event, udc->transceiver->otg->gadget);
1388 static int tegra_usb_set_charging_current(struct tegra_udc *udc)
1394 dev = &udc->pdev->dev;
1395 switch (udc->connect_type) {
1396 case CONNECT_TYPE_NONE:
1397 dev_info(dev, "USB cable/charger disconnected\n");
1399 /* Notify if HOST(SDP/CDP) is connected */
1400 if ((udc->prev_connect_type == CONNECT_TYPE_SDP) ||
1401 (udc->prev_connect_type == CONNECT_TYPE_CDP))
1402 tegra_udc_notify_event(udc, USB_EVENT_NONE);
1404 case CONNECT_TYPE_SDP:
1405 if (udc->current_limit > 2)
1406 dev_info(dev, "connected to SDP\n");
1407 max_ua = min(udc->current_limit * 1000,
1408 USB_CHARGING_SDP_CURRENT_LIMIT_UA);
1409 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1411 case CONNECT_TYPE_DCP:
1412 dev_info(dev, "connected to DCP(wall charger)\n");
1413 max_ua = udc->dcp_current_limit;
1414 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1416 case CONNECT_TYPE_DCP_QC2:
1417 dev_info(dev, "connected to QuickCharge 2(wall charger)\n");
1418 max_ua = udc->qc2_current_limit;
1419 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1421 case CONNECT_TYPE_DCP_MAXIM:
1422 dev_info(dev, "connected to Maxim(wall charger)\n");
1423 max_ua = udc->dcp_current_limit;
1424 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1426 case CONNECT_TYPE_CDP:
1427 dev_info(dev, "connected to CDP(1.5A)\n");
1429 * if current is more than VBUS suspend current, we draw CDP
1430 * allowed maximum current (override SDP max current which is
1431 * set by the upper level driver).
1433 if (udc->current_limit > 2)
1434 max_ua = USB_CHARGING_CDP_CURRENT_LIMIT_UA;
1436 max_ua = udc->current_limit * 1000;
1437 tegra_udc_notify_event(udc, USB_EVENT_VBUS);
1439 case CONNECT_TYPE_NV_CHARGER:
1440 dev_info(dev, "connected to NV charger\n");
1441 max_ua = USB_CHARGING_NV_CHARGER_CURRENT_LIMIT_UA;
1442 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1444 case CONNECT_TYPE_NON_STANDARD_CHARGER:
1445 dev_info(dev, "connected to non-standard charger\n");
1446 max_ua = USB_CHARGING_NON_STANDARD_CHARGER_CURRENT_LIMIT_UA;
1447 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1449 case CONNECT_TYPE_APPLE_500MA:
1450 dev_info(dev, "connected to Apple/Other 0.5A custom charger\n");
1451 max_ua = USB_CHARGING_APPLE_CHARGER_500mA_CURRENT_LIMIT_UA;
1452 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1454 case CONNECT_TYPE_APPLE_1000MA:
1455 dev_info(dev, "connected to Apple/Other 1A custom charger\n");
1456 max_ua = USB_CHARGING_APPLE_CHARGER_1000mA_CURRENT_LIMIT_UA;
1457 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1459 case CONNECT_TYPE_APPLE_2000MA:
1460 dev_info(dev, "connected to Apple/Other/NV 2A custom charger\n");
1461 max_ua = USB_CHARGING_APPLE_CHARGER_2000mA_CURRENT_LIMIT_UA;
1462 tegra_udc_notify_event(udc, USB_EVENT_CHARGER);
1465 dev_info(dev, "connected to unknown USB port\n");
1471 * we set charging regulator's maximum charging current 1st, then
1472 * notify the charging type.
1474 if (NULL != udc->vbus_reg && !udc->vbus_in_lp0) {
1475 if (udc->connect_type != udc->connect_type_lp0 ||
1476 udc->connect_type == CONNECT_TYPE_NONE)
1477 ret = regulator_set_current_limit(udc->vbus_reg,
1481 if (!udc->vbus_in_lp0) {
1482 tegra_udc_set_extcon_state(udc);
1483 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
1488 static int tegra_detect_cable_type(struct tegra_udc *udc)
1490 if (!udc->charging_supported) {
1491 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1495 if (tegra_usb_phy_charger_detected(udc->phy)) {
1496 if (tegra_usb_phy_cdp_charger_detected(udc->phy))
1497 tegra_udc_set_charger_type(udc, CONNECT_TYPE_CDP);
1498 else if (tegra_usb_phy_maxim_charger_detected(udc->phy))
1499 tegra_udc_set_charger_type(udc,
1500 CONNECT_TYPE_DCP_MAXIM);
1501 else if (udc->qc2_voltage) {
1502 /* Must be DCP -- figure out if Quick Charge 2 or DCP.
1503 * Initially set low current since QC2 will reset to
1504 * 5V if current is too high when it changes to higher
1505 * voltage during detection. So setting to non-standard
1506 * which sets for low current. Also, setting current
1507 * early allows the charging icon to show up on UI.
1509 tegra_udc_set_charger_type(udc,
1510 CONNECT_TYPE_NON_STANDARD_CHARGER);
1511 tegra_usb_set_charging_current(udc);
1513 if (tegra_usb_phy_qc2_charger_detected(udc->phy,
1515 tegra_udc_set_charger_type(udc,
1516 CONNECT_TYPE_DCP_QC2);
1518 tegra_udc_set_charger_type(udc,
1521 tegra_udc_set_charger_type(udc, CONNECT_TYPE_DCP);
1523 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
1524 else if (tegra_usb_phy_apple_500ma_charger_detected(udc->phy))
1525 tegra_udc_set_charger_type(udc, CONNECT_TYPE_APPLE_500MA);
1526 else if (tegra_usb_phy_apple_1000ma_charger_detected(udc->phy))
1527 tegra_udc_set_charger_type(udc, CONNECT_TYPE_APPLE_1000MA);
1528 else if (tegra_usb_phy_apple_2000ma_charger_detected(udc->phy))
1529 tegra_udc_set_charger_type(udc, CONNECT_TYPE_APPLE_2000MA);
1531 else if (tegra_usb_phy_nv_charger_detected(udc->phy))
1532 tegra_udc_set_charger_type(udc, CONNECT_TYPE_NV_CHARGER);
1534 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1537 * If it is charger type, we start charging now. If it is connected to
1538 * USB host(CDP/SDP), we let upper gadget driver to decide the current
1541 if ((udc->connect_type != CONNECT_TYPE_SDP) &&
1542 (udc->connect_type != CONNECT_TYPE_CDP))
1543 tegra_usb_set_charging_current(udc);
1549 * Notify controller that VBUS is powered, called by whatever
1550 * detects VBUS sessions
1552 static int tegra_vbus_session(struct usb_gadget *gadget, int is_active)
1554 struct tegra_udc *udc = container_of(gadget, struct tegra_udc, gadget);
1555 unsigned long flags;
1557 mutex_lock(&udc->sync_lock);
1558 DBG("%s(%d) turn VBUS state from %s to %s", __func__, __LINE__,
1559 udc->vbus_active ? "on" : "off", is_active ? "on" : "off");
1561 if (udc->vbus_active && !is_active) {
1562 /* If cable disconnected, cancel any delayed work */
1563 cancel_delayed_work_sync(&udc->non_std_charger_work);
1564 spin_lock_irqsave(&udc->lock, flags);
1565 /* reset all internal Queues and inform client driver */
1567 /* stop the controller and turn off the clocks */
1568 dr_controller_stop(udc);
1569 dr_controller_reset(udc);
1570 udc->vbus_active = 0;
1571 udc->usb_state = USB_STATE_DEFAULT;
1572 tegra_udc_set_charger_type(udc, CONNECT_TYPE_NONE);
1573 spin_unlock_irqrestore(&udc->lock, flags);
1574 tegra_usb_phy_power_off(udc->phy);
1575 tegra_usb_set_charging_current(udc);
1576 udc->current_limit = 0;
1577 } else if (!udc->vbus_active && is_active) {
1578 tegra_usb_phy_power_on(udc->phy);
1579 /* setup the controller in the device mode */
1580 dr_controller_setup(udc);
1581 /* setup EP0 for setup packet */
1583 /* initialize the USB and EP states */
1584 udc->usb_state = USB_STATE_ATTACHED;
1585 udc->ep0_state = WAIT_FOR_SETUP;
1587 udc->vbus_active = 1;
1588 tegra_detect_cable_type(udc);
1589 /* start the controller if USB host detected */
1590 if ((udc->connect_type == CONNECT_TYPE_SDP) ||
1591 (udc->connect_type == CONNECT_TYPE_CDP) ||
1592 (udc->connect_type == CONNECT_TYPE_DCP_MAXIM))
1593 dr_controller_run(udc);
1595 mutex_unlock(&udc->sync_lock);
1601 * Constrain controller's VBUS power usage.
1602 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1603 * reporting how much power the device may consume. For example, this
1604 * could affect how quickly batteries are recharged.
1606 * Returns zero on success, else negative errno.
1608 static int tegra_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1610 struct tegra_udc *udc;
1612 udc = container_of(gadget, struct tegra_udc, gadget);
1614 /* Some hosts during booting first supply vbus and then
1615 send setup packets after x seconds. In this case we detect
1616 as non-standard. Handle this case by setting to SDP */
1617 if (udc->connect_type != CONNECT_TYPE_NONE
1618 && udc->connect_type != CONNECT_TYPE_SDP
1619 && udc->connect_type != CONNECT_TYPE_CDP)
1620 tegra_udc_set_charger_type(udc, CONNECT_TYPE_SDP);
1622 /* Avoid unnecessary work if there is no change in current limit */
1623 if (udc->current_limit != mA) {
1624 udc->current_limit = mA;
1625 schedule_work(&udc->current_work);
1628 if (udc->transceiver)
1629 return usb_phy_set_power(udc->transceiver, mA);
1634 * Change Data+ pullup status
1635 * this func is used by usb_gadget_connect/disconnect
1637 static int tegra_pullup(struct usb_gadget *gadget, int is_on)
1639 struct tegra_udc *udc;
1641 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
1643 udc = container_of(gadget, struct tegra_udc, gadget);
1644 udc->softconnect = (is_on != 0);
1645 if (udc->transceiver && udc->transceiver->state !=
1646 OTG_STATE_B_PERIPHERAL)
1649 /* set interrupt latency to 125 uS (1 uFrame) */
1650 tmp = udc_readl(udc, USB_CMD_REG_OFFSET);
1651 tmp &= ~USB_CMD_ITC;
1652 tmp |= USB_CMD_ITC_1_MICRO_FRM;
1653 if (can_pullup(udc)) {
1654 udc_writel(udc, tmp | USB_CMD_RUN_STOP, USB_CMD_REG_OFFSET);
1656 * We cannot tell difference between a SDP and non-standard
1657 * charger (which has D+/D- line floating) based on line status
1658 * at the time VBUS is detected.
1660 * We can schedule a 4s delayed work and verify it is an
1661 * non-standard charger if no setup packet is received after
1662 * enumeration started.
1664 if (udc->charging_supported &&
1665 (udc->connect_type == CONNECT_TYPE_SDP))
1666 schedule_delayed_work(&udc->non_std_charger_work,
1667 msecs_to_jiffies(NON_STD_CHARGER_DET_TIME_MS));
1669 cancel_delayed_work(&udc->non_std_charger_work);
1670 udc_writel(udc, (tmp & ~USB_CMD_RUN_STOP), USB_CMD_REG_OFFSET);
1673 DBG("%s(%d) END\n", __func__, __LINE__);
1677 /* Release udc structures */
1678 static void tegra_udc_release(struct device *dev)
1680 struct platform_device *pdev = to_platform_device(dev);
1681 struct tegra_udc *udc = platform_get_drvdata(pdev);
1683 complete(udc->done);
1684 usb_phy_shutdown(get_usb_phy(udc->phy));
1688 static int tegra_udc_start(struct usb_gadget *g,
1689 struct usb_gadget_driver *driver);
1690 static int tegra_udc_stop(struct usb_gadget *g,
1691 struct usb_gadget_driver *driver);
1692 /* defined in gadget.h */
1693 static const struct usb_gadget_ops tegra_gadget_ops = {
1694 .get_frame = tegra_get_frame,
1695 #ifndef CONFIG_USB_ANDROID
1696 .wakeup = tegra_wakeup,
1698 .set_selfpowered = tegra_set_selfpowered,
1699 .vbus_session = tegra_vbus_session,
1700 .vbus_draw = tegra_vbus_draw,
1701 .pullup = tegra_pullup,
1702 .udc_start = tegra_udc_start,
1703 .udc_stop = tegra_udc_stop,
1707 * Set protocol stall on ep0, protocol stall will automatically be cleared
1708 * on new transaction.
1710 static void ep0stall(struct tegra_udc *udc)
1714 /* must set tx and rx to stall at the same time */
1715 tmp = udc_readl(udc, EP_CONTROL_REG_OFFSET);
1716 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1717 udc_writel(udc, tmp, EP_CONTROL_REG_OFFSET);
1718 udc->ep0_state = WAIT_FOR_SETUP;
1722 /* Prime a status phase for ep0 */
1723 static int ep0_prime_status(struct tegra_udc *udc, int direction)
1725 struct tegra_req *req = udc->status_req;
1726 struct tegra_ep *ep;
1728 if (direction == EP_DIR_IN)
1729 udc->ep0_dir = USB_DIR_IN;
1731 udc->ep0_dir = USB_DIR_OUT;
1734 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1737 req->req.length = 0;
1738 req->req.status = -EINPROGRESS;
1739 req->req.actual = 0;
1740 req->req.complete = NULL;
1743 if (tegra_req_to_dtd(req, GFP_ATOMIC) == 0)
1744 tegra_queue_td(ep, req);
1748 list_add_tail(&req->queue, &ep->queue);
1753 static void udc_reset_ep_queue(struct tegra_udc *udc, u8 pipe)
1755 struct tegra_ep *ep = get_ep_by_pipe(udc, pipe);
1758 nuke(ep, -ESHUTDOWN);
1761 /* ch9 Set address */
1762 static void ch9setaddress(struct tegra_udc *udc, u16 value, u16 index,
1765 /* Save the new address to device struct */
1766 udc->device_address = (u8) value;
1767 /* Update usb state */
1768 udc->usb_state = USB_STATE_ADDRESS;
1770 if (ep0_prime_status(udc, EP_DIR_IN))
1774 /* ch9 Get status */
1775 static void ch9getstatus(struct tegra_udc *udc, u8 request_type, u16 value,
1776 u16 index, u16 length)
1778 u16 tmp = 0; /* Status, cpu endian */
1779 struct tegra_req *req;
1780 struct tegra_ep *ep;
1784 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1785 /* Get device status */
1786 if (udc->selfpowered)
1787 tmp = 1 << USB_DEVICE_SELF_POWERED;
1788 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1789 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1790 /* Get interface status
1791 * We don't have interface information in udc driver */
1793 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1794 /* Get endpoint status */
1795 struct tegra_ep *target_ep;
1797 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1799 /* stall if endpoint doesn't exist */
1800 if (!target_ep->desc)
1802 tmp = dr_ep_get_stall(udc, ep_index(target_ep),
1803 ep_is_in(target_ep)) << USB_ENDPOINT_HALT;
1806 udc->ep0_dir = USB_DIR_IN;
1807 /* Borrow the per device status_req */
1808 req = udc->status_req;
1809 /* Fill in the reqest structure */
1810 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1812 req->req.length = 2;
1813 req->req.status = -EINPROGRESS;
1814 req->req.actual = 0;
1815 req->req.complete = NULL;
1818 /* map virtual address to hardware */
1819 if (req->req.dma == DMA_ADDR_INVALID) {
1820 DEFINE_DMA_ATTRS(attrs);
1821 struct device *dev = ep->udc->gadget.dev.parent;
1822 size_t orig = req->req.length;
1823 size_t ext = orig + AHB_PREFETCH_BUFFER;
1824 enum dma_data_direction dir =
1825 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1827 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
1828 req->req.dma = dma_map_single_attrs(dev, req->req.buf, ext, dir,
1830 if (dma_mapping_error(dev, req->req.dma))
1833 dma_sync_single_for_device(dev, req->req.dma, orig, dir);
1837 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1838 req->req.dma, req->req.length,
1845 /* prime the data phase */
1846 if ((tegra_req_to_dtd(req, GFP_ATOMIC) == 0))
1847 tegra_queue_td(ep, req);
1851 list_add_tail(&req->queue, &ep->queue);
1852 udc->ep0_state = DATA_STATE_XMIT;
1858 static void udc_test_mode(struct tegra_udc *udc, u32 test_mode)
1860 struct tegra_req *req = NULL;
1861 struct tegra_ep *ep;
1862 u32 portsc, bitmask;
1863 unsigned long timeout;
1865 /* Ack the ep0 IN */
1866 if (ep0_prime_status(udc, EP_DIR_IN))
1871 bitmask = ep_is_in(ep)
1872 ? (1 << (ep_index(ep) + 16))
1873 : (1 << (ep_index(ep)));
1875 timeout = jiffies + HZ;
1876 /* Wait until ep0 IN endpoint txfr is complete */
1877 while (!(udc_readl(udc, EP_COMPLETE_REG_OFFSET) & bitmask)) {
1878 if (time_after(jiffies, timeout)) {
1879 pr_err("Timeout for Ep0 IN Ack\n");
1885 switch (test_mode << PORTSCX_PTC_BIT_POS) {
1886 case PORTSCX_PTC_JSTATE:
1887 udc->current_limit = USB_CHARGING_TEST_MODE_CURRENT_LIMIT_MA;
1888 schedule_work(&udc->current_work);
1891 case PORTSCX_PTC_KSTATE:
1892 udc->current_limit = USB_CHARGING_TEST_MODE_CURRENT_LIMIT_MA;
1893 schedule_work(&udc->current_work);
1896 case PORTSCX_PTC_SEQNAK:
1897 udc->current_limit = USB_CHARGING_TEST_MODE_CURRENT_LIMIT_MA;
1898 schedule_work(&udc->current_work);
1899 VDBG("TEST_SE0_NAK\n");
1901 case PORTSCX_PTC_PACKET:
1902 VDBG("TEST_PACKET\n");
1904 /* get the ep and configure for IN direction */
1906 udc->ep0_dir = USB_DIR_IN;
1908 /* Initialize ep0 status request structure */
1909 req = container_of(tegra_alloc_request(NULL, GFP_ATOMIC),
1910 struct tegra_req, req);
1911 /* allocate a small amount of memory to get valid address */
1912 req->req.buf = kmalloc(sizeof(tegra_udc_test_packet),
1914 req->req.dma = virt_to_phys(req->req.buf);
1916 /* Fill in the reqest structure */
1917 memcpy(req->req.buf, tegra_udc_test_packet,
1918 sizeof(tegra_udc_test_packet));
1920 req->req.length = sizeof(tegra_udc_test_packet);
1921 req->req.status = -EINPROGRESS;
1922 req->req.actual = 0;
1923 req->req.complete = NULL;
1927 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1928 req->req.dma, req->req.length,
1933 /* prime the data phase */
1934 if ((tegra_req_to_dtd(req, GFP_ATOMIC) == 0))
1935 tegra_queue_td(ep, req);
1939 list_add_tail(&req->queue, &ep->queue);
1940 udc->ep0_state = DATA_STATE_XMIT;
1942 case PORTSCX_PTC_FORCE_EN:
1943 VDBG("TEST_FORCE_EN\n");
1946 ERR("udc unknown test mode[%d]!\n", test_mode);
1950 /* read the portsc register */
1951 portsc = udc_readl(udc, PORTSCX_REG_OFFSET);
1952 /* set the test mode selector */
1953 portsc |= test_mode << PORTSCX_PTC_BIT_POS;
1954 udc_writel(udc, portsc, PORTSCX_REG_OFFSET);
1957 * The device must have its power cycled to exit test mode.
1958 * See USB 2.0 spec, section 9.4.9 for test modes operation
1960 * See USB 2.0 spec, section 7.1.20 for test modes.
1962 pr_info("udc entering the test mode, power cycle to exit test mode\n");
1967 kfree(req->req.buf);
1968 tegra_free_request(NULL, &req->req);
1972 static void setup_received_irq(struct tegra_udc *udc,
1973 struct usb_ctrlrequest *setup)
1975 u16 wValue = le16_to_cpu(setup->wValue);
1976 u16 wIndex = le16_to_cpu(setup->wIndex);
1977 u16 wLength = le16_to_cpu(setup->wLength);
1979 udc_reset_ep_queue(udc, 0);
1981 /* We process some stardard setup requests here */
1982 switch (setup->bRequest) {
1983 case USB_REQ_GET_STATUS:
1984 /* Data+Status phase from udc */
1985 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1986 != (USB_DIR_IN | USB_TYPE_STANDARD))
1988 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1991 case USB_REQ_SET_ADDRESS:
1992 /* Status phase from udc */
1993 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1994 | USB_RECIP_DEVICE))
1996 /* This delay is necessary for some windows drivers to
1997 * properly recognize the device */
1999 ch9setaddress(udc, wValue, wIndex, wLength);
2002 case USB_REQ_CLEAR_FEATURE:
2003 case USB_REQ_SET_FEATURE:
2004 /* Status phase from udc */
2006 int rc = -EOPNOTSUPP;
2008 if (setup->bRequestType == USB_RECIP_DEVICE &&
2009 wValue == USB_DEVICE_TEST_MODE) {
2011 * If the feature selector is TEST_MODE, then the most
2012 * significant byte of wIndex is used to specify the
2013 * specific test mode and the lower byte of wIndex must
2016 udc_test_mode(udc, wIndex >> 8);
2019 } else if ((setup->bRequestType &
2020 (USB_RECIP_MASK | USB_TYPE_MASK)) ==
2021 (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2022 int pipe = get_pipe_by_windex(wIndex);
2023 struct tegra_ep *ep;
2025 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
2027 ep = get_ep_by_pipe(udc, pipe);
2029 spin_unlock(&udc->lock);
2030 rc = tegra_ep_set_halt(&ep->ep,
2031 (setup->bRequest == USB_REQ_SET_FEATURE)
2033 spin_lock(&udc->lock);
2035 } else if ((setup->bRequestType & (USB_RECIP_MASK
2036 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2037 | USB_TYPE_STANDARD)) {
2038 /* Note: The driver has not include OTG support yet.
2039 * This will be set when OTG support is added */
2040 if (!gadget_is_otg(&udc->gadget))
2042 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
2043 udc->gadget.b_hnp_enable = 1;
2044 else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2045 udc->gadget.a_hnp_support = 1;
2046 else if (setup->bRequest ==
2047 USB_DEVICE_A_ALT_HNP_SUPPORT)
2048 udc->gadget.a_alt_hnp_support = 1;
2056 if (ep0_prime_status(udc, EP_DIR_IN))
2066 /* Requests handled by gadget */
2068 /* Data phase from gadget, status phase from udc */
2069 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2070 ? USB_DIR_IN : USB_DIR_OUT;
2071 spin_unlock(&udc->lock);
2072 if (udc->driver && udc->driver->setup(&udc->gadget,
2073 &udc->local_setup_buff) < 0)
2075 spin_lock(&udc->lock);
2076 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
2077 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2079 /* No data phase, IN status from gadget */
2080 udc->ep0_dir = USB_DIR_IN;
2081 spin_unlock(&udc->lock);
2082 if (udc->driver && udc->driver->setup(&udc->gadget,
2083 &udc->local_setup_buff) < 0)
2085 spin_lock(&udc->lock);
2086 udc->ep0_state = WAIT_FOR_OUT_STATUS;
2090 /* Process request for Data or Status phase of ep0
2091 * prime status phase if needed */
2092 static void ep0_req_complete(struct tegra_udc *udc, struct tegra_ep *ep0,
2093 struct tegra_req *req)
2095 if (udc->usb_state == USB_STATE_ADDRESS) {
2096 /* Set the new address */
2097 u32 new_address = (u32) udc->device_address;
2098 udc_writel(udc, new_address << USB_DEVICE_ADDRESS_BIT_POS,
2099 USB_DEVICE_ADDR_REG_OFFSET);
2104 switch (udc->ep0_state) {
2105 case DATA_STATE_XMIT:
2106 /* receive status phase */
2107 if (ep0_prime_status(udc, EP_DIR_OUT))
2110 case DATA_STATE_RECV:
2111 /* send status phase */
2112 if (ep0_prime_status(udc, EP_DIR_IN))
2115 case WAIT_FOR_OUT_STATUS:
2116 udc->ep0_state = WAIT_FOR_SETUP;
2118 case WAIT_FOR_SETUP:
2119 ERR("Unexpect ep0 packets\n");
2127 /* Tripwire mechanism to ensure a setup packet payload is extracted without
2128 * being corrupted by another incoming setup packet */
2129 static void tripwire_handler(struct tegra_udc *udc, u8 ep_num, u8 *buffer_ptr)
2132 struct ep_queue_head *qh;
2134 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
2136 /* Clear bit in ENDPTSETUPSTAT */
2137 temp = udc_readl(udc, EP_SETUP_STATUS_REG_OFFSET);
2138 udc_writel(udc, temp | (1 << ep_num), EP_SETUP_STATUS_REG_OFFSET);
2140 /* while a hazard exists when setup package arrives */
2142 /* Set Setup Tripwire */
2143 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
2144 udc_writel(udc, temp | USB_CMD_SUTW, USB_CMD_REG_OFFSET);
2146 /* Copy the setup packet to local buffer */
2147 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
2148 } while (!(udc_readl(udc, USB_CMD_REG_OFFSET) & USB_CMD_SUTW));
2150 /* Clear Setup Tripwire */
2151 temp = udc_readl(udc, USB_CMD_REG_OFFSET);
2152 udc_writel(udc, temp & ~USB_CMD_SUTW, USB_CMD_REG_OFFSET);
2155 /* process-ep_req(): free the completed Tds for this req */
2156 static int process_ep_req(struct tegra_udc *udc, int pipe,
2157 struct tegra_req *curr_req)
2159 struct ep_td_struct *curr_td;
2160 int td_complete, actual, remaining_length, j, tmp;
2163 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
2164 int direction = pipe % 2;
2166 curr_td = curr_req->head;
2168 actual = curr_req->req.length;
2170 for (j = 0; j < curr_req->dtd_count; j++) {
2171 /* Fence read for coherency of AHB master intiated writes */
2172 if (udc->fence_read)
2173 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
2175 dma_sync_single_for_cpu(udc->gadget.dev.parent, curr_td->td_dma,
2176 sizeof(struct ep_td_struct), DMA_FROM_DEVICE);
2178 remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
2180 >> DTD_LENGTH_BIT_POS;
2181 actual -= remaining_length;
2182 errors = le32_to_cpu(curr_td->size_ioc_sts);
2183 if (errors & DTD_ERROR_MASK) {
2184 if (errors & DTD_STATUS_HALTED) {
2185 ERR("dTD error %08x QH=%d\n", errors, pipe);
2186 /* Clear the errors and Halt condition */
2187 tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
2189 curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
2191 /* FIXME: continue with next queued TD? */
2195 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
2196 VDBG("Transfer overflow");
2199 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
2204 ERR("Unknown error has occurred (0x%x)!\n",
2207 } else if (le32_to_cpu(curr_td->size_ioc_sts)
2208 & DTD_STATUS_ACTIVE) {
2209 VDBG("Request not complete");
2210 status = REQ_UNCOMPLETE;
2212 } else if (remaining_length) {
2214 VDBG("Transmit dTD remaining length not zero");
2223 VDBG("dTD transmitted successful");
2226 if (j != curr_req->dtd_count - 1)
2227 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
2233 curr_req->req.actual = actual;
2238 /* Process a DTD completion interrupt */
2239 static void dtd_complete_irq(struct tegra_udc *udc)
2242 int i, ep_num, direction, bit_mask, status;
2243 struct tegra_ep *curr_ep;
2244 struct tegra_req *curr_req, *temp_req;
2246 /* Clear the bits in the register */
2247 bit_pos = udc_readl(udc, EP_COMPLETE_REG_OFFSET);
2248 udc_writel(udc, bit_pos, EP_COMPLETE_REG_OFFSET);
2253 for (i = 0; i < udc->max_ep; i++) {
2257 bit_mask = 1 << (ep_num + 16 * direction);
2259 if (!(bit_pos & bit_mask))
2262 curr_ep = get_ep_by_pipe(udc, i);
2264 /* If the ep is configured */
2265 if (curr_ep->name[0] == '\0') {
2266 WARNING("Invalid EP?");
2270 /* process the req queue until an uncomplete request */
2271 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
2273 status = process_ep_req(udc, i, curr_req);
2275 VDBG("status of process_ep_req= %d, ep = %d",
2277 if (status == REQ_UNCOMPLETE)
2279 /* write back status to req */
2280 curr_req->req.status = status;
2283 ep0_req_complete(udc, curr_ep, curr_req);
2286 done(curr_ep, curr_req, status);
2291 /* Process a port change interrupt */
2292 static void port_change_irq(struct tegra_udc *udc)
2295 unsigned int port_control_reg_offset;
2297 if (udc->has_hostpc)
2298 port_control_reg_offset = USB_HOSTPCX_DEVLC_REG_OFFSET;
2300 port_control_reg_offset = PORTSCX_REG_OFFSET;
2302 /* Bus resetting is finished */
2303 if (!(udc_readl(udc, port_control_reg_offset) & PORTSCX_PORT_RESET)) {
2305 speed = (udc_readl(udc, port_control_reg_offset)
2306 & PORTSCX_PORT_SPEED_MASK);
2307 if (speed == PORTSCX_PORT_SPEED_HIGH)
2308 udc->gadget.speed = USB_SPEED_HIGH;
2309 else if (speed == PORTSCX_PORT_SPEED_FULL)
2310 udc->gadget.speed = USB_SPEED_FULL;
2311 else if (speed == PORTSCX_PORT_SPEED_LOW)
2312 udc->gadget.speed = USB_SPEED_LOW;
2314 udc->gadget.speed = USB_SPEED_UNKNOWN;
2317 /* Update USB state */
2318 if (!udc->resume_state)
2319 udc->usb_state = USB_STATE_DEFAULT;
2322 /* Process suspend interrupt */
2323 static void suspend_irq(struct tegra_udc *udc)
2325 udc->resume_state = udc->usb_state;
2326 udc->usb_state = USB_STATE_SUSPENDED;
2328 /* report suspend to the driver, serial.c does not support this */
2329 if (udc->driver && udc->driver->suspend)
2330 udc->driver->suspend(&udc->gadget);
2333 static void bus_resume(struct tegra_udc *udc)
2335 udc->usb_state = udc->resume_state;
2336 udc->resume_state = 0;
2338 /* report resume to the driver, serial.c does not support this */
2339 if (udc->driver && udc->driver->resume)
2340 udc->driver->resume(&udc->gadget);
2343 /* Clear up all ep queues */
2344 static int reset_queues(struct tegra_udc *udc)
2348 for (pipe = 0; pipe < udc->max_pipes; pipe++)
2349 udc_reset_ep_queue(udc, pipe);
2351 /* report disconnect; the driver is already quiesced */
2352 spin_unlock(&udc->lock);
2353 if (udc->driver && udc->driver->disconnect)
2354 udc->driver->disconnect(&udc->gadget);
2355 spin_lock(&udc->lock);
2360 /* Process reset interrupt */
2361 static void reset_irq(struct tegra_udc *udc)
2364 unsigned long timeout;
2366 /* Clear the device address */
2367 temp = udc_readl(udc, USB_DEVICE_ADDR_REG_OFFSET);
2368 udc_writel(udc, temp & ~USB_DEVICE_ADDRESS_MASK,
2369 USB_DEVICE_ADDR_REG_OFFSET);
2371 udc->device_address = 0;
2373 /* Clear usb state */
2374 udc->resume_state = 0;
2376 udc->ep0_state = WAIT_FOR_SETUP;
2377 udc->remote_wakeup = 0; /* default to 0 on reset */
2378 udc->gadget.b_hnp_enable = 0;
2379 udc->gadget.a_hnp_support = 0;
2380 udc->gadget.a_alt_hnp_support = 0;
2382 /* Clear all the setup token semaphores */
2383 temp = udc_readl(udc, EP_SETUP_STATUS_REG_OFFSET);
2384 udc_writel(udc, temp, EP_SETUP_STATUS_REG_OFFSET);
2386 /* Clear all the endpoint complete status bits */
2387 temp = udc_readl(udc, EP_COMPLETE_REG_OFFSET);
2388 udc_writel(udc, temp, EP_COMPLETE_REG_OFFSET);
2390 timeout = jiffies + 100;
2391 while (udc_readl(udc, EP_PRIME_REG_OFFSET)) {
2392 /* Wait until all endptprime bits cleared */
2393 if (time_after(jiffies, timeout)) {
2394 ERR("Timeout for reset\n");
2400 /* Write 1s to the flush register */
2401 udc_writel(udc, 0xffffffff, EPFLUSH_REG_OFFSET);
2403 /* When the bus reset is seen on Tegra, the PORTSCX_PORT_RESET bit
2404 * is not set. Reset all the queues, include XD, dTD, EP queue
2405 * head and TR Queue */
2408 udc->usb_state = USB_STATE_DEFAULT;
2411 static void tegra_udc_set_current_limit_work(struct work_struct *work)
2413 struct tegra_udc *udc = container_of(work, struct tegra_udc,
2415 tegra_usb_set_charging_current(udc);
2418 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
2419 void tegra_udc_set_cpu_freq_normal(unsigned long data)
2421 set_cpufreq_normal_flag = 1;
2422 schedule_work(&the_udc->boost_cpufreq_work);
2425 static void tegra_udc_boost_cpu_frequency_work(struct work_struct *work)
2427 if (set_cpufreq_normal_flag) {
2428 pm_qos_update_request(&boost_cpu_freq_req,
2429 PM_QOS_DEFAULT_VALUE);
2430 boost_cpufreq_work_flag = 1;
2431 set_cpufreq_normal_flag = 0;
2432 DBG("%s(%d) set CPU frequency to normal\n", __func__,
2437 /* If CPU frequency is not boosted earlier boost it, and modify
2438 * timer expiry time to 2sec */
2439 if (boost_cpufreq_work_flag) {
2441 pm_qos_update_request(
2442 &boost_cpu_freq_req,
2443 (s32)(CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
2445 boost_cpufreq_work_flag = 0;
2446 DBG("%s(%d) boost CPU frequency\n", __func__, __LINE__);
2448 mod_timer(&boost_timer, jiffies + msecs_to_jiffies(2000));
2452 static void tegra_udc_irq_work(struct work_struct *irq_work)
2454 struct tegra_udc *udc = container_of(irq_work, struct tegra_udc,
2456 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2458 /* Check whether cable is connected*/
2459 if (vbus_enabled(udc))
2460 tegra_vbus_session(&udc->gadget, 1);
2462 tegra_vbus_session(&udc->gadget, 0);
2464 DBG("%s(%d) END\n", __func__, __LINE__);
2468 * When VBUS is detected we already know it is DCP/SDP/CDP devices if it is a
2469 * standard device. If we did not receive EP0 setup packet, we can assume it
2470 * as a non-standard charger.
2472 static void tegra_udc_non_std_charger_detect_work(struct work_struct *work)
2474 struct tegra_udc *udc = container_of(work, struct tegra_udc,
2475 non_std_charger_work.work);
2476 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2478 tegra_udc_set_charger_type(udc, CONNECT_TYPE_NON_STANDARD_CHARGER);
2479 tegra_usb_set_charging_current(udc);
2481 DBG("%s(%d) END\n", __func__, __LINE__);
2484 /* Restart device controller in the OTG mode on VBUS detection */
2485 static void tegra_udc_restart(struct tegra_udc *udc)
2487 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2489 /* setup the controller in the device mode */
2490 dr_controller_setup(udc);
2491 /* setup EP0 for setup packet */
2493 udc->vbus_active = 1;
2494 /* start the controller */
2495 dr_controller_run(udc);
2496 /* initialize the USB and EP states */
2497 udc->usb_state = USB_STATE_ATTACHED;
2498 udc->ep0_state = WAIT_FOR_SETUP;
2501 DBG("%s(%d) END\n", __func__, __LINE__);
2504 /* USB device controller interrupt handler */
2505 static irqreturn_t tegra_udc_irq(int irq, void *_udc)
2507 struct tegra_udc *udc = _udc;
2509 irqreturn_t status = IRQ_NONE;
2510 unsigned long flags;
2512 spin_lock_irqsave(&udc->lock, flags);
2514 if (!udc->transceiver) {
2515 if (tegra_platform_is_fpga()) {
2516 temp = udc_readl(udc, VBUS_SENSOR_REG_OFFSET);
2517 /* write back the register to clear the interrupt */
2518 udc_writel(udc, temp, VBUS_SENSOR_REG_OFFSET);
2519 if (temp & USB_SYS_VBUS_ASESSION_CHANGED)
2520 schedule_work(&udc->irq_work);
2521 status = IRQ_HANDLED;
2523 temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
2524 /* write back the register to clear the interrupt */
2525 udc_writel(udc, temp, VBUS_WAKEUP_REG_OFFSET);
2526 if (temp & USB_SYS_VBUS_WAKEUP_INT_STATUS)
2527 schedule_work(&udc->irq_work);
2528 status = IRQ_HANDLED;
2532 /* Disable ISR for OTG host mode */
2536 /* Fence read for coherency of AHB master intiated writes */
2537 if (udc->fence_read)
2538 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
2540 irq_src = udc_readl(udc, USB_STS_REG_OFFSET) &
2541 udc_readl(udc, USB_INTR_REG_OFFSET);
2546 /* Clear notification bits */
2547 udc_writel(udc, irq_src, USB_STS_REG_OFFSET);
2549 /* Need to resume? */
2550 if (udc->usb_state == USB_STATE_SUSPENDED)
2551 if (!(udc_readl(udc, PORTSCX_REG_OFFSET)
2552 & PORTSCX_PORT_SUSPEND))
2556 if (irq_src & USB_STS_INT) {
2558 /* Setup package, we only support ep0 as control ep */
2559 if (udc_readl(udc, EP_SETUP_STATUS_REG_OFFSET) &
2560 EP_SETUP_STATUS_EP0) {
2561 /* Setup packet received, we are connected to host
2562 * and not to charger. Cancel any delayed work */
2563 cancel_delayed_work(&udc->non_std_charger_work);
2564 tripwire_handler(udc, 0,
2565 (u8 *) (&udc->local_setup_buff));
2566 setup_received_irq(udc, &udc->local_setup_buff);
2567 status = IRQ_HANDLED;
2570 /* completion of dtd */
2571 if (udc_readl(udc, EP_COMPLETE_REG_OFFSET)) {
2572 dtd_complete_irq(udc);
2573 status = IRQ_HANDLED;
2577 /* SOF (for ISO transfer) */
2578 if (irq_src & USB_STS_SOF)
2579 status = IRQ_HANDLED;
2582 if (irq_src & USB_STS_PORT_CHANGE) {
2583 port_change_irq(udc);
2584 status = IRQ_HANDLED;
2587 /* Reset Received */
2588 if (irq_src & USB_STS_RESET) {
2590 status = IRQ_HANDLED;
2593 /* Sleep Enable (Suspend) */
2594 if (irq_src & USB_STS_SUSPEND) {
2596 status = IRQ_HANDLED;
2599 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR))
2600 VDBG("Error IRQ %x", irq_src);
2603 spin_unlock_irqrestore(&udc->lock, flags);
2608 * Hook to gadget drivers
2609 * Called by initialization code of gadget drivers
2611 static int tegra_udc_start(struct usb_gadget *g,
2612 struct usb_gadget_driver *driver)
2614 struct tegra_udc *udc = the_udc;
2615 unsigned long flags = 0;
2616 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2618 /* lock is needed but whether should use this lock or another */
2619 spin_lock_irqsave(&udc->lock, flags);
2621 driver->driver.bus = NULL;
2622 /* hook up the driver */
2623 udc->driver = driver;
2624 spin_unlock_irqrestore(&udc->lock, flags);
2626 /* Enable DR IRQ reg and Set usbcmd reg Run bit */
2627 if (vbus_enabled(udc) && !(udc->transceiver
2628 && udc->transceiver->state != OTG_STATE_B_PERIPHERAL))
2629 tegra_vbus_session(&udc->gadget, 1);
2631 printk(KERN_INFO "%s: bind to driver %s\n",
2632 udc->gadget.name, driver->driver.name);
2634 DBG("%s(%d) END\n", __func__, __LINE__);
2638 /* Disconnect from gadget driver */
2639 static int tegra_udc_stop(struct usb_gadget *g,
2640 struct usb_gadget_driver *driver)
2642 struct tegra_udc *udc = the_udc;
2643 struct tegra_ep *loop_ep;
2644 unsigned long flags;
2646 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2648 tegra_vbus_session(&udc->gadget, 0);
2650 /* stand operation */
2651 spin_lock_irqsave(&udc->lock, flags);
2652 udc->gadget.speed = USB_SPEED_UNKNOWN;
2653 nuke(&udc->eps[0], -ESHUTDOWN);
2654 list_for_each_entry(loop_ep, &udc->gadget.ep_list,
2656 nuke(loop_ep, -ESHUTDOWN);
2657 spin_unlock_irqrestore(&udc->lock, flags);
2659 udc->gadget.dev.driver = NULL;
2663 DBG("%s(%d) unregistered gadget driver '%s'\n",
2664 __func__, __LINE__, driver->driver.name);
2666 DBG("%s(%d) END\n", __func__, __LINE__);
2672 /* Internal structure setup functions */
2673 static int tegra_udc_setup_qh(struct tegra_udc *udc)
2677 struct resource *res;
2679 /* Read Device Controller Capability Parameters register */
2680 dccparams = udc_readl(udc, DCCPARAMS_REG_OFFSET);
2681 if (!(dccparams & DCCPARAMS_DC)) {
2682 ERR("This SOC doesn't support device role\n");
2686 /* Get max device endpoints */
2687 /* DEN is bidirectional ep number, max_ep doubles the number */
2688 udc->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2690 udc->eps = kzalloc(sizeof(struct tegra_ep) * udc->max_ep, GFP_KERNEL);
2692 ERR("malloc tegra_ep failed\n");
2696 /* Setup hardware queue heads */
2697 size = udc->max_ep * sizeof(struct ep_queue_head);
2698 udc->ep_qh = (struct ep_queue_head *)((u8 *)(udc->regs) + QH_OFFSET);
2699 res = platform_get_resource(udc->pdev, IORESOURCE_MEM, 0);
2701 ERR("resource request failed\n");
2705 udc->ep_qh_dma = res->start + QH_OFFSET;
2706 udc->ep_qh_size = size;
2708 /* Initialize ep0 status request structure */
2709 /* FIXME: tegra_alloc_request() ignores ep argument */
2710 udc->status_req = container_of(tegra_alloc_request(NULL, GFP_KERNEL),
2711 struct tegra_req, req);
2712 /* Allocate a small amount of memory to get valid address */
2713 udc->status_req->req.buf = dma_alloc_coherent(&udc->pdev->dev,
2714 STATUS_BUFFER_SIZE, &udc->status_req->req.dma,
2716 if (!udc->status_req->req.buf) {
2717 ERR("alloc status_req buffer failed\n");
2722 udc->resume_state = USB_STATE_NOTATTACHED;
2723 udc->usb_state = USB_STATE_POWERED;
2725 udc->remote_wakeup = 0; /* default to 0 on reset */
2731 * Setup the tegra_ep struct for eps
2732 * Link tegra_ep->ep to gadget->ep_list
2733 * ep0out is not used so do nothing here
2734 * ep0in should be taken care
2736 static int __init struct_ep_setup(struct tegra_udc *udc, unsigned char index,
2737 char *name, int link)
2739 struct tegra_ep *ep = &udc->eps[index];
2742 strcpy(ep->name, name);
2743 ep->ep.name = ep->name;
2745 ep->ep.ops = &tegra_ep_ops;
2748 /* for ep0: maxP defined in desc
2749 * for other eps, maxP is set by epautoconfig() called by gadget layer
2751 ep->ep.maxpacket = (unsigned short) ~0;
2753 /* the queue lists any req for this ep */
2754 INIT_LIST_HEAD(&ep->queue);
2756 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2758 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2759 ep->gadget = &udc->gadget;
2760 ep->qh = &udc->ep_qh[index];
2765 static int tegra_udc_ep_setup(struct tegra_udc *udc)
2767 /* initialize EP0 descriptor */
2768 static const struct usb_endpoint_descriptor tegra_ep0_desc = {
2769 .bLength = USB_DT_ENDPOINT_SIZE,
2770 .bDescriptorType = USB_DT_ENDPOINT,
2771 .bEndpointAddress = 0,
2772 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2773 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
2777 /* setup QH and epctrl for ep0 */
2780 /* setup udc->eps[] for ep0 */
2781 struct_ep_setup(udc, 0, "ep0", 0);
2782 /* for ep0: the desc defined here;
2783 * for other eps, gadget layer called ep_enable with defined desc
2785 udc->eps[0].desc = &tegra_ep0_desc;
2786 udc->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2788 /* setup the udc->eps[] for non-control endpoints and link
2789 * to gadget.ep_list */
2790 for (i = 1; i < (int)(udc->max_ep / 2); i++) {
2793 sprintf(name, "ep%dout", i);
2794 struct_ep_setup(udc, i * 2, name, 1);
2795 sprintf(name, "ep%din", i);
2796 struct_ep_setup(udc, i * 2 + 1, name, 1);
2803 /* Driver probe function
2804 * all intialization operations implemented here except enabling usb_intr reg
2805 * board setup should have been done in the platform code
2807 static int __init tegra_udc_probe(struct platform_device *pdev)
2809 struct tegra_udc *udc;
2810 struct resource *res;
2811 struct tegra_usb_platform_data *pdata;
2813 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
2815 if (strcmp(pdev->name, driver_name)) {
2816 VDBG("Wrong device");
2820 the_udc = udc = kzalloc(sizeof(struct tegra_udc), GFP_KERNEL);
2822 ERR("malloc udc failed\n");
2826 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2829 ERR("failed to get platform resources\n");
2833 if (!request_mem_region(res->start, res->end - res->start + 1,
2835 ERR("request mem region failed\n");
2840 udc->regs = ioremap(res->start, resource_size(res));
2843 ERR("failed to map mem region\n");
2844 goto err_rel_mem_region;
2847 udc->irq = platform_get_irq(pdev, 0);
2850 ERR("failed to get platform irq resources\n");
2854 err = request_irq(udc->irq, tegra_udc_irq,
2855 IRQF_SHARED | IRQF_TRIGGER_HIGH,
2858 ERR("cannot request irq %d err %d\n", udc->irq, err);
2862 /*Disable fence read if H/W support is disabled*/
2863 pdata = dev_get_platdata(&pdev->dev);
2865 if (pdata->unaligned_dma_buf_supported)
2866 udc->fence_read = false;
2868 udc->fence_read = true;
2870 udc->charging_supported = pdata->u_data.dev.charging_supported;
2871 udc->qc2_voltage = pdata->qc2_voltage;
2873 udc->qc2_current_limit =
2874 pdata->u_data.dev.qc2_current_limit_ma * 1000;
2876 DBG("%s: QC2 voltage = %d, current = %d\n",
2879 udc->qc2_current_limit);
2881 if (pdata->u_data.dev.dcp_current_limit_ma)
2882 udc->dcp_current_limit =
2883 pdata->u_data.dev.dcp_current_limit_ma * 1000;
2885 udc->dcp_current_limit =
2886 USB_CHARGING_DCP_CURRENT_LIMIT_UA;
2888 dev_err(&pdev->dev, "failed to get platform_data\n");
2893 udc->phy = tegra_usb_phy_open(pdev);
2894 if (IS_ERR(udc->phy)) {
2895 dev_err(&pdev->dev, "failed to open USB phy\n");
2900 err = tegra_usb_phy_power_on(udc->phy);
2902 dev_err(&pdev->dev, "failed to power on the phy\n");
2906 err = usb_phy_init(get_usb_phy(udc->phy));
2908 dev_err(&pdev->dev, "failed to init the phy\n");
2911 spin_lock_init(&udc->lock);
2912 mutex_init(&udc->sync_lock);
2915 udc->has_hostpc = pdata->has_hostpc;
2916 udc->support_pmu_vbus = pdata->support_pmu_vbus;
2917 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
2918 platform_set_drvdata(pdev, udc);
2920 /* Initialize the udc structure including QH members */
2921 err = tegra_udc_setup_qh(udc);
2923 dev_err(&pdev->dev, "failed to setup udc QH\n");
2927 /* Initialize usb hw reg except for regs for EP,
2928 * leave usbintr reg untouched */
2929 err = dr_controller_setup(udc);
2931 dev_err(&pdev->dev, "failed to setup udc controller\n");
2935 /* Setup gadget structure */
2936 udc->gadget.ops = &tegra_gadget_ops;
2937 udc->gadget.max_speed = USB_SPEED_HIGH;
2938 udc->gadget.ep0 = &udc->eps[0].ep;
2939 INIT_LIST_HEAD(&udc->gadget.ep_list);
2940 udc->gadget.speed = USB_SPEED_UNKNOWN;
2941 udc->gadget.name = driver_name;
2943 err = tegra_udc_ep_setup(udc);
2945 dev_err(&pdev->dev, "failed to setup end points\n");
2949 /* Use dma_pool for TD management */
2950 udc->td_pool = dma_pool_create("udc_td", &pdev->dev,
2951 sizeof(struct ep_td_struct),
2952 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2953 if (!udc->td_pool) {
2958 err = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2962 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
2963 boost_cpufreq_work_flag = 1;
2964 ep_queue_request_count = 0;
2965 INIT_WORK(&udc->boost_cpufreq_work,
2966 tegra_udc_boost_cpu_frequency_work);
2967 pm_qos_add_request(&boost_cpu_freq_req, PM_QOS_CPU_FREQ_MIN,
2968 PM_QOS_DEFAULT_VALUE);
2969 setup_timer(&boost_timer, tegra_udc_set_cpu_freq_normal, 0);
2972 /* External connector */
2973 udc->edev = kzalloc(sizeof(struct extcon_dev), GFP_KERNEL);
2975 dev_err(&pdev->dev, "failed to allocate memory for extcon\n");
2980 udc->edev->name = driver_name;
2981 udc->edev->supported_cable = (const char **) tegra_udc_extcon_cable;
2982 err = extcon_dev_register(udc->edev, &pdev->dev);
2984 dev_err(&pdev->dev, "failed to register extcon device\n");
2989 if (udc->support_pmu_vbus && pdata->vbus_extcon_dev_name)
2990 udc->vbus_extcon_dev =
2991 extcon_get_extcon_dev(pdata->vbus_extcon_dev_name);
2993 /* Create work for controlling clocks to the phy if otg is disabled */
2994 INIT_WORK(&udc->irq_work, tegra_udc_irq_work);
2995 INIT_DELAYED_WORK(&udc->non_std_charger_work,
2996 tegra_udc_non_std_charger_detect_work);
2997 INIT_WORK(&udc->current_work, tegra_udc_set_current_limit_work);
2998 /* Get the regulator for drawing the vbus current in udc driver */
2999 udc->vbus_reg = regulator_get(&pdev->dev, "usb_bat_chg");
3000 if (IS_ERR(udc->vbus_reg)) {
3001 dev_info(&pdev->dev,
3002 "usb_bat_chg regulator not registered:"
3003 " USB charging will not be enabled\n");
3004 udc->vbus_reg = NULL;
3007 if (pdata->port_otg)
3008 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
3010 if (IS_ERR_OR_NULL(udc->transceiver))
3011 udc->transceiver = NULL;
3013 if (udc->transceiver) {
3014 dr_controller_stop(udc);
3015 dr_controller_reset(udc);
3016 tegra_usb_phy_power_off(udc->phy);
3017 udc->vbus_active = 0;
3018 udc->usb_state = USB_STATE_DEFAULT;
3019 otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
3022 DBG("%s(%d) END\n", __func__, __LINE__);
3026 dma_pool_destroy(udc->td_pool);
3029 usb_phy_shutdown(get_usb_phy(udc->phy));
3032 free_irq(udc->irq, udc);
3038 release_mem_region(res->start, res->end - res->start + 1);
3046 /* Driver removal function
3047 * Free resources and finish pending transactions
3049 static int __exit tegra_udc_remove(struct platform_device *pdev)
3051 struct tegra_udc *udc = platform_get_drvdata(pdev);
3052 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3054 DECLARE_COMPLETION(done);
3059 ERR("resource request failed\n");
3063 if (udc->edev != NULL) {
3064 extcon_dev_unregister(udc->edev);
3068 usb_del_gadget_udc(&udc->gadget);
3071 cancel_delayed_work(&udc->non_std_charger_work);
3072 cancel_work_sync(&udc->irq_work);
3073 #ifdef CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ
3074 cancel_work_sync(&udc->boost_cpufreq_work);
3075 pm_qos_remove_request(&boost_cpu_freq_req);
3076 del_timer(&boost_timer);
3080 regulator_put(udc->vbus_reg);
3082 if (udc->transceiver)
3083 otg_set_peripheral(udc->transceiver->otg, NULL);
3085 /* Free allocated memory */
3086 dma_free_coherent(&pdev->dev, STATUS_BUFFER_SIZE,
3087 udc->status_req->req.buf,
3088 udc->status_req->req.dma);
3089 kfree(udc->status_req);
3092 dma_pool_destroy(udc->td_pool);
3093 free_irq(udc->irq, udc);
3095 release_mem_region(res->start, res->end - res->start + 1);
3097 mutex_destroy(&udc->sync_lock);
3098 /* Free udc -- wait for the release() finished */
3099 wait_for_completion(&done);
3104 static int tegra_udc_suspend(struct platform_device *pdev, pm_message_t state)
3106 struct tegra_udc *udc = platform_get_drvdata(pdev);
3107 unsigned long flags;
3111 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
3113 if (udc->support_pmu_vbus) {
3114 if (extcon_get_cable_state(udc->vbus_extcon_dev, "USB"))
3115 udc->vbus_in_lp0 = true;
3117 temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
3118 if (temp & USB_SYS_VBUS_STATUS)
3119 udc->vbus_in_lp0 = true;
3121 udc->connect_type_lp0 = udc->connect_type;
3123 /* If the controller is in otg mode, return */
3124 if (udc->transceiver)
3128 err = enable_irq_wake(udc->irq);
3131 "Couldn't enable USB udc mode wakeup,"
3132 " irq=%d, error=%d\n", udc->irq, err);
3135 if (udc->vbus_active) {
3136 spin_lock_irqsave(&udc->lock, flags);
3137 /* Reset all internal Queues and inform client driver */
3139 udc->vbus_active = 0;
3140 udc->usb_state = USB_STATE_DEFAULT;
3141 spin_unlock_irqrestore(&udc->lock, flags);
3143 /* Stop the controller and turn off the clocks */
3144 dr_controller_stop(udc);
3146 tegra_usb_phy_power_off(udc->phy);
3148 DBG("%s(%d) END\n", __func__, __LINE__);
3152 static int tegra_udc_resume(struct platform_device *pdev)
3154 struct tegra_udc *udc = platform_get_drvdata(pdev);
3158 DBG("%s(%d) BEGIN\n", __func__, __LINE__);
3160 udc->vbus_in_lp0 = false;
3162 /* Set Current limit to 0 if charger is disconnected in LP0 */
3163 if (udc->vbus_reg != NULL) {
3164 if (udc->support_pmu_vbus) {
3165 if ((udc->connect_type_lp0 != CONNECT_TYPE_NONE) &&
3166 !extcon_get_cable_state(udc->vbus_extcon_dev, "USB")) {
3167 tegra_udc_set_extcon_state(udc);
3168 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3169 regulator_set_current_limit(udc->vbus_reg,
3173 temp = udc_readl(udc, VBUS_WAKEUP_REG_OFFSET);
3174 if ((udc->connect_type_lp0 != CONNECT_TYPE_NONE) &&
3175 !(temp & USB_SYS_VBUS_STATUS)) {
3176 tegra_udc_set_extcon_state(udc);
3177 udc->connect_type_lp0 = CONNECT_TYPE_NONE;
3178 regulator_set_current_limit(udc->vbus_reg,
3184 if (udc->transceiver)
3188 err = disable_irq_wake(udc->irq);
3191 "Couldn't disable USB udc mode wakeup, "
3192 "irq=%d, error=%d\n", udc->irq, err);
3195 tegra_usb_phy_power_on(udc->phy);
3196 tegra_udc_restart(udc);
3198 /* Power down the phy if cable is not connected */
3199 if (!vbus_enabled(udc)) {
3200 udc->vbus_active = 0;
3201 tegra_usb_phy_power_off(udc->phy);
3204 DBG("%s(%d) END\n", __func__, __LINE__);
3209 static struct platform_driver tegra_udc_driver = {
3210 .remove = __exit_p(tegra_udc_remove),
3211 .suspend = tegra_udc_suspend,
3212 .resume = tegra_udc_resume,
3214 .name = (char *)driver_name,
3215 .owner = THIS_MODULE,
3219 static int __init udc_init(void)
3221 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
3222 return platform_driver_probe(&tegra_udc_driver, tegra_udc_probe);
3224 module_init(udc_init);
3225 static void __exit udc_exit(void)
3227 platform_driver_unregister(&tegra_udc_driver);
3228 printk(KERN_WARNING "%s unregistered\n", driver_desc);
3230 module_exit(udc_exit);
3232 MODULE_DESCRIPTION(DRIVER_DESC);
3233 MODULE_AUTHOR(DRIVER_AUTHOR);
3234 MODULE_LICENSE("GPL");
3235 MODULE_ALIAS("platform:tegra-udc");