2 * include/linux/tegra_profiler.h
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef __TEGRA_PROFILER_H
18 #define __TEGRA_PROFILER_H
20 #include <linux/ioctl.h>
22 #define QUADD_SAMPLES_VERSION 29
23 #define QUADD_IO_VERSION 12
25 #define QUADD_IO_VERSION_DYNAMIC_RB 5
26 #define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
27 #define QUADD_IO_VERSION_MOD_STATE_STATUS_FIELD 7
28 #define QUADD_IO_VERSION_BT_KERNEL_CTX 8
29 #define QUADD_IO_VERSION_GET_MMAP 9
30 #define QUADD_IO_VERSION_BT_UNWIND_TABLES 10
31 #define QUADD_IO_VERSION_UNWIND_MIXED 11
32 #define QUADD_IO_VERSION_EXTABLES_MMAP 12
34 #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
35 #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
36 #define QUADD_SAMPLE_VERSION_THREAD_STATE_FLD 19
37 #define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22
38 #define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23
39 #define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24
40 #define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25
41 #define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE 26
42 #define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER 27
43 #define QUADD_SAMPLE_VERSION_SCHED_SAMPLES 28
44 #define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29
46 #define QUADD_MAX_COUNTERS 32
47 #define QUADD_MAX_PROCESS 64
49 #define QUADD_DEVICE_NAME "quadd"
50 #define QUADD_AUTH_DEVICE_NAME "quadd_auth"
52 #define QUADD_MOD_DEVICE_NAME "quadd_mod"
53 #define QUADD_MOD_AUTH_DEVICE_NAME "quadd_mod_auth"
55 #define QUADD_IOCTL 100
58 * Setup params (profiling frequency, etc.)
60 #define IOCTL_SETUP _IOW(QUADD_IOCTL, 0, struct quadd_parameters)
65 #define IOCTL_START _IO(QUADD_IOCTL, 1)
70 #define IOCTL_STOP _IO(QUADD_IOCTL, 2)
73 * Getting capabilities
75 #define IOCTL_GET_CAP _IOR(QUADD_IOCTL, 3, struct quadd_comm_cap)
78 * Getting state of module
80 #define IOCTL_GET_STATE _IOR(QUADD_IOCTL, 4, struct quadd_module_state)
83 * Getting version of module
85 #define IOCTL_GET_VERSION _IOR(QUADD_IOCTL, 5, struct quadd_module_version)
88 * Send exception-handling tables info
90 #define IOCTL_SET_EXTAB _IOW(QUADD_IOCTL, 6, struct quadd_extables)
92 #define QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP (1 << 29) /* LP CPU */
93 #define QUADD_CPUMODE_THUMB (1 << 30) /* thumb mode */
95 enum quadd_events_id {
96 QUADD_EVENT_TYPE_CPU_CYCLES = 0,
98 QUADD_EVENT_TYPE_INSTRUCTIONS,
99 QUADD_EVENT_TYPE_BRANCH_INSTRUCTIONS,
100 QUADD_EVENT_TYPE_BRANCH_MISSES,
101 QUADD_EVENT_TYPE_BUS_CYCLES,
103 QUADD_EVENT_TYPE_L1_DCACHE_READ_MISSES,
104 QUADD_EVENT_TYPE_L1_DCACHE_WRITE_MISSES,
105 QUADD_EVENT_TYPE_L1_ICACHE_MISSES,
107 QUADD_EVENT_TYPE_L2_DCACHE_READ_MISSES,
108 QUADD_EVENT_TYPE_L2_DCACHE_WRITE_MISSES,
109 QUADD_EVENT_TYPE_L2_ICACHE_MISSES,
111 QUADD_EVENT_TYPE_MAX,
122 enum quadd_record_type {
123 QUADD_RECORD_TYPE_SAMPLE = 1,
124 QUADD_RECORD_TYPE_MMAP,
125 QUADD_RECORD_TYPE_MA,
126 QUADD_RECORD_TYPE_COMM,
127 QUADD_RECORD_TYPE_DEBUG,
128 QUADD_RECORD_TYPE_HEADER,
129 QUADD_RECORD_TYPE_POWER_RATE,
130 QUADD_RECORD_TYPE_ADDITIONAL_SAMPLE,
131 QUADD_RECORD_TYPE_SCHED,
134 enum quadd_event_source {
135 QUADD_EVENT_SOURCE_PMU = 1,
136 QUADD_EVENT_SOURCE_PL310,
139 enum quadd_cpu_mode {
140 QUADD_CPU_MODE_KERNEL = 1,
145 #pragma pack(push, 1)
147 #define QUADD_SAMPLE_UNW_METHOD_SHIFT 0
148 #define QUADD_SAMPLE_UNW_METHOD_MASK (1 << QUADD_SAMPLE_UNW_METHOD_SHIFT)
151 QUADD_UNW_METHOD_FP = 0,
152 QUADD_UNW_METHOD_EHT,
153 QUADD_UNW_METHOD_MIXED,
154 QUADD_UNW_METHOD_NONE,
157 #define QUADD_SAMPLE_URC_SHIFT 1
158 #define QUADD_SAMPLE_URC_MASK (0x0f << QUADD_SAMPLE_URC_SHIFT)
161 QUADD_URC_SUCCESS = 0,
163 QUADD_URC_IDX_NOT_FOUND,
164 QUADD_URC_TBL_NOT_EXIST,
166 QUADD_URC_TBL_IS_CORRUPT,
167 QUADD_URC_CANTUNWIND,
168 QUADD_URC_UNHANDLED_INSTRUCTION,
169 QUADD_URC_REFUSE_TO_UNWIND,
170 QUADD_URC_SP_INCORRECT,
171 QUADD_URC_SPARE_ENCODING,
172 QUADD_URC_UNSUPPORTED_PR,
173 QUADD_URC_PC_INCORRECT,
174 QUADD_URC_LEVEL_TOO_DEEP,
175 QUADD_URC_FP_INCORRECT,
179 #define QUADD_SED_IP64 (1 << 0)
181 #define QUADD_SED_UNW_METHOD_SHIFT 1
182 #define QUADD_SED_UNW_METHOD_MASK (0x07 << QUADD_SED_UNW_METHOD_SHIFT)
185 QUADD_UNW_TYPE_FP = 0,
187 QUADD_UNW_TYPE_LR_FP,
188 QUADD_UNW_TYPE_LR_UT,
192 struct quadd_sample_data {
209 #define QUADD_MMAP_ED_IS_FILE_EXISTS (1 << 0)
211 struct quadd_mmap_data {
221 struct quadd_ma_data {
229 struct quadd_power_rate_data {
238 struct quadd_additional_sample {
245 struct quadd_sched_data {
258 QM_DEBUG_SAMPLE_TYPE_SCHED_IN = 1,
259 QM_DEBUG_SAMPLE_TYPE_SCHED_OUT,
261 QM_DEBUG_SAMPLE_TYPE_TIMER_HANDLE,
262 QM_DEBUG_SAMPLE_TYPE_TIMER_START,
263 QM_DEBUG_SAMPLE_TYPE_TIMER_CANCEL,
264 QM_DEBUG_SAMPLE_TYPE_TIMER_FORWARD,
266 QM_DEBUG_SAMPLE_TYPE_READ_COUNTER,
268 QM_DEBUG_SAMPLE_TYPE_SOURCE_START,
269 QM_DEBUG_SAMPLE_TYPE_SOURCE_STOP,
272 struct quadd_debug_data {
288 #define QUADD_HEADER_MAGIC 0x1122
290 #define QUADD_HDR_UNW_METHOD_SHIFT 0
291 #define QUADD_HDR_UNW_METHOD_MASK (0x07 << QUADD_HDR_UNW_METHOD_SHIFT)
293 struct quadd_header_data {
303 reserved:26; /* reserved fields for future extensions */
313 struct quadd_record_data {
316 /* sample: it should be the biggest size */
318 struct quadd_sample_data sample;
319 struct quadd_mmap_data mmap;
320 struct quadd_ma_data ma;
321 struct quadd_debug_data debug;
322 struct quadd_header_data hdr;
323 struct quadd_power_rate_data power_rate;
324 struct quadd_sched_data sched;
325 struct quadd_additional_sample additional_sample;
331 #define QUADD_MAX_PACKAGE_NAME 320
334 QUADD_PARAM_IDX_SIZE_OF_RB = 0,
335 QUADD_PARAM_IDX_EXTRA = 1,
338 #define QUADD_PARAM_EXTRA_GET_MMAP (1 << 0)
339 #define QUADD_PARAM_EXTRA_BT_FP (1 << 1)
340 #define QUADD_PARAM_EXTRA_BT_UNWIND_TABLES (1 << 2)
341 #define QUADD_PARAM_EXTRA_BT_MIXED (1 << 3)
343 struct quadd_parameters {
353 u32 pids[QUADD_MAX_PROCESS];
356 u8 package_name[QUADD_MAX_PACKAGE_NAME];
358 u32 events[QUADD_MAX_COUNTERS];
361 u32 reserved[16]; /* reserved fields for future extensions */
364 struct quadd_events_cap {
367 branch_instructions:1,
371 l1_dcache_read_misses:1,
372 l1_dcache_write_misses:1,
375 l2_dcache_read_misses:1,
376 l2_dcache_write_misses:1,
381 QUADD_COMM_CAP_IDX_EXTRA = 0,
384 #define QUADD_COMM_CAP_EXTRA_BT_KERNEL_CTX (1 << 0)
385 #define QUADD_COMM_CAP_EXTRA_GET_MMAP (1 << 1)
386 #define QUADD_COMM_CAP_EXTRA_GROUP_SAMPLES (1 << 2)
387 #define QUADD_COMM_CAP_EXTRA_BT_UNWIND_TABLES (1 << 3)
388 #define QUADD_COMM_CAP_EXTRA_SUPPORT_AARCH64 (1 << 4)
389 #define QUADD_COMM_CAP_EXTRA_SPECIAL_ARCH_MMAP (1 << 5)
390 #define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED (1 << 6)
391 #define QUADD_COMM_CAP_EXTRA_UNW_ENTRY_TYPE (1 << 7)
392 #define QUADD_COMM_CAP_EXTRA_USE_ARCH_TIMER (1 << 8)
394 struct quadd_comm_cap {
398 l2_multiple_events:1,
402 struct quadd_events_cap events_cap;
404 u32 reserved[16]; /* reserved fields for future extensions */
408 QUADD_MOD_STATE_IDX_RB_MAX_FILL_COUNT = 0,
409 QUADD_MOD_STATE_IDX_STATUS,
412 #define QUADD_MOD_STATE_STATUS_IS_ACTIVE (1 << 0)
413 #define QUADD_MOD_STATE_STATUS_IS_AUTH_OPEN (1 << 1)
415 struct quadd_module_state {
417 u64 nr_skipped_samples;
420 u32 buffer_fill_size;
422 u32 reserved[16]; /* reserved fields for future extensions */
425 struct quadd_module_version {
432 u32 reserved[4]; /* reserved fields for future extensions */
435 struct quadd_sec_info {
441 QUADD_EXT_IDX_EXTAB_OFFSET = 0,
442 QUADD_EXT_IDX_EXIDX_OFFSET = 1,
443 QUADD_EXT_IDX_MMAP_VM_START = 2,
446 struct quadd_extables {
450 struct quadd_sec_info extab;
451 struct quadd_sec_info exidx;
453 u32 reserved[4]; /* reserved fields for future extensions */
461 struct vm_area_struct;
463 #ifdef CONFIG_TEGRA_PROFILER
464 extern void __quadd_task_sched_in(struct task_struct *prev,
465 struct task_struct *task);
466 extern void __quadd_task_sched_out(struct task_struct *prev,
467 struct task_struct *next);
469 extern void __quadd_event_mmap(struct vm_area_struct *vma);
471 static inline void quadd_task_sched_in(struct task_struct *prev,
472 struct task_struct *task)
474 __quadd_task_sched_in(prev, task);
477 static inline void quadd_task_sched_out(struct task_struct *prev,
478 struct task_struct *next)
480 __quadd_task_sched_out(prev, next);
483 static inline void quadd_event_mmap(struct vm_area_struct *vma)
485 __quadd_event_mmap(vma);
488 #else /* CONFIG_TEGRA_PROFILER */
490 static inline void quadd_task_sched_in(struct task_struct *prev,
491 struct task_struct *task)
495 static inline void quadd_task_sched_out(struct task_struct *prev,
496 struct task_struct *next)
500 static inline void quadd_event_mmap(struct vm_area_struct *vma)
504 #endif /* CONFIG_TEGRA_PROFILER */
506 #endif /* __KERNEL__ */
508 #endif /* __TEGRA_PROFILER_H */