2 * arch/arm/mach-tegra/board-ardbeg-sensors.c
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/i2c.h>
20 #include <linux/gpio.h>
21 #include <linux/mpu.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/nct1008.h>
25 #include <linux/pid_thermal_gov.h>
26 #include <linux/power/sbs-battery.h>
27 #include <linux/tegra-fuse.h>
29 #include <mach/pinmux-t12.h>
30 #include <mach/pinmux.h>
31 #include <mach/io_dpd.h>
32 #include <media/camera.h>
33 #include <media/ar0261.h>
34 #include <media/imx135.h>
35 #include <media/dw9718.h>
36 #include <media/as364x.h>
37 #include <media/ov5693.h>
38 #include <media/ov7695.h>
39 #include <media/mt9m114.h>
40 #include <media/ad5823.h>
41 #include <media/max77387.h>
43 #include <linux/platform_device.h>
44 #include <media/soc_camera.h>
45 #include <media/soc_camera_platform.h>
46 #include <media/tegra_v4l2_camera.h>
48 #include "cpu-tegra.h"
51 #include "board-common.h"
52 #include "board-ardbeg.h"
53 #include "tegra-board-id.h"
55 static struct i2c_board_info ardbeg_i2c_board_info_cm32181[] = {
57 I2C_BOARD_INFO("cm32181", 0x48),
61 /* MPU board file definition */
62 static struct mpu_platform_data mpu9250_gyro_data = {
65 /* Located in board_[platformname].h */
66 .orientation = MPU_GYRO_ORIENTATION,
67 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
68 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
69 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
72 static struct mpu_platform_data mpu9250_gyro_data_e1762 = {
75 /* Located in board_[platformname].h */
76 .orientation = MPU_GYRO_ORIENTATION_E1762,
77 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
78 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
79 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
82 static struct mpu_platform_data mpu_compass_data = {
83 .orientation = MPU_COMPASS_ORIENTATION,
84 .config = NVI_CONFIG_BOOT_MPU,
87 static struct mpu_platform_data mpu_bmp_pdata = {
88 .config = NVI_CONFIG_BOOT_MPU,
91 static struct i2c_board_info __initdata inv_mpu9250_i2c0_board_info[] = {
93 I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
94 .platform_data = &mpu9250_gyro_data,
97 /* The actual BMP180 address is 0x77 but because this conflicts
98 * with another device, this address is hacked so Linux will
99 * call the driver. The conflict is technically okay since the
100 * BMP180 is behind the MPU. Also, the BMP180 driver uses a
101 * hard-coded address of 0x77 since it can't be changed anyway.
103 I2C_BOARD_INFO(MPU_BMP_NAME, MPU_BMP_ADDR),
104 .platform_data = &mpu_bmp_pdata,
107 I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR),
108 .platform_data = &mpu_compass_data,
112 static void mpuirq_init(void)
115 unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
116 unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
117 char *gyro_name = MPU_GYRO_NAME;
118 struct board_info board_info;
120 pr_info("*** MPU START *** mpuirq_init...\n");
122 tegra_get_board_info(&board_info);
124 ret = gpio_request(gyro_irq_gpio, gyro_name);
126 pr_err("%s: gpio_request failed %d\n", __func__, ret);
130 ret = gpio_direction_input(gyro_irq_gpio);
132 pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
133 gpio_free(gyro_irq_gpio);
136 pr_info("*** MPU END *** mpuirq_init...\n");
138 /* TN8 with diferent Compass address from ardbeg */
139 if (of_machine_is_compatible("nvidia,tn8"))
140 inv_mpu9250_i2c0_board_info[2].addr = MPU_COMPASS_ADDR_TN8;
142 if (board_info.board_id == BOARD_E1762)
143 inv_mpu9250_i2c0_board_info[0].platform_data =
144 &mpu9250_gyro_data_e1762;
145 inv_mpu9250_i2c0_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
146 i2c_register_board_info(gyro_bus_num, inv_mpu9250_i2c0_board_info,
147 ARRAY_SIZE(inv_mpu9250_i2c0_board_info));
151 * Soc Camera platform driver for testing
153 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
154 static int ardbeg_soc_camera_add(struct soc_camera_device *icd);
155 static void ardbeg_soc_camera_del(struct soc_camera_device *icd);
157 static int ardbeg_soc_camera_set_capture(struct soc_camera_platform_info *info,
160 /* TODO: probably add clk opertaion here */
161 return 0; /* camera sensor always enabled */
164 static struct soc_camera_platform_info ardbeg_soc_camera_info = {
165 .format_name = "RGB4",
168 .code = V4L2_MBUS_FMT_RGBA8888_4X8_LE,
169 .colorspace = V4L2_COLORSPACE_SRGB,
170 .field = V4L2_FIELD_NONE,
174 .set_capture = ardbeg_soc_camera_set_capture,
177 static struct tegra_camera_platform_data ardbeg_camera_platform_data = {
180 .port = TEGRA_CAMERA_PORT_CSI_A,
185 static struct soc_camera_link ardbeg_soc_camera_link = {
186 .bus_id = 0, /* This must match the .id of tegra_vi01_device */
187 .add_device = ardbeg_soc_camera_add,
188 .del_device = ardbeg_soc_camera_del,
189 .module_name = "soc_camera_platform",
190 .priv = &ardbeg_camera_platform_data,
191 .dev_priv = &ardbeg_soc_camera_info,
194 static struct platform_device *ardbeg_pdev;
196 static void ardbeg_soc_camera_release(struct device *dev)
198 soc_camera_platform_release(&ardbeg_pdev);
201 static int ardbeg_soc_camera_add(struct soc_camera_device *icd)
203 return soc_camera_platform_add(icd, &ardbeg_pdev,
204 &ardbeg_soc_camera_link,
205 ardbeg_soc_camera_release, 0);
208 static void ardbeg_soc_camera_del(struct soc_camera_device *icd)
210 soc_camera_platform_del(icd, ardbeg_pdev, &ardbeg_soc_camera_link);
213 static struct platform_device ardbeg_soc_camera_device = {
214 .name = "soc-camera-pdrv",
217 .platform_data = &ardbeg_soc_camera_link,
222 static struct regulator *ardbeg_vcmvdd;
224 static int ardbeg_get_extra_regulators(void)
226 if (!ardbeg_vcmvdd) {
227 ardbeg_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
228 if (WARN_ON(IS_ERR(ardbeg_vcmvdd))) {
229 pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
230 __func__, PTR_ERR(ardbeg_vcmvdd));
231 regulator_put(ardbeg_vcmvdd);
232 ardbeg_vcmvdd = NULL;
240 static struct tegra_io_dpd csia_io = {
242 .io_dpd_reg_index = 0,
246 static struct tegra_io_dpd csib_io = {
248 .io_dpd_reg_index = 0,
252 static struct tegra_io_dpd csie_io = {
254 .io_dpd_reg_index = 1,
258 static int ardbeg_ar0261_power_on(struct ar0261_power_rail *pw)
262 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
265 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
266 tegra_io_dpd_disable(&csie_io);
268 if (ardbeg_get_extra_regulators())
269 goto ardbeg_ar0261_poweron_fail;
271 gpio_set_value(CAM_RSTN, 0);
272 gpio_set_value(CAM_AF_PWDN, 1);
275 err = regulator_enable(ardbeg_vcmvdd);
277 goto ar0261_vcm_fail;
279 err = regulator_enable(pw->dvdd);
281 goto ar0261_dvdd_fail;
283 err = regulator_enable(pw->avdd);
285 goto ar0261_avdd_fail;
287 err = regulator_enable(pw->iovdd);
289 goto ar0261_iovdd_fail;
292 gpio_set_value(CAM2_PWDN, 1);
294 gpio_set_value(CAM_RSTN, 1);
298 regulator_disable(pw->dvdd);
301 regulator_disable(pw->avdd);
304 regulator_disable(ardbeg_vcmvdd);
307 pr_err("%s vcmvdd failed.\n", __func__);
310 ardbeg_ar0261_poweron_fail:
311 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
312 tegra_io_dpd_enable(&csie_io);
313 pr_err("%s failed.\n", __func__);
317 static int ardbeg_ar0261_power_off(struct ar0261_power_rail *pw)
319 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
321 /* put CSIE IOs into DPD mode to
322 * save additional power for ardbeg
324 tegra_io_dpd_enable(&csie_io);
328 gpio_set_value(CAM_RSTN, 0);
332 regulator_disable(pw->iovdd);
333 regulator_disable(pw->dvdd);
334 regulator_disable(pw->avdd);
335 regulator_disable(ardbeg_vcmvdd);
336 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
337 tegra_io_dpd_enable(&csie_io);
341 static unsigned ar0261_estates[] = { 302, 0 };
343 struct ar0261_platform_data ardbeg_ar0261_data = {
345 .states = ar0261_estates,
346 .num_states = ARRAY_SIZE(ar0261_estates),
347 .e0_index = ARRAY_SIZE(ar0261_estates) - 1,
348 .priority = EDP_MAX_PRIO + 1,
350 .power_on = ardbeg_ar0261_power_on,
351 .power_off = ardbeg_ar0261_power_off,
352 .mclk_name = "mclk2",
355 static int ardbeg_imx135_get_extra_regulators(struct imx135_power_rail *pw)
358 pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
359 if (WARN_ON(IS_ERR(pw->ext_reg1))) {
360 pr_err("%s: can't get regulator imx135_reg1: %ld\n",
361 __func__, PTR_ERR(pw->ext_reg1));
368 pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
369 if (WARN_ON(IS_ERR(pw->ext_reg2))) {
370 pr_err("%s: can't get regulator imx135_reg2: %ld\n",
371 __func__, PTR_ERR(pw->ext_reg2));
380 static int ardbeg_imx135_power_on(struct imx135_power_rail *pw)
384 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
387 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
388 tegra_io_dpd_disable(&csia_io);
389 tegra_io_dpd_disable(&csib_io);
391 if (ardbeg_imx135_get_extra_regulators(pw))
392 goto imx135_poweron_fail;
394 err = regulator_enable(pw->ext_reg1);
396 goto imx135_ext_reg1_fail;
398 err = regulator_enable(pw->ext_reg2);
400 goto imx135_ext_reg2_fail;
403 gpio_set_value(CAM_AF_PWDN, 1);
404 gpio_set_value(CAM1_PWDN, 0);
405 usleep_range(10, 20);
407 err = regulator_enable(pw->avdd);
409 goto imx135_avdd_fail;
411 err = regulator_enable(pw->iovdd);
413 goto imx135_iovdd_fail;
416 gpio_set_value(CAM1_PWDN, 1);
418 usleep_range(300, 310);
424 regulator_disable(pw->avdd);
428 regulator_disable(pw->ext_reg2);
430 imx135_ext_reg2_fail:
432 regulator_disable(pw->ext_reg1);
433 gpio_set_value(CAM_AF_PWDN, 0);
435 imx135_ext_reg1_fail:
437 tegra_io_dpd_enable(&csia_io);
438 tegra_io_dpd_enable(&csib_io);
439 pr_err("%s failed.\n", __func__);
443 static int ardbeg_imx135_power_off(struct imx135_power_rail *pw)
445 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
446 tegra_io_dpd_enable(&csia_io);
447 tegra_io_dpd_enable(&csib_io);
451 regulator_disable(pw->iovdd);
452 regulator_disable(pw->avdd);
454 regulator_disable(pw->ext_reg1);
455 regulator_disable(pw->ext_reg2);
457 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
458 tegra_io_dpd_enable(&csia_io);
459 tegra_io_dpd_enable(&csib_io);
463 static unsigned imx135_estates[] = { 486, 0 };
465 struct imx135_platform_data ardbeg_imx135_data = {
467 .states = imx135_estates,
468 .num_states = ARRAY_SIZE(imx135_estates),
469 .e0_index = ARRAY_SIZE(imx135_estates) - 1,
470 .priority = EDP_MAX_PRIO + 1,
479 .power_on = ardbeg_imx135_power_on,
480 .power_off = ardbeg_imx135_power_off,
483 static int ardbeg_dw9718_power_on(struct dw9718_power_rail *pw)
486 pr_info("%s\n", __func__);
488 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c))
491 err = regulator_enable(pw->vdd);
493 goto dw9718_vdd_fail;
495 err = regulator_enable(pw->vdd_i2c);
497 goto dw9718_i2c_fail;
499 usleep_range(1000, 1020);
501 /* return 1 to skip the in-driver power_on sequence */
502 pr_debug("%s --\n", __func__);
506 regulator_disable(pw->vdd);
509 pr_err("%s FAILED\n", __func__);
513 static int ardbeg_dw9718_power_off(struct dw9718_power_rail *pw)
515 pr_info("%s\n", __func__);
517 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c))
520 regulator_disable(pw->vdd);
521 regulator_disable(pw->vdd_i2c);
526 static u16 dw9718_devid;
527 static int ardbeg_dw9718_detect(void *buf, size_t size)
529 dw9718_devid = 0x9718;
533 static struct nvc_focus_cap dw9718_cap = {
535 .slew_rate = 0x3A200C,
537 .focus_infinity = 200,
541 static struct dw9718_platform_data ardbeg_dw9718_data = {
542 .cfg = NVC_CFG_NODEV,
545 .dev_name = "focuser",
547 .power_on = ardbeg_dw9718_power_on,
548 .power_off = ardbeg_dw9718_power_off,
549 .detect = ardbeg_dw9718_detect,
552 /* estate values under 1000/200/0/0mA, 3.5V input */
553 static unsigned max77387_estates[] = {3500, 710, 0};
555 static struct max77387_platform_data ardbeg_max77387_pdata = {
558 .flash_trigger_mode = 1,
559 /* use ONE-SHOOT flash mode - flash triggered at the
560 * raising edge of strobe or strobe signal.
564 .max_total_current_mA = 1000,
565 .max_peak_current_mA = 600,
567 .flash_torch_ratio = 18100,
573 .flash_torch_ratio = 18100,
581 .gpio_strobe = CAM_FLASH_STROBE,
583 .states = max77387_estates,
584 .num_states = ARRAY_SIZE(max77387_estates),
585 .e0_index = ARRAY_SIZE(max77387_estates) - 1,
586 .priority = EDP_MAX_PRIO + 2,
590 static struct as364x_platform_data ardbeg_as3648_data = {
593 .max_total_current_mA = 1000,
594 .max_peak_current_mA = 600,
595 .max_torch_current_mA = 600,
596 .vin_low_v_run_mV = 3070,
600 .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
601 .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
605 .gpio_strobe = CAM_FLASH_STROBE,
608 static int ardbeg_ov7695_power_on(struct ov7695_power_rail *pw)
612 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
615 gpio_set_value(CAM2_PWDN, 0);
616 usleep_range(1000, 1020);
618 err = regulator_enable(pw->avdd);
620 goto ov7695_avdd_fail;
621 usleep_range(300, 320);
623 err = regulator_enable(pw->iovdd);
625 goto ov7695_iovdd_fail;
626 usleep_range(1000, 1020);
628 gpio_set_value(CAM2_PWDN, 1);
629 usleep_range(1000, 1020);
634 regulator_disable(pw->avdd);
638 gpio_set_value(CAM_RSTN, 0);
642 static int ardbeg_ov7695_power_off(struct ov7695_power_rail *pw)
644 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
646 usleep_range(100, 120);
648 gpio_set_value(CAM2_PWDN, 0);
649 usleep_range(100, 120);
651 regulator_disable(pw->iovdd);
652 usleep_range(100, 120);
654 regulator_disable(pw->avdd);
658 struct ov7695_platform_data ardbeg_ov7695_pdata = {
659 .power_on = ardbeg_ov7695_power_on,
660 .power_off = ardbeg_ov7695_power_off,
661 .mclk_name = "mclk2",
664 static int ardbeg_mt9m114_power_on(struct mt9m114_power_rail *pw)
667 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
670 gpio_set_value(CAM_RSTN, 0);
671 gpio_set_value(CAM2_PWDN, 1);
672 usleep_range(1000, 1020);
674 err = regulator_enable(pw->iovdd);
676 goto mt9m114_iovdd_fail;
678 err = regulator_enable(pw->avdd);
680 goto mt9m114_avdd_fail;
682 usleep_range(1000, 1020);
683 gpio_set_value(CAM_RSTN, 1);
684 gpio_set_value(CAM2_PWDN, 0);
685 usleep_range(1000, 1020);
687 /* return 1 to skip the in-driver power_on swquence */
691 regulator_disable(pw->iovdd);
694 gpio_set_value(CAM_RSTN, 0);
698 static int ardbeg_mt9m114_power_off(struct mt9m114_power_rail *pw)
700 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
703 usleep_range(100, 120);
704 gpio_set_value(CAM_RSTN, 0);
705 usleep_range(100, 120);
706 regulator_disable(pw->avdd);
707 usleep_range(100, 120);
708 regulator_disable(pw->iovdd);
713 static unsigned mt9m114_estates[] = { 150, 0 };
715 struct mt9m114_platform_data ardbeg_mt9m114_pdata = {
717 .states = mt9m114_estates,
718 .num_states = ARRAY_SIZE(mt9m114_estates),
719 .e0_index = ARRAY_SIZE(mt9m114_estates) - 1,
720 .priority = EDP_MAX_PRIO + 1,
722 .power_on = ardbeg_mt9m114_power_on,
723 .power_off = ardbeg_mt9m114_power_off,
724 .mclk_name = "mclk2",
728 static int ardbeg_ov5693_power_on(struct ov5693_power_rail *pw)
732 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
735 if (ardbeg_get_extra_regulators())
736 goto ov5693_poweron_fail;
738 gpio_set_value(CAM1_PWDN, 0);
739 usleep_range(10, 20);
741 err = regulator_enable(pw->avdd);
743 goto ov5693_avdd_fail;
745 err = regulator_enable(pw->dovdd);
747 goto ov5693_iovdd_fail;
750 gpio_set_value(CAM1_PWDN, 1);
752 err = regulator_enable(ardbeg_vcmvdd);
754 goto ov5693_vcmvdd_fail;
756 usleep_range(300, 310);
761 regulator_disable(pw->dovdd);
764 regulator_disable(pw->avdd);
767 gpio_set_value(CAM1_PWDN, 0);
770 pr_err("%s FAILED\n", __func__);
774 static int ardbeg_ov5693_power_off(struct ov5693_power_rail *pw)
776 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
779 usleep_range(21, 25);
780 gpio_set_value(CAM1_PWDN, 0);
783 regulator_disable(ardbeg_vcmvdd);
784 regulator_disable(pw->dovdd);
785 regulator_disable(pw->avdd);
790 static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
791 { OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
794 static unsigned ov5693_estates[] = { 300, 0 };
796 static struct ov5693_platform_data ardbeg_ov5693_pdata = {
798 .states = ov5693_estates,
799 .num_states = ARRAY_SIZE(ov5693_estates),
800 .e0_index = ARRAY_SIZE(ov5693_estates) - 1,
801 .priority = EDP_MAX_PRIO + 1,
803 .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
804 .gpio = ov5693_gpio_pdata,
805 .power_on = ardbeg_ov5693_power_on,
806 .power_off = ardbeg_ov5693_power_off,
809 static int ardbeg_ad5823_power_on(struct ad5823_platform_data *pdata)
813 pr_info("%s\n", __func__);
814 gpio_set_value_cansleep(pdata->gpio, 1);
819 static int ardbeg_ad5823_power_off(struct ad5823_platform_data *pdata)
821 pr_info("%s\n", __func__);
822 gpio_set_value_cansleep(pdata->gpio, 0);
827 static struct ad5823_platform_data ardbeg_ad5823_pdata = {
829 .power_on = ardbeg_ad5823_power_on,
830 .power_off = ardbeg_ad5823_power_off,
833 static struct i2c_board_info ardbeg_i2c_board_info_imx135 = {
834 I2C_BOARD_INFO("imx135", 0x10),
835 .platform_data = &ardbeg_imx135_data,
838 static struct i2c_board_info ardbeg_i2c_board_info_ar0261 = {
839 I2C_BOARD_INFO("ar0261", 0x36),
840 .platform_data = &ardbeg_ar0261_data,
843 static struct i2c_board_info ardbeg_i2c_board_info_dw9718 = {
844 I2C_BOARD_INFO("dw9718", 0x0c),
845 .platform_data = &ardbeg_dw9718_data,
848 static struct i2c_board_info ardbeg_i2c_board_info_ov5693 = {
849 I2C_BOARD_INFO("ov5693", 0x10),
850 .platform_data = &ardbeg_ov5693_pdata,
853 static struct i2c_board_info ardbeg_i2c_board_info_ov7695 = {
854 I2C_BOARD_INFO("ov7695", 0x21),
855 .platform_data = &ardbeg_ov7695_pdata,
858 static struct i2c_board_info ardbeg_i2c_board_info_mt9m114 = {
859 I2C_BOARD_INFO("mt9m114", 0x48),
860 .platform_data = &ardbeg_mt9m114_pdata,
863 static struct i2c_board_info ardbeg_i2c_board_info_ad5823 = {
864 I2C_BOARD_INFO("ad5823", 0x0c),
865 .platform_data = &ardbeg_ad5823_pdata,
868 static struct i2c_board_info ardbeg_i2c_board_info_as3648 = {
869 I2C_BOARD_INFO("as3648", 0x30),
870 .platform_data = &ardbeg_as3648_data,
873 static struct i2c_board_info ardbeg_i2c_board_info_max77387 = {
874 I2C_BOARD_INFO("max77387", 0x4A),
875 .platform_data = &ardbeg_max77387_pdata,
878 static struct camera_module ardbeg_camera_module_info[] = {
879 /* E1823 camera board */
882 .sensor = &ardbeg_i2c_board_info_imx135,
883 .focuser = &ardbeg_i2c_board_info_dw9718,
884 .flash = &ardbeg_i2c_board_info_as3648,
888 .sensor = &ardbeg_i2c_board_info_ar0261,
890 /* E1793 camera board */
893 .sensor = &ardbeg_i2c_board_info_ov5693,
894 .focuser = &ardbeg_i2c_board_info_ad5823,
895 .flash = &ardbeg_i2c_board_info_as3648,
899 .sensor = &ardbeg_i2c_board_info_ov7695,
901 /* E1806 camera board has the same rear camera module as E1793,
902 but the front camera is different */
905 .sensor = &ardbeg_i2c_board_info_mt9m114,
911 static struct camera_platform_data ardbeg_pcl_pdata = {
913 .modules = ardbeg_camera_module_info,
916 static struct platform_device ardbeg_camera_generic = {
917 .name = "pcl-generic",
921 static int ardbeg_camera_init(void)
923 pr_debug("%s: ++\n", __func__);
925 if (!of_machine_is_compatible("nvidia,tn8")) {
926 /* put CSIA/B/E IOs into DPD mode to
927 * save additional power for ardbeg
929 tegra_io_dpd_enable(&csia_io);
930 tegra_io_dpd_enable(&csib_io);
931 tegra_io_dpd_enable(&csie_io);
934 platform_device_add_data(&ardbeg_camera_generic,
935 &ardbeg_pcl_pdata, sizeof(ardbeg_pcl_pdata));
936 platform_device_register(&ardbeg_camera_generic);
938 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
939 platform_device_register(&ardbeg_soc_camera_device);
945 static struct pid_thermal_gov_params cpu_pid_params = {
946 .max_err_temp = 4000,
947 .max_err_gain = 1000,
952 .up_compensation = 15,
953 .down_compensation = 15,
956 static struct thermal_zone_params cpu_tzp = {
957 .governor_name = "pid_thermal_gov",
958 .governor_params = &cpu_pid_params,
961 static struct throttle_table cpu_throttle_table[] = {
962 /* CPU_THROT_LOW cannot be used by other than CPU */
963 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
964 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
965 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
966 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
967 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
968 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
969 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
970 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
971 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
972 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
973 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
974 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
975 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
976 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
977 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
978 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
979 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
980 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
981 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
982 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
983 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
984 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
985 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
986 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
987 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
988 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
989 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
990 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
991 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
992 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
993 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
994 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
995 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
996 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
997 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
998 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
999 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1000 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1001 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1002 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1003 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1004 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1005 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1006 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1007 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1008 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1009 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1010 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1011 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1012 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1013 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1014 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1015 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1016 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1017 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1018 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1019 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1020 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1021 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1022 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1023 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1024 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1025 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1026 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1027 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1028 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1029 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1030 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1031 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1032 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1033 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1034 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1035 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1036 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1037 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1038 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1039 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1040 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1041 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1042 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1043 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1044 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1045 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1046 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1049 static struct balanced_throttle cpu_throttle = {
1050 .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
1051 .throt_tab = cpu_throttle_table,
1054 static struct throttle_table gpu_throttle_table[] = {
1055 /* CPU_THROT_LOW cannot be used by other than CPU */
1056 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1057 { { 2295000, 782800, 480000, 756000, 384000, 924000 } },
1058 { { 2269500, 772200, 480000, 756000, 384000, 924000 } },
1059 { { 2244000, 761600, 480000, 756000, 384000, 924000 } },
1060 { { 2218500, 751100, 480000, 756000, 384000, 924000 } },
1061 { { 2193000, 740500, 480000, 756000, 384000, 924000 } },
1062 { { 2167500, 729900, 480000, 756000, 384000, 924000 } },
1063 { { 2142000, 719300, 480000, 756000, 384000, 924000 } },
1064 { { 2116500, 708700, 480000, 756000, 384000, 924000 } },
1065 { { 2091000, 698100, 480000, 756000, 384000, 924000 } },
1066 { { 2065500, 687500, 480000, 756000, 384000, 924000 } },
1067 { { 2040000, 676900, 480000, 756000, 384000, 924000 } },
1068 { { 2014500, 666000, 480000, 756000, 384000, 924000 } },
1069 { { 1989000, 656000, 480000, 756000, 384000, 924000 } },
1070 { { 1963500, 645000, 480000, 756000, 384000, 924000 } },
1071 { { 1938000, 635000, 480000, 756000, 384000, 924000 } },
1072 { { 1912500, 624000, 480000, 756000, 384000, 924000 } },
1073 { { 1887000, 613000, 480000, 756000, 384000, 924000 } },
1074 { { 1861500, 603000, 480000, 756000, 384000, 924000 } },
1075 { { 1836000, 592000, 480000, 756000, 384000, 924000 } },
1076 { { 1810500, 582000, 480000, 756000, 384000, 924000 } },
1077 { { 1785000, 571000, 480000, 756000, 384000, 924000 } },
1078 { { 1759500, 560000, 480000, 756000, 384000, 924000 } },
1079 { { 1734000, 550000, 480000, 756000, 384000, 924000 } },
1080 { { 1708500, 539000, 480000, 756000, 384000, 924000 } },
1081 { { 1683000, 529000, 480000, 756000, 384000, 924000 } },
1082 { { 1657500, 518000, 480000, 756000, 384000, 924000 } },
1083 { { 1632000, 508000, 480000, 756000, 384000, 924000 } },
1084 { { 1606500, 497000, 480000, 756000, 384000, 924000 } },
1085 { { 1581000, 486000, 480000, 756000, 384000, 924000 } },
1086 { { 1555500, 476000, 480000, 756000, 384000, 924000 } },
1087 { { 1530000, 465000, 480000, 756000, 384000, 924000 } },
1088 { { 1504500, 455000, 480000, 756000, 384000, 924000 } },
1089 { { 1479000, 444000, 480000, 756000, 384000, 924000 } },
1090 { { 1453500, 433000, 480000, 756000, 384000, 924000 } },
1091 { { 1428000, 423000, 480000, 756000, 384000, 924000 } },
1092 { { 1402500, 412000, 480000, 756000, 384000, 924000 } },
1093 { { 1377000, 402000, 480000, 756000, 384000, 924000 } },
1094 { { 1351500, 391000, 480000, 756000, 384000, 924000 } },
1095 { { 1326000, 380000, 480000, 756000, 384000, 924000 } },
1096 { { 1300500, 370000, 480000, 756000, 384000, 924000 } },
1097 { { 1275000, 359000, 480000, 756000, 384000, 924000 } },
1098 { { 1249500, 349000, 480000, 756000, 384000, 924000 } },
1099 { { 1224000, 338000, 480000, 756000, 384000, 792000 } },
1100 { { 1198500, 328000, 480000, 756000, 384000, 792000 } },
1101 { { 1173000, 317000, 480000, 756000, 360000, 792000 } },
1102 { { 1147500, 306000, 480000, 756000, 360000, 792000 } },
1103 { { 1122000, 296000, 480000, 684000, 360000, 792000 } },
1104 { { 1096500, 285000, 444000, 684000, 360000, 792000 } },
1105 { { 1071000, 275000, 444000, 684000, 360000, 792000 } },
1106 { { 1045500, 264000, 444000, 684000, 360000, 792000 } },
1107 { { 1020000, 253000, 444000, 684000, 324000, 792000 } },
1108 { { 994500, 243000, 444000, 684000, 324000, 792000 } },
1109 { { 969000, 232000, 444000, 600000, 324000, 792000 } },
1110 { { 943500, 222000, 444000, 600000, 324000, 792000 } },
1111 { { 918000, 211000, 396000, 600000, 324000, 792000 } },
1112 { { 892500, 200000, 396000, 600000, 324000, 792000 } },
1113 { { 867000, 190000, 396000, 600000, 324000, 792000 } },
1114 { { 841500, 179000, 396000, 600000, 288000, 792000 } },
1115 { { 816000, 169000, 396000, 600000, 288000, 792000 } },
1116 { { 790500, 158000, 396000, 600000, 288000, 792000 } },
1117 { { 765000, 148000, 396000, 504000, 288000, 792000 } },
1118 { { 739500, 137000, 348000, 504000, 288000, 792000 } },
1119 { { 714000, 126000, 348000, 504000, 288000, 624000 } },
1120 { { 688500, 116000, 348000, 504000, 288000, 624000 } },
1121 { { 663000, 105000, 348000, 504000, 288000, 624000 } },
1122 { { 637500, 95000, 348000, 504000, 288000, 624000 } },
1123 { { 612000, 84000, 348000, 504000, 252000, 624000 } },
1124 { { 586500, 84000, 348000, 504000, 252000, 624000 } },
1125 { { 561000, 84000, 348000, 420000, 252000, 624000 } },
1126 { { 535500, 84000, 288000, 420000, 252000, 624000 } },
1127 { { 510000, 84000, 288000, 420000, 252000, 624000 } },
1128 { { 484500, 84000, 288000, 420000, 252000, 624000 } },
1129 { { 459000, 84000, 288000, 420000, 252000, 624000 } },
1130 { { 433500, 84000, 288000, 420000, 252000, 396000 } },
1131 { { 408000, 84000, 288000, 420000, 252000, 396000 } },
1132 { { 382500, 84000, 288000, 420000, 252000, 396000 } },
1133 { { 357000, 84000, 288000, 420000, 252000, 396000 } },
1134 { { 331500, 84000, 288000, 420000, 252000, 396000 } },
1135 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1136 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1137 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1138 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1139 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1142 static struct balanced_throttle gpu_throttle = {
1143 .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
1144 .throt_tab = gpu_throttle_table,
1147 static int __init ardbeg_tj_throttle_init(void)
1149 if (of_machine_is_compatible("nvidia,ardbeg") ||
1150 of_machine_is_compatible("nvidia,tn8")) {
1151 balanced_throttle_register(&cpu_throttle, "cpu-balanced");
1152 balanced_throttle_register(&gpu_throttle, "gpu-balanced");
1157 module_init(ardbeg_tj_throttle_init);
1159 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1160 static struct thermal_trip_info skin_trips[] = {
1162 .cdev_type = "skin-balanced",
1164 .trip_type = THERMAL_TRIP_PASSIVE,
1165 .upper = THERMAL_NO_LIMIT,
1166 .lower = THERMAL_NO_LIMIT,
1171 static struct therm_est_subdevice skin_devs[] = {
1173 .dev_data = "Tdiode_tegra",
1183 .dev_data = "Tboard_tegra",
1194 static struct pid_thermal_gov_params skin_pid_params = {
1195 .max_err_temp = 4000,
1196 .max_err_gain = 1000,
1201 .up_compensation = 15,
1202 .down_compensation = 15,
1205 static struct thermal_zone_params skin_tzp = {
1206 .governor_name = "pid_thermal_gov",
1207 .governor_params = &skin_pid_params,
1210 static struct therm_est_data skin_data = {
1211 .num_trips = ARRAY_SIZE(skin_trips),
1212 .trips = skin_trips,
1214 .polling_period = 1100,
1215 .passive_delay = 15000,
1218 .ndevs = ARRAY_SIZE(skin_devs),
1223 static struct throttle_table skin_throttle_table[] = {
1224 /* CPU_THROT_LOW cannot be used by other than CPU */
1225 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1226 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1227 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1228 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1229 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1230 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1231 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1232 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1233 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1234 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1235 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1236 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1237 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1238 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1239 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1240 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1241 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1242 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1243 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1244 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1245 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1246 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1247 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1248 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1249 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1250 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1251 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1252 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1253 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1254 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1255 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1256 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1257 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1258 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1259 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1260 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1261 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1262 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1263 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1264 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1265 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1266 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1267 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1268 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1269 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1270 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1271 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1272 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1273 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1274 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1275 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1276 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1277 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1278 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1279 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1280 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1281 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1282 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1283 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1284 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1285 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1286 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1287 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1288 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1289 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1290 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1291 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1292 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1293 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1294 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1295 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1296 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1297 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1298 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1299 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1300 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1301 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1302 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1303 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1304 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1305 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1306 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1307 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1308 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1311 static struct balanced_throttle skin_throttle = {
1312 .throt_tab_size = ARRAY_SIZE(skin_throttle_table),
1313 .throt_tab = skin_throttle_table,
1316 static int __init ardbeg_skin_init(void)
1318 balanced_throttle_register(&skin_throttle, "skin-balanced");
1319 tegra_skin_therm_est_device.dev.platform_data = &skin_data;
1320 platform_device_register(&tegra_skin_therm_est_device);
1323 late_initcall(ardbeg_skin_init);
1326 static struct nct1008_platform_data ardbeg_nct72_pdata = {
1327 .loc_name = "tegra",
1329 .supported_hwrev = true,
1331 .conv_rate = 0x06, /* 4Hz conversion rate */
1333 .shutdown_ext_limit = 95, /* C */
1334 .shutdown_local_limit = 120, /* C */
1336 .passive_delay = 1000,
1342 .cdev_type = "shutdown_warning",
1344 .trip_type = THERMAL_TRIP_PASSIVE,
1345 .upper = THERMAL_NO_LIMIT,
1346 .lower = THERMAL_NO_LIMIT,
1349 .cdev_type = "cpu-balanced",
1351 .trip_type = THERMAL_TRIP_PASSIVE,
1352 .upper = THERMAL_NO_LIMIT,
1353 .lower = THERMAL_NO_LIMIT,
1359 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1360 static struct nct1008_platform_data ardbeg_nct72_tskin_pdata = {
1363 .supported_hwrev = true,
1365 .conv_rate = 0x06, /* 4Hz conversion rate */
1367 .shutdown_ext_limit = 85, /* C */
1368 .shutdown_local_limit = 120, /* C */
1370 .passive_delay = 10000,
1371 .polling_delay = 1000,
1377 .cdev_type = "skin-balanced",
1379 .trip_type = THERMAL_TRIP_PASSIVE,
1380 .upper = THERMAL_NO_LIMIT,
1381 .lower = THERMAL_NO_LIMIT,
1387 static struct i2c_board_info ardbeg_i2c_nct72_board_info[] = {
1389 I2C_BOARD_INFO("nct72", 0x4c),
1390 .platform_data = &ardbeg_nct72_pdata,
1393 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1395 I2C_BOARD_INFO("nct72", 0x4d),
1396 .platform_data = &ardbeg_nct72_tskin_pdata,
1402 static struct i2c_board_info laguna_i2c_nct72_board_info[] = {
1404 I2C_BOARD_INFO("nct72", 0x4c),
1405 .platform_data = &ardbeg_nct72_pdata,
1410 static int ardbeg_nct72_init(void)
1412 s32 base_cp, shft_cp;
1413 u32 base_ft, shft_ft;
1414 int nct72_port = TEGRA_GPIO_PI6;
1417 struct thermal_trip_info *trip_state;
1418 struct board_info board_info;
1420 tegra_get_board_info(&board_info);
1421 /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
1422 if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
1423 (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
1424 ardbeg_nct72_pdata.shutdown_ext_limit += 20;
1425 for (i = 0; i < ardbeg_nct72_pdata.num_trips; i++) {
1426 trip_state = &ardbeg_nct72_pdata.trips[i];
1427 if (!strncmp(trip_state->cdev_type, "cpu-balanced",
1428 THERMAL_NAME_LENGTH)) {
1429 trip_state->cdev_type = "_none_";
1434 tegra_platform_edp_init(ardbeg_nct72_pdata.trips,
1435 &ardbeg_nct72_pdata.num_trips,
1436 12000); /* edp temperature margin */
1437 tegra_add_tj_trips(ardbeg_nct72_pdata.trips,
1438 &ardbeg_nct72_pdata.num_trips);
1439 tegra_add_tgpu_trips(ardbeg_nct72_pdata.trips,
1440 &ardbeg_nct72_pdata.num_trips);
1443 tegra_add_cdev_trips(ardbeg_nct72_pdata.trips,
1444 &ardbeg_nct72_pdata.num_trips);
1446 ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
1448 ret = gpio_request(nct72_port, "temp_alert");
1452 ret = gpio_direction_input(nct72_port);
1454 pr_info("%s: calling gpio_free(nct72_port)", __func__);
1455 gpio_free(nct72_port);
1458 /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */
1459 if (board_info.board_id == BOARD_PM358 ||
1460 board_info.board_id == BOARD_PM359 ||
1461 board_info.board_id == BOARD_PM363)
1462 i2c_register_board_info(1, laguna_i2c_nct72_board_info,
1463 ARRAY_SIZE(laguna_i2c_nct72_board_info));
1465 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
1466 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
1471 static struct sbs_platform_data sbs_pdata = {
1472 .poll_retry_count = 100,
1473 .i2c_retry_count = 2,
1476 static struct i2c_board_info __initdata bq20z45_pdata[] = {
1478 I2C_BOARD_INFO("sbs-battery", 0x0B),
1479 .platform_data = &sbs_pdata,
1483 int __init ardbeg_sensors_init(void)
1485 struct board_info board_info;
1486 tegra_get_board_info(&board_info);
1487 /* PM363 don't have mpu 9250 mounted */
1488 /* TN8 sensors use Device Tree */
1489 if (board_info.board_id != BOARD_PM363 &&
1490 !of_machine_is_compatible("nvidia,tn8"))
1492 ardbeg_camera_init();
1493 ardbeg_nct72_init();
1495 /* TN8 don't have ALS CM32181 */
1496 if (!of_machine_is_compatible("nvidia,tn8"))
1497 i2c_register_board_info(0, ardbeg_i2c_board_info_cm32181,
1498 ARRAY_SIZE(ardbeg_i2c_board_info_cm32181));
1500 if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY)
1501 i2c_register_board_info(1, bq20z45_pdata,
1502 ARRAY_SIZE(bq20z45_pdata));