drivers/pinctrl/pinctrl-tegra124.c

   1 /*
   2  * Pinctrl data for the NVIDIA Tegra124 pinmux
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/tegra-pmc.h>
  22
  23 #include "mach/pinmux-defines.h"
  24 #include "pinctrl-tegra.h"
  25
  26 /*
  27  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  28  * These must match how the GPIO driver names/numbers its pins.
  29  */
  30 #define _GPIO(offset)                           (offset)
  31
  32 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
  33 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
  34 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
  35 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
  36 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
  37 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
  38 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
  39 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
  40 #define TEGRA_PIN_PB0                           _GPIO(8)
  41 #define TEGRA_PIN_PB1                           _GPIO(9)
  42 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
  43 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
  44 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
  45 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
  46 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
  47 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
  48 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
  49 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
  50 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
  51 #define TEGRA_PIN_PC7                           _GPIO(23)
  52 #define TEGRA_PIN_PG0                           _GPIO(48)
  53 #define TEGRA_PIN_PG1                           _GPIO(49)
  54 #define TEGRA_PIN_PG2                           _GPIO(50)
  55 #define TEGRA_PIN_PG3                           _GPIO(51)
  56 #define TEGRA_PIN_PG4                           _GPIO(52)
  57 #define TEGRA_PIN_PG5                           _GPIO(53)
  58 #define TEGRA_PIN_PG6                           _GPIO(54)
  59 #define TEGRA_PIN_PG7                           _GPIO(55)
  60 #define TEGRA_PIN_PH0                           _GPIO(56)
  61 #define TEGRA_PIN_PH1                           _GPIO(57)
  62 #define TEGRA_PIN_PH2                           _GPIO(58)
  63 #define TEGRA_PIN_PH3                           _GPIO(59)
  64 #define TEGRA_PIN_PH4                           _GPIO(60)
  65 #define TEGRA_PIN_PH5                           _GPIO(61)
  66 #define TEGRA_PIN_PH6                           _GPIO(62)
  67 #define TEGRA_PIN_PH7                           _GPIO(63)
  68 #define TEGRA_PIN_PI0                           _GPIO(64)
  69 #define TEGRA_PIN_PI1                           _GPIO(65)
  70 #define TEGRA_PIN_PI2                           _GPIO(66)
  71 #define TEGRA_PIN_PI3                           _GPIO(67)
  72 #define TEGRA_PIN_PI4                           _GPIO(68)
  73 #define TEGRA_PIN_PI5                           _GPIO(69)
  74 #define TEGRA_PIN_PI6                           _GPIO(70)
  75 #define TEGRA_PIN_PI7                           _GPIO(71)
  76 #define TEGRA_PIN_PJ0                           _GPIO(72)
  77 #define TEGRA_PIN_PJ2                           _GPIO(74)
  78 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
  79 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
  80 #define TEGRA_PIN_PJ7                           _GPIO(79)
  81 #define TEGRA_PIN_PK0                           _GPIO(80)
  82 #define TEGRA_PIN_PK1                           _GPIO(81)
  83 #define TEGRA_PIN_PK2                           _GPIO(82)
  84 #define TEGRA_PIN_PK3                           _GPIO(83)
  85 #define TEGRA_PIN_PK4                           _GPIO(84)
  86 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
  87 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
  88 #define TEGRA_PIN_PK7                           _GPIO(87)
  89 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
  90 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
  91 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
  92 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
  93 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
  94 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
  95 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
  96 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
  97 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
  98 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
  99 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
 100 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
 101 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
 102 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
 103 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
 104 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
 105 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
 106 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
 107 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
 108 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
 109 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
 110 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
 111 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
 112 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
 113 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
 114 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
 115 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
 116 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
 117 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
 118 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
 119 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
 120 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
 121 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
 122 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
 123 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
 124 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
 125 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
 126 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
 127 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
 128 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
 129 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
 130 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
 131 #define TEGRA_PIN_KB_ROW11_PS3                  _GPIO(147)
 132 #define TEGRA_PIN_KB_ROW12_PS4                  _GPIO(148)
 133 #define TEGRA_PIN_KB_ROW13_PS5                  _GPIO(149)
 134 #define TEGRA_PIN_KB_ROW14_PS6                  _GPIO(150)
 135 #define TEGRA_PIN_KB_ROW15_PS7                  _GPIO(151)
 136 #define TEGRA_PIN_KB_ROW16_PT0                  _GPIO(152)
 137 #define TEGRA_PIN_KB_ROW17_PT1                  _GPIO(153)
 138 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
 139 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
 140 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
 141 #define TEGRA_PIN_PU0                           _GPIO(160)
 142 #define TEGRA_PIN_PU1                           _GPIO(161)
 143 #define TEGRA_PIN_PU2                           _GPIO(162)
 144 #define TEGRA_PIN_PU3                           _GPIO(163)
 145 #define TEGRA_PIN_PU4                           _GPIO(164)
 146 #define TEGRA_PIN_PU5                           _GPIO(165)
 147 #define TEGRA_PIN_PU6                           _GPIO(166)
 148 #define TEGRA_PIN_PV0                           _GPIO(168)
 149 #define TEGRA_PIN_PV1                           _GPIO(169)
 150 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
 151 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
 152 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
 153 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
 154 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
 155 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
 156 #define TEGRA_PIN_DAP_MCLK1_PW4                 _GPIO(180)
 157 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
 158 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
 159 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
 160 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
 161 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
 162 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
 163 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
 164 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
 165 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
 166 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
 167 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
 168 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
 169 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
 170 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
 171 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
 172 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
 173 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
 174 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
 175 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
 176 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
 177 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
 178 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
 179 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
 180 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
 181 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
 182 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
 183 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
 184 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
 185 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
 186 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
 187 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
 188 #define TEGRA_PIN_PBB0                          _GPIO(216)
 189 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
 190 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
 191 #define TEGRA_PIN_PBB3                          _GPIO(219)
 192 #define TEGRA_PIN_PBB4                          _GPIO(220)
 193 #define TEGRA_PIN_PBB5                          _GPIO(221)
 194 #define TEGRA_PIN_PBB6                          _GPIO(222)
 195 #define TEGRA_PIN_PBB7                          _GPIO(223)
 196 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
 197 #define TEGRA_PIN_PCC1                          _GPIO(225)
 198 #define TEGRA_PIN_PCC2                          _GPIO(226)
 199 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
 200 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
 201 #define TEGRA_PIN_PEX_L0_RST_N_PDD1             _GPIO(233)
 202 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2          _GPIO(234)
 203 #define TEGRA_PIN_PEX_WAKE_N_PDD3               _GPIO(235)
 204 #define TEGRA_PIN_PEX_L1_RST_N_PDD5             _GPIO(237)
 205 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6          _GPIO(238)
 206 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
 207 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
 208 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2            _GPIO(242)
 209 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
 210 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
 211 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
 212 #define TEGRA_PIN_DP_HPD_PFF0                   _GPIO(248)
 213 #define TEGRA_PIN_USB_VBUS_EN2_PFF1             _GPIO(249)
 214 #define TEGRA_PIN_PFF2                          _GPIO(250)
 215
 216 /* All non-GPIO pins follow */
 217 #define NUM_GPIOS       (TEGRA_PIN_PFF2 + 1)
 218 #define _PIN(offset)    (NUM_GPIOS + (offset))
 219
 220 /* Non-GPIO pins */
 221 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
 222 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
 223 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
 224 #define TEGRA_PIN_GMI_CLK_LB                    _PIN(3)
 225 #define TEGRA_PIN_RESET_OUT_N                   _PIN(4)
 226 #define TEGRA_PIN_OWR                           _PIN(5)
 227 #define TEGRA_PIN_CLK_32K_IN                    _PIN(6)
 228 #define TEGRA_PIN_JTAG_RTCK                     _PIN(7)
 229 #define TEGRA_PIN_DSI_B_CLK_P                   _PIN(8)
 230 #define TEGRA_PIN_DSI_B_CLK_N                   _PIN(9)
 231 #define TEGRA_PIN_DSI_B_D0_P                    _PIN(10)
 232 #define TEGRA_PIN_DSI_B_D0_N                    _PIN(11)
 233 #define TEGRA_PIN_DSI_B_D1_P                    _PIN(12)
 234 #define TEGRA_PIN_DSI_B_D1_N                    _PIN(13)
 235 #define TEGRA_PIN_DSI_B_D2_P                    _PIN(14)
 236 #define TEGRA_PIN_DSI_B_D2_N                    _PIN(15)
 237 #define TEGRA_PIN_DSI_B_D3_P                    _PIN(16)
 238 #define TEGRA_PIN_DSI_B_D3_N                    _PIN(17)
 239
 240 static const struct pinctrl_pin_desc  tegra124_pins[] = {
 241         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 242         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 243         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 244         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 245         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 246         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 247         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 248         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 249         PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
 250         PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
 251         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 252         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 253         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 254         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 255         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 256         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 257         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 258         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 259         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 260         PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
 261         PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
 262         PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
 263         PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
 264         PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
 265         PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
 266         PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
 267         PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
 268         PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
 269         PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
 270         PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
 271         PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
 272         PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
 273         PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
 274         PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
 275         PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
 276         PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
 277         PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
 278         PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
 279         PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
 280         PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
 281         PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
 282         PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
 283         PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
 284         PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
 285         PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
 286         PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
 287         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 288         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 289         PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
 290         PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
 291         PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
 292         PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
 293         PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
 294         PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
 295         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 296         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 297         PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
 298         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 299         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 300         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 301         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 302         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
 303         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
 304         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 305         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 306         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 307         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 308         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 309         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 310         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 311         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 312         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 313         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 314         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 315         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 316         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 317         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 318         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 319         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 320         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 321         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 322         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 323         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 324         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 325         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 326         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 327         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 328         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 329         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 330         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 331         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 332         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 333         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 334         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 335         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 336         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 337         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 338         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 339         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 340         PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"),
 341         PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"),
 342         PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"),
 343         PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"),
 344         PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"),
 345         PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"),
 346         PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"),
 347         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 348         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 349         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 350         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 351         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 352         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 353         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 354         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 355         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 356         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 357         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 358         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 359         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
 360         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
 361         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 362         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 363         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
 364         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
 365         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
 366         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 367         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 368         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 369         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
 370         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
 371         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
 372         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
 373         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
 374         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
 375         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
 376         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
 377         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 378         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 379         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 380         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 381         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 382         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 383         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 384         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 385         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 386         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 387         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 388         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 389         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 390         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 391         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 392         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 393         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 394         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 395         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 396         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 397         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 398         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 399         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 400         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 401         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 402         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 403         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 404         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 405         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 406         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 407         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 408         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 409         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 410         PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
 411         PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
 412         PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
 413         PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
 414         PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
 415         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 416         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 417         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
 418         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 419         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
 420         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
 421         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 422         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 423         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 424         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 425         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
 426         PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
 427         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
 428         PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
 429         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 430         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
 431         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
 432         PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
 433         PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
 434         PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
 435         PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
 436         PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
 437         PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
 438         PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
 439         PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
 440         PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
 441         PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
 442 };
 443
 444 static const unsigned clk_32k_out_pa0_pins[] = {
 445         TEGRA_PIN_CLK_32K_OUT_PA0,
 446 };
 447
 448 static const unsigned uart3_cts_n_pa1_pins[] = {
 449         TEGRA_PIN_UART3_CTS_N_PA1,
 450 };
 451
 452 static const unsigned dap2_fs_pa2_pins[] = {
 453         TEGRA_PIN_DAP2_FS_PA2,
 454 };
 455
 456 static const unsigned dap2_sclk_pa3_pins[] = {
 457         TEGRA_PIN_DAP2_SCLK_PA3,
 458 };
 459
 460 static const unsigned dap2_din_pa4_pins[] = {
 461         TEGRA_PIN_DAP2_DIN_PA4,
 462 };
 463
 464 static const unsigned dap2_dout_pa5_pins[] = {
 465         TEGRA_PIN_DAP2_DOUT_PA5,
 466 };
 467
 468 static const unsigned sdmmc3_clk_pa6_pins[] = {
 469         TEGRA_PIN_SDMMC3_CLK_PA6,
 470 };
 471
 472 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 473         TEGRA_PIN_SDMMC3_CMD_PA7,
 474 };
 475
 476 static const unsigned pb0_pins[] = {
 477         TEGRA_PIN_PB0,
 478 };
 479
 480 static const unsigned pb1_pins[] = {
 481         TEGRA_PIN_PB1,
 482 };
 483
 484 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 485         TEGRA_PIN_SDMMC3_DAT3_PB4,
 486 };
 487
 488 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 489         TEGRA_PIN_SDMMC3_DAT2_PB5,
 490 };
 491
 492 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 493         TEGRA_PIN_SDMMC3_DAT1_PB6,
 494 };
 495
 496 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 497         TEGRA_PIN_SDMMC3_DAT0_PB7,
 498 };
 499
 500 static const unsigned uart3_rts_n_pc0_pins[] = {
 501         TEGRA_PIN_UART3_RTS_N_PC0,
 502 };
 503
 504 static const unsigned uart2_txd_pc2_pins[] = {
 505         TEGRA_PIN_UART2_TXD_PC2,
 506 };
 507
 508 static const unsigned uart2_rxd_pc3_pins[] = {
 509         TEGRA_PIN_UART2_RXD_PC3,
 510 };
 511
 512 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 513         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 514 };
 515
 516 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 517         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 518 };
 519
 520 static const unsigned pc7_pins[] = {
 521         TEGRA_PIN_PC7,
 522 };
 523
 524 static const unsigned pg0_pins[] = {
 525         TEGRA_PIN_PG0,
 526 };
 527
 528 static const unsigned pg1_pins[] = {
 529         TEGRA_PIN_PG1,
 530 };
 531
 532 static const unsigned pg2_pins[] = {
 533         TEGRA_PIN_PG2,
 534 };
 535
 536 static const unsigned pg3_pins[] = {
 537         TEGRA_PIN_PG3,
 538 };
 539
 540 static const unsigned pg4_pins[] = {
 541         TEGRA_PIN_PG4,
 542 };
 543
 544 static const unsigned pg5_pins[] = {
 545         TEGRA_PIN_PG5,
 546 };
 547
 548 static const unsigned pg6_pins[] = {
 549         TEGRA_PIN_PG6,
 550 };
 551
 552 static const unsigned pg7_pins[] = {
 553         TEGRA_PIN_PG7,
 554 };
 555
 556 static const unsigned ph0_pins[] = {
 557         TEGRA_PIN_PH0,
 558 };
 559
 560 static const unsigned ph1_pins[] = {
 561         TEGRA_PIN_PH1,
 562 };
 563
 564 static const unsigned ph2_pins[] = {
 565         TEGRA_PIN_PH2,
 566 };
 567
 568 static const unsigned ph3_pins[] = {
 569         TEGRA_PIN_PH3,
 570 };
 571
 572 static const unsigned ph4_pins[] = {
 573         TEGRA_PIN_PH4,
 574 };
 575
 576 static const unsigned ph5_pins[] = {
 577         TEGRA_PIN_PH5,
 578 };
 579
 580 static const unsigned ph6_pins[] = {
 581         TEGRA_PIN_PH6,
 582 };
 583
 584 static const unsigned ph7_pins[] = {
 585         TEGRA_PIN_PH7,
 586 };
 587
 588 static const unsigned pi0_pins[] = {
 589         TEGRA_PIN_PI0,
 590 };
 591
 592 static const unsigned pi1_pins[] = {
 593         TEGRA_PIN_PI1,
 594 };
 595
 596 static const unsigned pi2_pins[] = {
 597         TEGRA_PIN_PI2,
 598 };
 599
 600 static const unsigned pi3_pins[] = {
 601         TEGRA_PIN_PI3,
 602 };
 603
 604 static const unsigned pi4_pins[] = {
 605         TEGRA_PIN_PI4,
 606 };
 607
 608 static const unsigned pi5_pins[] = {
 609         TEGRA_PIN_PI5,
 610 };
 611
 612 static const unsigned pi6_pins[] = {
 613         TEGRA_PIN_PI6,
 614 };
 615
 616 static const unsigned pi7_pins[] = {
 617         TEGRA_PIN_PI7,
 618 };
 619
 620 static const unsigned pj0_pins[] = {
 621         TEGRA_PIN_PJ0,
 622 };
 623
 624 static const unsigned pj2_pins[] = {
 625         TEGRA_PIN_PJ2,
 626 };
 627
 628 static const unsigned uart2_cts_n_pj5_pins[] = {
 629         TEGRA_PIN_UART2_CTS_N_PJ5,
 630 };
 631
 632 static const unsigned uart2_rts_n_pj6_pins[] = {
 633         TEGRA_PIN_UART2_RTS_N_PJ6,
 634 };
 635
 636 static const unsigned pj7_pins[] = {
 637         TEGRA_PIN_PJ7,
 638 };
 639
 640 static const unsigned pk0_pins[] = {
 641         TEGRA_PIN_PK0,
 642 };
 643
 644 static const unsigned pk1_pins[] = {
 645         TEGRA_PIN_PK1,
 646 };
 647
 648 static const unsigned pk2_pins[] = {
 649         TEGRA_PIN_PK2,
 650 };
 651
 652 static const unsigned pk3_pins[] = {
 653         TEGRA_PIN_PK3,
 654 };
 655
 656 static const unsigned pk4_pins[] = {
 657         TEGRA_PIN_PK4,
 658 };
 659
 660 static const unsigned spdif_out_pk5_pins[] = {
 661         TEGRA_PIN_SPDIF_OUT_PK5,
 662 };
 663
 664 static const unsigned spdif_in_pk6_pins[] = {
 665         TEGRA_PIN_SPDIF_IN_PK6,
 666 };
 667
 668 static const unsigned pk7_pins[] = {
 669         TEGRA_PIN_PK7,
 670 };
 671
 672 static const unsigned dap1_fs_pn0_pins[] = {
 673         TEGRA_PIN_DAP1_FS_PN0,
 674 };
 675
 676 static const unsigned dap1_din_pn1_pins[] = {
 677         TEGRA_PIN_DAP1_DIN_PN1,
 678 };
 679
 680 static const unsigned dap1_dout_pn2_pins[] = {
 681         TEGRA_PIN_DAP1_DOUT_PN2,
 682 };
 683
 684 static const unsigned dap1_sclk_pn3_pins[] = {
 685         TEGRA_PIN_DAP1_SCLK_PN3,
 686 };
 687
 688 static const unsigned usb_vbus_en0_pn4_pins[] = {
 689         TEGRA_PIN_USB_VBUS_EN0_PN4,
 690 };
 691
 692 static const unsigned usb_vbus_en1_pn5_pins[] = {
 693         TEGRA_PIN_USB_VBUS_EN1_PN5,
 694 };
 695
 696 static const unsigned hdmi_int_pn7_pins[] = {
 697         TEGRA_PIN_HDMI_INT_PN7,
 698 };
 699
 700 static const unsigned ulpi_data7_po0_pins[] = {
 701         TEGRA_PIN_ULPI_DATA7_PO0,
 702 };
 703
 704 static const unsigned ulpi_data0_po1_pins[] = {
 705         TEGRA_PIN_ULPI_DATA0_PO1,
 706 };
 707
 708 static const unsigned ulpi_data1_po2_pins[] = {
 709         TEGRA_PIN_ULPI_DATA1_PO2,
 710 };
 711
 712 static const unsigned ulpi_data2_po3_pins[] = {
 713         TEGRA_PIN_ULPI_DATA2_PO3,
 714 };
 715
 716 static const unsigned ulpi_data3_po4_pins[] = {
 717         TEGRA_PIN_ULPI_DATA3_PO4,
 718 };
 719
 720 static const unsigned ulpi_data4_po5_pins[] = {
 721         TEGRA_PIN_ULPI_DATA4_PO5,
 722 };
 723
 724 static const unsigned ulpi_data5_po6_pins[] = {
 725         TEGRA_PIN_ULPI_DATA5_PO6,
 726 };
 727
 728 static const unsigned ulpi_data6_po7_pins[] = {
 729         TEGRA_PIN_ULPI_DATA6_PO7,
 730 };
 731
 732 static const unsigned dap3_fs_pp0_pins[] = {
 733         TEGRA_PIN_DAP3_FS_PP0,
 734 };
 735
 736 static const unsigned dap3_din_pp1_pins[] = {
 737         TEGRA_PIN_DAP3_DIN_PP1,
 738 };
 739
 740 static const unsigned dap3_dout_pp2_pins[] = {
 741         TEGRA_PIN_DAP3_DOUT_PP2,
 742 };
 743
 744 static const unsigned dap3_sclk_pp3_pins[] = {
 745         TEGRA_PIN_DAP3_SCLK_PP3,
 746 };
 747
 748 static const unsigned dap4_fs_pp4_pins[] = {
 749         TEGRA_PIN_DAP4_FS_PP4,
 750 };
 751
 752 static const unsigned dap4_din_pp5_pins[] = {
 753         TEGRA_PIN_DAP4_DIN_PP5,
 754 };
 755
 756 static const unsigned dap4_dout_pp6_pins[] = {
 757         TEGRA_PIN_DAP4_DOUT_PP6,
 758 };
 759
 760 static const unsigned dap4_sclk_pp7_pins[] = {
 761         TEGRA_PIN_DAP4_SCLK_PP7,
 762 };
 763
 764 static const unsigned kb_col0_pq0_pins[] = {
 765         TEGRA_PIN_KB_COL0_PQ0,
 766 };
 767
 768 static const unsigned kb_col1_pq1_pins[] = {
 769         TEGRA_PIN_KB_COL1_PQ1,
 770 };
 771
 772 static const unsigned kb_col2_pq2_pins[] = {
 773         TEGRA_PIN_KB_COL2_PQ2,
 774 };
 775
 776 static const unsigned kb_col3_pq3_pins[] = {
 777         TEGRA_PIN_KB_COL3_PQ3,
 778 };
 779
 780 static const unsigned kb_col4_pq4_pins[] = {
 781         TEGRA_PIN_KB_COL4_PQ4,
 782 };
 783
 784 static const unsigned kb_col5_pq5_pins[] = {
 785         TEGRA_PIN_KB_COL5_PQ5,
 786 };
 787
 788 static const unsigned kb_col6_pq6_pins[] = {
 789         TEGRA_PIN_KB_COL6_PQ6,
 790 };
 791
 792 static const unsigned kb_col7_pq7_pins[] = {
 793         TEGRA_PIN_KB_COL7_PQ7,
 794 };
 795
 796 static const unsigned kb_row0_pr0_pins[] = {
 797         TEGRA_PIN_KB_ROW0_PR0,
 798 };
 799
 800 static const unsigned kb_row1_pr1_pins[] = {
 801         TEGRA_PIN_KB_ROW1_PR1,
 802 };
 803
 804 static const unsigned kb_row2_pr2_pins[] = {
 805         TEGRA_PIN_KB_ROW2_PR2,
 806 };
 807
 808 static const unsigned kb_row3_pr3_pins[] = {
 809         TEGRA_PIN_KB_ROW3_PR3,
 810 };
 811
 812 static const unsigned kb_row4_pr4_pins[] = {
 813         TEGRA_PIN_KB_ROW4_PR4,
 814 };
 815
 816 static const unsigned kb_row5_pr5_pins[] = {
 817         TEGRA_PIN_KB_ROW5_PR5,
 818 };
 819
 820 static const unsigned kb_row6_pr6_pins[] = {
 821         TEGRA_PIN_KB_ROW6_PR6,
 822 };
 823
 824 static const unsigned kb_row7_pr7_pins[] = {
 825         TEGRA_PIN_KB_ROW7_PR7,
 826 };
 827
 828 static const unsigned kb_row8_ps0_pins[] = {
 829         TEGRA_PIN_KB_ROW8_PS0,
 830 };
 831
 832 static const unsigned kb_row9_ps1_pins[] = {
 833         TEGRA_PIN_KB_ROW9_PS1,
 834 };
 835
 836 static const unsigned kb_row10_ps2_pins[] = {
 837         TEGRA_PIN_KB_ROW10_PS2,
 838 };
 839
 840 static const unsigned kb_row11_ps3_pins[] = {
 841         TEGRA_PIN_KB_ROW11_PS3,
 842 };
 843
 844 static const unsigned kb_row12_ps4_pins[] = {
 845         TEGRA_PIN_KB_ROW12_PS4,
 846 };
 847
 848 static const unsigned kb_row13_ps5_pins[] = {
 849         TEGRA_PIN_KB_ROW13_PS5,
 850 };
 851
 852 static const unsigned kb_row14_ps6_pins[] = {
 853         TEGRA_PIN_KB_ROW14_PS6,
 854 };
 855
 856 static const unsigned kb_row15_ps7_pins[] = {
 857         TEGRA_PIN_KB_ROW15_PS7,
 858 };
 859
 860 static const unsigned kb_row16_pt0_pins[] = {
 861         TEGRA_PIN_KB_ROW16_PT0,
 862 };
 863
 864 static const unsigned kb_row17_pt1_pins[] = {
 865         TEGRA_PIN_KB_ROW17_PT1,
 866 };
 867
 868 static const unsigned gen2_i2c_scl_pt5_pins[] = {
 869         TEGRA_PIN_GEN2_I2C_SCL_PT5,
 870 };
 871
 872 static const unsigned gen2_i2c_sda_pt6_pins[] = {
 873         TEGRA_PIN_GEN2_I2C_SDA_PT6,
 874 };
 875
 876 static const unsigned sdmmc4_cmd_pt7_pins[] = {
 877         TEGRA_PIN_SDMMC4_CMD_PT7,
 878 };
 879
 880 static const unsigned pu0_pins[] = {
 881         TEGRA_PIN_PU0,
 882 };
 883
 884 static const unsigned pu1_pins[] = {
 885         TEGRA_PIN_PU1,
 886 };
 887
 888 static const unsigned pu2_pins[] = {
 889         TEGRA_PIN_PU2,
 890 };
 891
 892 static const unsigned pu3_pins[] = {
 893         TEGRA_PIN_PU3,
 894 };
 895
 896 static const unsigned pu4_pins[] = {
 897         TEGRA_PIN_PU4,
 898 };
 899
 900 static const unsigned pu5_pins[] = {
 901         TEGRA_PIN_PU5,
 902 };
 903
 904 static const unsigned pu6_pins[] = {
 905         TEGRA_PIN_PU6,
 906 };
 907
 908 static const unsigned pv0_pins[] = {
 909         TEGRA_PIN_PV0,
 910 };
 911
 912 static const unsigned pv1_pins[] = {
 913         TEGRA_PIN_PV1,
 914 };
 915
 916 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
 917         TEGRA_PIN_SDMMC3_CD_N_PV2,
 918 };
 919
 920 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
 921         TEGRA_PIN_SDMMC1_WP_N_PV3,
 922 };
 923
 924 static const unsigned ddc_scl_pv4_pins[] = {
 925         TEGRA_PIN_DDC_SCL_PV4,
 926 };
 927
 928 static const unsigned ddc_sda_pv5_pins[] = {
 929         TEGRA_PIN_DDC_SDA_PV5,
 930 };
 931
 932 static const unsigned gpio_w2_aud_pw2_pins[] = {
 933         TEGRA_PIN_GPIO_W2_AUD_PW2,
 934 };
 935
 936 static const unsigned gpio_w3_aud_pw3_pins[] = {
 937         TEGRA_PIN_GPIO_W3_AUD_PW3,
 938 };
 939
 940 static const unsigned dap_mclk1_pw4_pins[] = {
 941         TEGRA_PIN_DAP_MCLK1_PW4,
 942 };
 943
 944 static const unsigned clk2_out_pw5_pins[] = {
 945         TEGRA_PIN_CLK2_OUT_PW5,
 946 };
 947
 948 static const unsigned uart3_txd_pw6_pins[] = {
 949         TEGRA_PIN_UART3_TXD_PW6,
 950 };
 951
 952 static const unsigned uart3_rxd_pw7_pins[] = {
 953         TEGRA_PIN_UART3_RXD_PW7,
 954 };
 955
 956 static const unsigned dvfs_pwm_px0_pins[] = {
 957         TEGRA_PIN_DVFS_PWM_PX0,
 958 };
 959
 960 static const unsigned gpio_x1_aud_px1_pins[] = {
 961         TEGRA_PIN_GPIO_X1_AUD_PX1,
 962 };
 963
 964 static const unsigned dvfs_clk_px2_pins[] = {
 965         TEGRA_PIN_DVFS_CLK_PX2,
 966 };
 967
 968 static const unsigned gpio_x3_aud_px3_pins[] = {
 969         TEGRA_PIN_GPIO_X3_AUD_PX3,
 970 };
 971
 972 static const unsigned gpio_x4_aud_px4_pins[] = {
 973         TEGRA_PIN_GPIO_X4_AUD_PX4,
 974 };
 975
 976 static const unsigned gpio_x5_aud_px5_pins[] = {
 977         TEGRA_PIN_GPIO_X5_AUD_PX5,
 978 };
 979
 980 static const unsigned gpio_x6_aud_px6_pins[] = {
 981         TEGRA_PIN_GPIO_X6_AUD_PX6,
 982 };
 983
 984 static const unsigned gpio_x7_aud_px7_pins[] = {
 985         TEGRA_PIN_GPIO_X7_AUD_PX7,
 986 };
 987
 988 static const unsigned ulpi_clk_py0_pins[] = {
 989         TEGRA_PIN_ULPI_CLK_PY0,
 990 };
 991
 992 static const unsigned ulpi_dir_py1_pins[] = {
 993         TEGRA_PIN_ULPI_DIR_PY1,
 994 };
 995
 996 static const unsigned ulpi_nxt_py2_pins[] = {
 997         TEGRA_PIN_ULPI_NXT_PY2,
 998 };
 999
1000 static const unsigned ulpi_stp_py3_pins[] = {
1001         TEGRA_PIN_ULPI_STP_PY3,
1002 };
1003
1004 static const unsigned sdmmc1_dat3_py4_pins[] = {
1005         TEGRA_PIN_SDMMC1_DAT3_PY4,
1006 };
1007
1008 static const unsigned sdmmc1_dat2_py5_pins[] = {
1009         TEGRA_PIN_SDMMC1_DAT2_PY5,
1010 };
1011
1012 static const unsigned sdmmc1_dat1_py6_pins[] = {
1013         TEGRA_PIN_SDMMC1_DAT1_PY6,
1014 };
1015
1016 static const unsigned sdmmc1_dat0_py7_pins[] = {
1017         TEGRA_PIN_SDMMC1_DAT0_PY7,
1018 };
1019
1020 static const unsigned sdmmc1_clk_pz0_pins[] = {
1021         TEGRA_PIN_SDMMC1_CLK_PZ0,
1022 };
1023
1024 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1025         TEGRA_PIN_SDMMC1_CMD_PZ1,
1026 };
1027
1028 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1029         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1030 };
1031
1032 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1033         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1034 };
1035
1036 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1037         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1038 };
1039
1040 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1041         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1042 };
1043
1044 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1045         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1046 };
1047
1048 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1049         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1050 };
1051
1052 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1053         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1054 };
1055
1056 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1057         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1058 };
1059
1060 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1061         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1062 };
1063
1064 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1065         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1066 };
1067
1068 static const unsigned pbb0_pins[] = {
1069         TEGRA_PIN_PBB0,
1070 };
1071
1072 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1073         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1074 };
1075
1076 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1077         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1078 };
1079
1080 static const unsigned pbb3_pins[] = {
1081         TEGRA_PIN_PBB3,
1082 };
1083
1084 static const unsigned pbb4_pins[] = {
1085         TEGRA_PIN_PBB4,
1086 };
1087
1088 static const unsigned pbb5_pins[] = {
1089         TEGRA_PIN_PBB5,
1090 };
1091
1092 static const unsigned pbb6_pins[] = {
1093         TEGRA_PIN_PBB6,
1094 };
1095
1096 static const unsigned pbb7_pins[] = {
1097         TEGRA_PIN_PBB7,
1098 };
1099
1100 static const unsigned cam_mclk_pcc0_pins[] = {
1101         TEGRA_PIN_CAM_MCLK_PCC0,
1102 };
1103
1104 static const unsigned pcc1_pins[] = {
1105         TEGRA_PIN_PCC1,
1106 };
1107
1108 static const unsigned pcc2_pins[] = {
1109         TEGRA_PIN_PCC2,
1110 };
1111
1112 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1113         TEGRA_PIN_SDMMC4_CLK_PCC4,
1114 };
1115
1116 static const unsigned clk2_req_pcc5_pins[] = {
1117         TEGRA_PIN_CLK2_REQ_PCC5,
1118 };
1119
1120 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1121         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1122 };
1123
1124 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1125         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1126 };
1127
1128 static const unsigned pex_wake_n_pdd3_pins[] = {
1129         TEGRA_PIN_PEX_WAKE_N_PDD3,
1130 };
1131
1132 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1133         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1134 };
1135
1136 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1137         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1138 };
1139
1140 static const unsigned clk3_out_pee0_pins[] = {
1141         TEGRA_PIN_CLK3_OUT_PEE0,
1142 };
1143
1144 static const unsigned clk3_req_pee1_pins[] = {
1145         TEGRA_PIN_CLK3_REQ_PEE1,
1146 };
1147
1148 static const unsigned dap_mclk1_req_pee2_pins[] = {
1149         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1150 };
1151
1152 static const unsigned hdmi_cec_pee3_pins[] = {
1153         TEGRA_PIN_HDMI_CEC_PEE3,
1154 };
1155
1156 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1157         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1158 };
1159
1160 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1161         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1162 };
1163 static const unsigned dp_hpd_pff0_pins[] = {
1164         TEGRA_PIN_DP_HPD_PFF0,
1165 };
1166
1167 static const unsigned usb_vbus_en2_pff1_pins[] = {
1168         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1169 };
1170
1171 static const unsigned pff2_pins[] = {
1172         TEGRA_PIN_PFF2,
1173 };
1174
1175 static const unsigned core_pwr_req_pins[] = {
1176         TEGRA_PIN_CORE_PWR_REQ,
1177 };
1178
1179 static const unsigned cpu_pwr_req_pins[] = {
1180         TEGRA_PIN_CPU_PWR_REQ,
1181 };
1182
1183 static const unsigned owr_pins[] = {
1184         TEGRA_PIN_OWR,
1185 };
1186
1187 static const unsigned pwr_int_n_pins[] = {
1188         TEGRA_PIN_PWR_INT_N,
1189 };
1190
1191 static const unsigned reset_out_n_pins[] = {
1192         TEGRA_PIN_RESET_OUT_N,
1193 };
1194
1195 static const unsigned clk_32k_in_pins[] = {
1196         TEGRA_PIN_CLK_32K_IN,
1197 };
1198
1199 static const unsigned gmi_clk_lb_pins[] = {
1200         TEGRA_PIN_GMI_CLK_LB,
1201 };
1202
1203 static const unsigned jtag_rtck_pins[] = {
1204         TEGRA_PIN_JTAG_RTCK,
1205 };
1206
1207 static const unsigned drive_ao1_pins[] = {
1208         TEGRA_PIN_KB_ROW0_PR0,
1209         TEGRA_PIN_KB_ROW1_PR1,
1210         TEGRA_PIN_KB_ROW2_PR2,
1211         TEGRA_PIN_KB_ROW3_PR3,
1212         TEGRA_PIN_KB_ROW4_PR4,
1213         TEGRA_PIN_KB_ROW5_PR5,
1214         TEGRA_PIN_KB_ROW6_PR6,
1215         TEGRA_PIN_KB_ROW7_PR7,
1216         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1217         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1218 };
1219
1220 static const unsigned drive_ao2_pins[] = {
1221         TEGRA_PIN_CLK_32K_OUT_PA0,
1222         TEGRA_PIN_CLK_32K_IN,
1223         TEGRA_PIN_KB_COL0_PQ0,
1224         TEGRA_PIN_KB_COL1_PQ1,
1225         TEGRA_PIN_KB_COL2_PQ2,
1226         TEGRA_PIN_KB_COL3_PQ3,
1227         TEGRA_PIN_KB_COL4_PQ4,
1228         TEGRA_PIN_KB_COL5_PQ5,
1229         TEGRA_PIN_KB_COL6_PQ6,
1230         TEGRA_PIN_KB_COL7_PQ7,
1231         TEGRA_PIN_KB_ROW8_PS0,
1232         TEGRA_PIN_KB_ROW9_PS1,
1233         TEGRA_PIN_KB_ROW10_PS2,
1234         TEGRA_PIN_KB_ROW11_PS3,
1235         TEGRA_PIN_KB_ROW12_PS4,
1236         TEGRA_PIN_KB_ROW13_PS5,
1237         TEGRA_PIN_KB_ROW14_PS6,
1238         TEGRA_PIN_KB_ROW15_PS7,
1239         TEGRA_PIN_KB_ROW16_PT0,
1240         TEGRA_PIN_KB_ROW17_PT1,
1241         TEGRA_PIN_SDMMC3_CD_N_PV2,
1242         TEGRA_PIN_CORE_PWR_REQ,
1243         TEGRA_PIN_CPU_PWR_REQ,
1244         TEGRA_PIN_PWR_INT_N,
1245 };
1246
1247 static const unsigned drive_at1_pins[] = {
1248         TEGRA_PIN_PH0,
1249         TEGRA_PIN_PH1,
1250         TEGRA_PIN_PH2,
1251         TEGRA_PIN_PH3,
1252 };
1253
1254 static const unsigned drive_at2_pins[] = {
1255         TEGRA_PIN_PG0,
1256         TEGRA_PIN_PG1,
1257         TEGRA_PIN_PG2,
1258         TEGRA_PIN_PG3,
1259         TEGRA_PIN_PG4,
1260         TEGRA_PIN_PG5,
1261         TEGRA_PIN_PG6,
1262         TEGRA_PIN_PG7,
1263         TEGRA_PIN_PI0,
1264         TEGRA_PIN_PI1,
1265         TEGRA_PIN_PI3,
1266         TEGRA_PIN_PI4,
1267         TEGRA_PIN_PI7,
1268         TEGRA_PIN_PK0,
1269         TEGRA_PIN_PK2,
1270 };
1271
1272 static const unsigned drive_at3_pins[] = {
1273         TEGRA_PIN_PC7,
1274         TEGRA_PIN_PJ0,
1275 };
1276
1277 static const unsigned drive_at4_pins[] = {
1278         TEGRA_PIN_PB0,
1279         TEGRA_PIN_PB1,
1280         TEGRA_PIN_PJ0,
1281         TEGRA_PIN_PJ7,
1282         TEGRA_PIN_PK7,
1283 };
1284
1285 static const unsigned drive_at5_pins[] = {
1286         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1287         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1288 };
1289
1290 static const unsigned drive_cdev1_pins[] = {
1291         TEGRA_PIN_DAP_MCLK1_PW4,
1292         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1293 };
1294
1295 static const unsigned drive_cdev2_pins[] = {
1296         TEGRA_PIN_CLK2_OUT_PW5,
1297         TEGRA_PIN_CLK2_REQ_PCC5,
1298 };
1299
1300 static const unsigned drive_dap1_pins[] = {
1301         TEGRA_PIN_DAP1_FS_PN0,
1302         TEGRA_PIN_DAP1_DIN_PN1,
1303         TEGRA_PIN_DAP1_DOUT_PN2,
1304         TEGRA_PIN_DAP1_SCLK_PN3,
1305 };
1306
1307 static const unsigned drive_dap2_pins[] = {
1308         TEGRA_PIN_DAP2_FS_PA2,
1309         TEGRA_PIN_DAP2_SCLK_PA3,
1310         TEGRA_PIN_DAP2_DIN_PA4,
1311         TEGRA_PIN_DAP2_DOUT_PA5,
1312 };
1313
1314 static const unsigned drive_dap3_pins[] = {
1315         TEGRA_PIN_DAP3_FS_PP0,
1316         TEGRA_PIN_DAP3_DIN_PP1,
1317         TEGRA_PIN_DAP3_DOUT_PP2,
1318         TEGRA_PIN_DAP3_SCLK_PP3,
1319 };
1320
1321 static const unsigned drive_dap4_pins[] = {
1322         TEGRA_PIN_DAP4_FS_PP4,
1323         TEGRA_PIN_DAP4_DIN_PP5,
1324         TEGRA_PIN_DAP4_DOUT_PP6,
1325         TEGRA_PIN_DAP4_SCLK_PP7,
1326 };
1327
1328 static const unsigned drive_dbg_pins[] = {
1329         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1330         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1331         TEGRA_PIN_PU0,
1332         TEGRA_PIN_PU1,
1333         TEGRA_PIN_PU2,
1334         TEGRA_PIN_PU3,
1335         TEGRA_PIN_PU4,
1336         TEGRA_PIN_PU5,
1337         TEGRA_PIN_PU6,
1338 };
1339
1340 static const unsigned drive_sdio3_pins[] = {
1341         TEGRA_PIN_SDMMC3_CLK_PA6,
1342         TEGRA_PIN_SDMMC3_CMD_PA7,
1343         TEGRA_PIN_SDMMC3_DAT3_PB4,
1344         TEGRA_PIN_SDMMC3_DAT2_PB5,
1345         TEGRA_PIN_SDMMC3_DAT1_PB6,
1346         TEGRA_PIN_SDMMC3_DAT0_PB7,
1347         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1348         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1349 };
1350
1351 static const unsigned drive_spi_pins[] = {
1352         TEGRA_PIN_DVFS_PWM_PX0,
1353         TEGRA_PIN_GPIO_X1_AUD_PX1,
1354         TEGRA_PIN_DVFS_CLK_PX2,
1355         TEGRA_PIN_GPIO_X3_AUD_PX3,
1356         TEGRA_PIN_GPIO_X4_AUD_PX4,
1357         TEGRA_PIN_GPIO_X5_AUD_PX5,
1358         TEGRA_PIN_GPIO_X6_AUD_PX6,
1359         TEGRA_PIN_GPIO_X7_AUD_PX7,
1360         TEGRA_PIN_GPIO_W2_AUD_PW2,
1361         TEGRA_PIN_GPIO_W3_AUD_PW3,
1362 };
1363
1364 static const unsigned drive_uaa_pins[] = {
1365         TEGRA_PIN_ULPI_DATA0_PO1,
1366         TEGRA_PIN_ULPI_DATA1_PO2,
1367         TEGRA_PIN_ULPI_DATA2_PO3,
1368         TEGRA_PIN_ULPI_DATA3_PO4,
1369 };
1370
1371 static const unsigned drive_uab_pins[] = {
1372         TEGRA_PIN_ULPI_DATA7_PO0,
1373         TEGRA_PIN_ULPI_DATA4_PO5,
1374         TEGRA_PIN_ULPI_DATA5_PO6,
1375         TEGRA_PIN_ULPI_DATA6_PO7,
1376         TEGRA_PIN_PV0,
1377         TEGRA_PIN_PV1,
1378 };
1379
1380 static const unsigned drive_uart2_pins[] = {
1381         TEGRA_PIN_UART2_TXD_PC2,
1382         TEGRA_PIN_UART2_RXD_PC3,
1383         TEGRA_PIN_UART2_CTS_N_PJ5,
1384         TEGRA_PIN_UART2_RTS_N_PJ6,
1385 };
1386
1387 static const unsigned drive_uart3_pins[] = {
1388         TEGRA_PIN_UART3_CTS_N_PA1,
1389         TEGRA_PIN_UART3_RTS_N_PC0,
1390         TEGRA_PIN_UART3_TXD_PW6,
1391         TEGRA_PIN_UART3_RXD_PW7,
1392 };
1393
1394 static const unsigned drive_sdio1_pins[] = {
1395         TEGRA_PIN_SDMMC1_DAT3_PY4,
1396         TEGRA_PIN_SDMMC1_DAT2_PY5,
1397         TEGRA_PIN_SDMMC1_DAT1_PY6,
1398         TEGRA_PIN_SDMMC1_DAT0_PY7,
1399         TEGRA_PIN_SDMMC1_CLK_PZ0,
1400         TEGRA_PIN_SDMMC1_CMD_PZ1,
1401 };
1402
1403 static const unsigned drive_ddc_pins[] = {
1404         TEGRA_PIN_DDC_SCL_PV4,
1405         TEGRA_PIN_DDC_SDA_PV5,
1406 };
1407
1408 static const unsigned drive_gma_pins[] = {
1409         TEGRA_PIN_SDMMC4_CLK_PCC4,
1410         TEGRA_PIN_SDMMC4_CMD_PT7,
1411         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1412         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1413         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1414         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1415         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1416         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1417         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1418         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1419 };
1420
1421 static const unsigned drive_gme_pins[] = {
1422         TEGRA_PIN_PBB0,
1423         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1424         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1425         TEGRA_PIN_PBB3,
1426         TEGRA_PIN_PCC2,
1427 };
1428
1429 static const unsigned drive_gmf_pins[] = {
1430         TEGRA_PIN_PBB4,
1431         TEGRA_PIN_PBB5,
1432         TEGRA_PIN_PBB6,
1433         TEGRA_PIN_PBB7,
1434 };
1435
1436 static const unsigned drive_gmg_pins[] = {
1437         TEGRA_PIN_CAM_MCLK_PCC0,
1438 };
1439
1440 static const unsigned drive_gmh_pins[] = {
1441         TEGRA_PIN_PCC1,
1442 };
1443
1444 static const unsigned drive_owr_pins[] = {
1445         TEGRA_PIN_SDMMC3_CD_N_PV2,
1446         TEGRA_PIN_OWR,
1447 };
1448
1449 static const unsigned drive_uda_pins[] = {
1450         TEGRA_PIN_ULPI_CLK_PY0,
1451         TEGRA_PIN_ULPI_DIR_PY1,
1452         TEGRA_PIN_ULPI_NXT_PY2,
1453         TEGRA_PIN_ULPI_STP_PY3,
1454 };
1455
1456 static const unsigned drive_gpv_pins[] = {
1457         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1458         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1459         TEGRA_PIN_PEX_WAKE_N_PDD3,
1460         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1461         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1462         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1463         TEGRA_PIN_PFF2,
1464 };
1465
1466 static const unsigned drive_cec_pins[] = {
1467         TEGRA_PIN_HDMI_CEC_PEE3,
1468 };
1469
1470 static const unsigned drive_dev3_pins[] = {
1471         TEGRA_PIN_CLK3_OUT_PEE0,
1472         TEGRA_PIN_CLK3_REQ_PEE1,
1473 };
1474
1475 static const unsigned drive_at6_pins[] = {
1476         TEGRA_PIN_PK1,
1477         TEGRA_PIN_PK3,
1478         TEGRA_PIN_PK4,
1479         TEGRA_PIN_PI2,
1480         TEGRA_PIN_PI5,
1481         TEGRA_PIN_PI6,
1482         TEGRA_PIN_PH4,
1483         TEGRA_PIN_PH5,
1484         TEGRA_PIN_PH6,
1485         TEGRA_PIN_PH7,
1486 };
1487
1488 static const unsigned drive_dap5_pins[] = {
1489         TEGRA_PIN_SPDIF_IN_PK6,
1490         TEGRA_PIN_SPDIF_OUT_PK5,
1491         TEGRA_PIN_DP_HPD_PFF0,
1492 };
1493
1494 static const unsigned drive_usb_vbus_en_pins[] = {
1495         TEGRA_PIN_USB_VBUS_EN0_PN4,
1496         TEGRA_PIN_USB_VBUS_EN1_PN5,
1497 };
1498
1499 static const unsigned drive_ao3_pins[] = {
1500         TEGRA_PIN_RESET_OUT_N,
1501 };
1502
1503 static const unsigned drive_ao0_pins[] = {
1504         TEGRA_PIN_JTAG_RTCK,
1505 };
1506
1507 static const unsigned drive_hv0_pins[] = {
1508         TEGRA_PIN_HDMI_INT_PN7,
1509 };
1510
1511 static const unsigned drive_sdio4_pins[] = {
1512         TEGRA_PIN_SDMMC1_WP_N_PV3,
1513 };
1514
1515 static const unsigned drive_ao4_pins[] = {
1516         TEGRA_PIN_JTAG_RTCK,
1517 };
1518
1519 enum tegra_mux_dt {
1520         TEGRA_MUX_DT_SAFE,
1521         TEGRA_MUX_DT_BLINK,
1522         TEGRA_MUX_DT_CEC,
1523         TEGRA_MUX_DT_CLDVFS,
1524         TEGRA_MUX_DT_CLK12,
1525         TEGRA_MUX_DT_CPU,
1526         TEGRA_MUX_DT_DAP,
1527         TEGRA_MUX_DT_DAP1,
1528         TEGRA_MUX_DT_DAP2,
1529         TEGRA_MUX_DT_DEV3,
1530         TEGRA_MUX_DT_DISPLAYA,
1531         TEGRA_MUX_DT_DISPLAYA_ALT,
1532         TEGRA_MUX_DT_DISPLAYB,
1533         TEGRA_MUX_DT_DTV,
1534         TEGRA_MUX_DT_EXTPERIPH1,
1535         TEGRA_MUX_DT_EXTPERIPH2,
1536         TEGRA_MUX_DT_EXTPERIPH3,
1537         TEGRA_MUX_DT_GMI,
1538         TEGRA_MUX_DT_GMI_ALT,
1539         TEGRA_MUX_DT_HDA,
1540         TEGRA_MUX_DT_HSI,
1541         TEGRA_MUX_DT_I2C1,
1542         TEGRA_MUX_DT_I2C2,
1543         TEGRA_MUX_DT_I2C3,
1544         TEGRA_MUX_DT_I2C4,
1545         TEGRA_MUX_DT_I2CPWR,
1546         TEGRA_MUX_DT_I2S0,
1547         TEGRA_MUX_DT_I2S1,
1548         TEGRA_MUX_DT_I2S2,
1549         TEGRA_MUX_DT_I2S3,
1550         TEGRA_MUX_DT_I2S4,
1551         TEGRA_MUX_DT_IRDA,
1552         TEGRA_MUX_DT_KBC,
1553         TEGRA_MUX_DT_OWR,
1554         TEGRA_MUX_DT_PMI,
1555         TEGRA_MUX_DT_PWM0,
1556         TEGRA_MUX_DT_PWM1,
1557         TEGRA_MUX_DT_PWM2,
1558         TEGRA_MUX_DT_PWM3,
1559         TEGRA_MUX_DT_PWRON,
1560         TEGRA_MUX_DT_RESET_OUT_N,
1561         TEGRA_MUX_DT_RSVD1,
1562         TEGRA_MUX_DT_RSVD2,
1563         TEGRA_MUX_DT_RSVD3,
1564         TEGRA_MUX_DT_RSVD4,
1565         TEGRA_MUX_DT_SDMMC1,
1566         TEGRA_MUX_DT_SDMMC2,
1567         TEGRA_MUX_DT_SDMMC3,
1568         TEGRA_MUX_DT_SDMMC4,
1569         TEGRA_MUX_DT_SOC,
1570         TEGRA_MUX_DT_SPDIF,
1571         TEGRA_MUX_DT_SPI1,
1572         TEGRA_MUX_DT_SPI2,
1573         TEGRA_MUX_DT_SPI3,
1574         TEGRA_MUX_DT_SPI4,
1575         TEGRA_MUX_DT_SPI5,
1576         TEGRA_MUX_DT_SPI6,
1577         TEGRA_MUX_DT_TRACE,
1578         TEGRA_MUX_DT_UARTA,
1579         TEGRA_MUX_DT_UARTB,
1580         TEGRA_MUX_DT_UARTC,
1581         TEGRA_MUX_DT_UARTD,
1582         TEGRA_MUX_DT_ULPI,
1583         TEGRA_MUX_DT_USB,
1584         TEGRA_MUX_DT_VGP1,
1585         TEGRA_MUX_DT_VGP2,
1586         TEGRA_MUX_DT_VGP3,
1587         TEGRA_MUX_DT_VGP4,
1588         TEGRA_MUX_DT_VGP5,
1589         TEGRA_MUX_DT_VGP6,
1590         TEGRA_MUX_DT_VI,
1591         TEGRA_MUX_DT_VI_ALT1,
1592         TEGRA_MUX_DT_VI_ALT3,
1593         TEGRA_MUX_DT_VIMCLK2,
1594         TEGRA_MUX_DT_VIMCLK2_ALT,
1595         TEGRA_MUX_DT_SATA,
1596         TEGRA_MUX_DT_CCLA,
1597         TEGRA_MUX_DT_PE0,
1598         TEGRA_MUX_DT_PE,
1599         TEGRA_MUX_DT_PE1,
1600         TEGRA_MUX_DT_DP,
1601         TEGRA_MUX_DT_RTCK,
1602         TEGRA_MUX_DT_SYS,
1603         TEGRA_MUX_DT_CLK,
1604         TEGRA_MUX_DT_TMDS,
1605         TEGRA_MUX_DT_CSI,
1606         TEGRA_MUX_DT_DSI_B,
1607 };
1608
1609 static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
1610         TEGRA_PIN_DSI_B_CLK_P,
1611         TEGRA_PIN_DSI_B_CLK_N,
1612         TEGRA_PIN_DSI_B_D0_P,
1613         TEGRA_PIN_DSI_B_D0_N,
1614         TEGRA_PIN_DSI_B_D1_P,
1615         TEGRA_PIN_DSI_B_D1_N,
1616         TEGRA_PIN_DSI_B_D2_P,
1617         TEGRA_PIN_DSI_B_D2_N,
1618         TEGRA_PIN_DSI_B_D3_P,
1619         TEGRA_PIN_DSI_B_D3_N,
1620 };
1621
1622
1623 static const char * const blink_groups[] = {
1624         "clk_32k_out_pa0",
1625 };
1626
1627 static const char * const csi_groups[] = {
1628         "mipi_pad_ctrl_dsi_b",
1629 };
1630
1631 static const char * const dsi_b_groups[] = {
1632         "mipi_pad_ctrl_dsi_b",
1633 };
1634
1635
1636 static const char * const cec_groups[] = {
1637         "hdmi_cec_pee3",
1638 };
1639
1640 static const char * const cldvfs_groups[] = {
1641         "ph2",
1642         "ph3",
1643         "kb_row7_pr7",
1644         "kb_row8_ps0",
1645         "dvfs_pwm_px0",
1646         "dvfs_clk_px2",
1647 };
1648
1649 static const char * const clk12_groups[] = {
1650         "sdmmc1_wp_n_pv3",
1651         "sdmmc1_clk_pz0",
1652 };
1653
1654 static const char * const cpu_groups[] = {
1655         "cpu_pwr_req",
1656 };
1657
1658 static const char * const dap_groups[] = {
1659         "dap_mclk1_pee2",
1660         "clk2_req_pcc5",
1661 };
1662
1663 static const char * const dap1_groups[] = {
1664         "dap_mclk1_pee2",
1665 };
1666
1667 static const char * const dap2_groups[] = {
1668         "dap_mclk1_pw4",
1669         "gpio_x4_aud_px4",
1670 };
1671
1672 static const char * const dev3_groups[] = {
1673         "clk3_req_pee1",
1674 };
1675
1676 static const char * const displaya_groups[] = {
1677         "dap3_fs_pp0",
1678         "dap3_din_pp1",
1679         "dap3_dout_pp2",
1680         "ph1",
1681         "pi4",
1682         "pbb3",
1683         "pbb4",
1684         "pbb5",
1685         "kb_row3_pr3",
1686         "kb_row4_pr4",
1687         "kb_row5_pr5",
1688         "kb_row6_pr6",
1689         "kb_col3_pq3",
1690         "sdmmc3_dat2_pb5",
1691 };
1692
1693 static const char * const displaya_alt_groups[] = {
1694         "kb_row6_pr6",
1695 };
1696
1697 static const char * const displayb_groups[] = {
1698         "dap3_fs_pp0",
1699         "dap3_din_pp1",
1700         "dap3_sclk_pp3",
1701
1702         "pu3",
1703         "pu4",
1704         "pu5",
1705
1706         "pbb3",
1707         "pbb4",
1708         "pbb6",
1709
1710         "kb_row3_pr3",
1711         "kb_row4_pr4",
1712         "kb_row5_pr5",
1713         "kb_row6_pr6",
1714
1715         "sdmmc3_dat3_pb4",
1716 };
1717
1718 static const char * const dtv_groups[] = {
1719         "uart3_cts_n_pa1",
1720         "uart3_rts_n_pc0",
1721         "dap4_fs_pp4",
1722         "dap4_dout_pp6",
1723         "pi7",
1724         "ph0",
1725         "ph6",
1726         "ph7",
1727 };
1728
1729 static const char * const extperiph1_groups[] = {
1730         "dap_mclk1_pw4",
1731 };
1732
1733 static const char * const extperiph2_groups[] = {
1734         "clk2_out_pw5",
1735 };
1736
1737 static const char * const extperiph3_groups[] = {
1738         "clk3_out_pee0",
1739 };
1740
1741 static const char * const gmi_groups[] = {
1742         "uart2_cts_n_pj5",
1743         "uart2_rts_n_pj6",
1744         "uart3_txd_pw6",
1745         "uart3_rxd_pw7",
1746         "uart3_cts_n_pa1",
1747         "uart3_rts_n_pc0",
1748
1749         "pu0",
1750         "pu1",
1751         "pu2",
1752         "pu3",
1753         "pu4",
1754         "pu5",
1755         "pu6",
1756
1757         "dap4_fs_pp4",
1758         "dap4_din_pp5",
1759         "dap4_dout_pp6",
1760         "dap4_sclk_pp7",
1761
1762         "pc7",
1763
1764         "pg0",
1765         "pg1",
1766         "pg2",
1767         "pg3",
1768         "pg4",
1769         "pg5",
1770         "pg6",
1771         "pg7",
1772
1773         "ph0",
1774         "ph1",
1775         "ph2",
1776         "ph3",
1777         "ph4",
1778         "ph5",
1779         "ph6",
1780         "ph7",
1781
1782         "pi0",
1783         "pi1",
1784         "pi2",
1785         "pi3",
1786         "pi4",
1787         "pi5",
1788         "pi6",
1789         "pi7",
1790
1791         "pj0",
1792         "pj2",
1793
1794         "pk0",
1795         "pk1",
1796         "pk2",
1797         "pk3",
1798         "pk4",
1799
1800         "pj7",
1801         "pb0",
1802         "pb1",
1803         "pk7",
1804
1805         "gen2_i2c_scl_pt5",
1806         "gen2_i2c_sda_pt6",
1807
1808         "sdmmc4_dat0_paa0",
1809         "sdmmc4_dat1_paa1",
1810         "sdmmc4_dat2_paa2",
1811         "sdmmc4_dat3_paa3",
1812         "sdmmc4_dat4_paa4",
1813         "sdmmc4_dat6_paa6",
1814         "sdmmc4_dat7_paa7",
1815         "sdmmc4_clk_pcc4",
1816         "sdmmc4_cmd_pt7",
1817         "gmi_clk_lb",
1818
1819         "dap1_fs_pn0",
1820         "dap1_din_pn1",
1821         "dap1_dout_pn2",
1822         "dap1_sclk_pn3",
1823
1824         "dap2_fs_pa2",
1825         "dap2_din_pa4",
1826         "dap2_dout_pa5",
1827         "dap2_sclk_pa3",
1828
1829         "dvfs_pwm_px0",
1830         "dvfs_clk_px2",
1831         "gpio_x1_aud_px1",
1832         "gpio_x3_aud_px3",
1833         "gpio_x4_aud_px4",
1834         "gpio_x5_aud_px5",
1835         "gpio_x6_aud_px6",
1836 };
1837
1838 static const char * const gmi_alt_groups[] = {
1839         "pc7",
1840         "pk4",
1841         "pj7",
1842 };
1843
1844 static const char * const hda_groups[] = {
1845         "dap1_fs_pn0",
1846         "dap1_din_pn1",
1847         "dap1_dout_pn2",
1848         "dap1_sclk_pn3",
1849         "dap2_fs_pa2",
1850         "dap2_sclk_pa3",
1851         "dap2_din_pa4",
1852         "dap2_dout_pa5",
1853 };
1854
1855 static const char * const hsi_groups[] = {
1856         "ulpi_data0_po1",
1857         "ulpi_data1_po2",
1858         "ulpi_data2_po3",
1859         "ulpi_data3_po4",
1860         "ulpi_data4_po5",
1861         "ulpi_data5_po6",
1862         "ulpi_data6_po7",
1863         "ulpi_data7_po0",
1864 };
1865
1866 static const char * const i2c1_groups[] = {
1867         "gen1_i2c_scl_pc4",
1868         "gen1_i2c_sda_pc5",
1869         "gpio_w2_aud_pw2",
1870         "gpio_w3_aud_pw3",
1871 };
1872
1873 static const char * const i2c2_groups[] = {
1874         "gen2_i2c_scl_pt5",
1875         "gen2_i2c_sda_pt6",
1876 };
1877
1878 static const char * const i2c3_groups[] = {
1879         "spdif_in_pk6",
1880         "spdif_out_pk5",
1881         "cam_i2c_scl_pbb1",
1882         "cam_i2c_sda_pbb2",
1883 };
1884
1885 static const char * const i2c4_groups[] = {
1886         "ddc_scl_pv4",
1887         "ddc_sda_pv5",
1888 };
1889
1890 static const char * const i2cpwr_groups[] = {
1891         "pwr_i2c_scl_pz6",
1892         "pwr_i2c_sda_pz7",
1893 };
1894
1895 static const char * const i2s0_groups[] = {
1896         "dap1_fs_pn0",
1897         "dap1_din_pn1",
1898         "dap1_dout_pn2",
1899         "dap1_sclk_pn3",
1900 };
1901
1902 static const char * const i2s1_groups[] = {
1903         "dap2_fs_pa2",
1904         "dap2_sclk_pa3",
1905         "dap2_din_pa4",
1906         "dap2_dout_pa5",
1907 };
1908
1909 static const char * const i2s2_groups[] = {
1910         "dap3_fs_pp0",
1911         "dap3_din_pp1",
1912         "dap3_dout_pp2",
1913         "dap3_sclk_pp3",
1914 };
1915
1916 static const char * const i2s3_groups[] = {
1917         "dap4_fs_pp4",
1918         "dap4_din_pp5",
1919         "dap4_dout_pp6",
1920         "dap4_sclk_pp7",
1921 };
1922
1923 static const char * const i2s4_groups[] = {
1924         "pcc1",
1925         "pbb6",
1926         "pbb7",
1927         "pcc2",
1928 };
1929
1930 static const char * const irda_groups[] = {
1931         "uart2_rxd_pc3",
1932         "uart2_txd_pc2",
1933         "kb_row11_ps3",
1934         "kb_row12_ps4",
1935 };
1936
1937 static const char * const kbc_groups[] = {
1938         "kb_row0_pr0",
1939         "kb_row1_pr1",
1940         "kb_row2_pr2",
1941         "kb_row3_pr3",
1942         "kb_row4_pr4",
1943         "kb_row5_pr5",
1944         "kb_row6_pr6",
1945         "kb_row7_pr7",
1946         "kb_row8_ps0",
1947         "kb_row9_ps1",
1948         "kb_row10_ps2",
1949         "kb_row11_ps3",
1950         "kb_row12_ps4",
1951         "kb_row13_ps5",
1952         "kb_row14_ps6",
1953         "kb_row15_ps7",
1954         "kb_row16_pt0",
1955         "kb_row17_pt1",
1956
1957         "kb_col0_pq0",
1958         "kb_col1_pq1",
1959         "kb_col2_pq2",
1960         "kb_col3_pq3",
1961         "kb_col4_pq4",
1962         "kb_col5_pq5",
1963         "kb_col6_pq6",
1964         "kb_col7_pq7",
1965 };
1966
1967 static const char * const owr_groups[] = {
1968         "pu0",
1969         "kb_col4_pq4",
1970         "owr",
1971         "sdmmc3_cd_n_pv2",
1972 };
1973
1974 static const char * const pmi_groups[] = {
1975         "pwr_int_n",
1976 };
1977
1978 static const char * const pwm0_groups[] = {
1979         "sdmmc1_dat2_py5",
1980         "uart3_rts_n_pc0",
1981         "pu3",
1982         "ph0",
1983         "sdmmc3_dat3_pb4",
1984 };
1985
1986 static const char * const pwm1_groups[] = {
1987         "sdmmc1_dat1_py6",
1988         "pu4",
1989         "ph1",
1990         "sdmmc3_dat2_pb5",
1991 };
1992
1993 static const char * const pwm2_groups[] = {
1994         "pu5",
1995         "ph2",
1996         "kb_col3_pq3",
1997         "sdmmc3_dat1_pb6",
1998 };
1999
2000 static const char * const pwm3_groups[] = {
2001         "pu6",
2002         "ph3",
2003         "sdmmc3_cmd_pa7",
2004 };
2005
2006 static const char * const pwron_groups[] = {
2007         "core_pwr_req",
2008 };
2009
2010 static const char * const reset_out_n_groups[] = {
2011         "reset_out_n",
2012 };
2013
2014 static const char * const rsvd1_groups[] = {
2015         "pv0",
2016         "pv1",
2017
2018         "hdmi_int_pn7",
2019         "pu1",
2020         "pu2",
2021         "pc7",
2022         "pi7",
2023         "pk0",
2024         "pj0",
2025         "pj2",
2026         "pk2",
2027         "pi3",
2028         "pi6",
2029
2030         "pg0",
2031         "pg1",
2032         "pg2",
2033         "pg3",
2034         "pg4",
2035         "pg5",
2036         "pg6",
2037         "pg7",
2038
2039         "pi0",
2040         "pi1",
2041
2042         "gpio_x7_aud_px7",
2043
2044         "reset_out_n",
2045 };
2046
2047 static const char * const rsvd2_groups[] = {
2048         "pv0",
2049         "pv1",
2050
2051         "sdmmc1_dat0_py7",
2052         "clk2_out_pw5",
2053         "clk2_req_pcc5",
2054         "hdmi_int_pn7",
2055         "ddc_scl_pv4",
2056         "ddc_sda_pv5",
2057
2058         "uart3_txd_pw6",
2059         "uart3_rxd_pw7",
2060
2061         "gen1_i2c_scl_pc4",
2062         "gen1_i2c_sda_pc5",
2063
2064         "clk3_out_pee0",
2065         "clk3_req_pee1",
2066         "pc7",
2067         "pi5",
2068         "pj0",
2069         "pj2",
2070
2071         "pk4",
2072         "pk2",
2073         "pi3",
2074         "pi6",
2075         "pg0",
2076         "pg1",
2077         "pg5",
2078         "pg6",
2079         "pg7",
2080
2081         "ph4",
2082         "ph5",
2083         "pj7",
2084         "pb0",
2085         "pb1",
2086         "pk7",
2087         "pi0",
2088         "pi1",
2089
2090         "gen2_i2c_scl_pt5",
2091         "gen2_i2c_sda_pt6",
2092         "sdmmc4_clk_pcc4",
2093         "sdmmc4_cmd_pt7",
2094         "sdmmc4_dat7_paa7",
2095         "pcc1",
2096         "pbb6",
2097         "pbb7",
2098         "pcc2",
2099         "jtag_rtck",
2100
2101         "pwr_i2c_scl_pz6",
2102         "pwr_i2c_sda_pz7",
2103
2104         "kb_row0_pr0",
2105         "kb_row1_pr1",
2106         "kb_row2_pr2",
2107         "kb_row7_pr7",
2108         "kb_row8_ps0",
2109         "kb_row9_ps1",
2110         "kb_row10_ps2",
2111         "kb_row11_ps3",
2112         "kb_row12_ps4",
2113         "kb_row13_ps5",
2114         "kb_row14_ps6",
2115
2116         "kb_col0_pq0",
2117         "kb_col1_pq1",
2118         "kb_col2_pq2",
2119         "kb_col5_pq5",
2120         "kb_col6_pq6",
2121         "kb_col7_pq7",
2122
2123         "core_pwr_req",
2124         "cpu_pwr_req",
2125         "pwr_int_n",
2126         "clk_32k_in",
2127         "owr",
2128
2129         "spdif_in_pk6",
2130         "spdif_out_pk5",
2131         "gpio_x1_aud_px1",
2132
2133         "sdmmc3_clk_pa6",
2134         "sdmmc3_dat0_pb7",
2135
2136         "pex_l0_rst_n_pdd1",
2137         "pex_l0_clkreq_n_pdd2",
2138         "pex_wake_n_pdd3",
2139         "pex_l1_rst_n_pdd5",
2140         "pex_l1_clkreq_n_pdd6",
2141         "hdmi_cec_pee3",
2142
2143         "gpio_w2_aud_pw2",
2144         "usb_vbus_en0_pn4",
2145         "usb_vbus_en1_pn5",
2146         "sdmmc3_clk_lb_out_pee4",
2147         "sdmmc3_clk_lb_in_pee5",
2148         "gmi_clk_lb",
2149         "reset_out_n",
2150         "kb_row16_pt0",
2151         "kb_row17_pt1",
2152         "dp_hpd_pff0",
2153         "usb_vbus_en2_pff1",
2154         "pff2",
2155 };
2156
2157 static const char * const rsvd3_groups[] = {
2158         "dap3_sclk_pp3",
2159         "pv0",
2160         "pv1",
2161         "sdmmc1_clk_pz0",
2162         "clk2_out_pw5",
2163         "clk2_req_pcc5",
2164         "hdmi_int_pn7",
2165
2166         "ddc_scl_pv4",
2167         "ddc_sda_pv5",
2168
2169         "pu6",
2170
2171         "gen1_i2c_scl_pc4",
2172         "gen1_i2c_sda_pc5",
2173
2174         "dap4_din_pp5",
2175         "dap4_sclk_pp7",
2176
2177         "clk3_out_pee0",
2178         "clk3_req_pee1",
2179
2180         "sdmmc4_dat5_paa5",
2181         "gpio_pcc1",
2182         "cam_i2c_scl_pbb1",
2183         "cam_i2c_sda_pbb2",
2184         "pbb5",
2185         "pbb7",
2186         "jtag_rtck",
2187         "pwr_i2c_scl_pz6",
2188         "pwr_i2c_sda_pz7",
2189
2190         "kb_row0_pr0",
2191         "kb_row1_pr1",
2192         "kb_row2_pr2",
2193         "kb_row4_pr4",
2194         "kb_row5_pr5",
2195         "kb_row9_ps1",
2196         "kb_row10_ps2",
2197         "kb_row11_ps3",
2198         "kb_row12_ps4",
2199         "kb_row15_ps7",
2200
2201         "clk_32k_out_pa0",
2202         "core_pwr_req",
2203         "cpu_pwr_req",
2204         "pwr_int_n",
2205         "clk_32k_in",
2206         "owr",
2207
2208         "dap_mclk1_pw4",
2209         "spdif_in_pk6",
2210         "spdif_out_pk5",
2211         "sdmmc3_clk_pa6",
2212         "sdmmc3_dat0_pb7",
2213
2214         "pex_l0_rst_n_pdd1",
2215         "pex_l0_clkreq_n_pdd2",
2216         "pex_wake_n_pdd3",
2217         "pex_l1_rst_n_pdd5",
2218         "pex_l1_clkreq_n_pdd6",
2219         "hdmi_cec_pee3",
2220
2221         "sdmmc3_cd_n_pv2",
2222         "usb_vbus_en0_pn4",
2223         "usb_vbus_en1_pn5",
2224         "sdmmc3_clk_lb_out_pee4",
2225         "sdmmc3_clk_lb_in_pee5",
2226         "reset_out_n",
2227         "kb_row16_pt0",
2228         "kb_row17_pt1",
2229         "dp_hpd_pff0",
2230         "usb_vbus_en2_pff1",
2231         "pff2",
2232 };
2233
2234 static const char * const rsvd4_groups[] = {
2235         "dap3_dout_pp2",
2236         "pv0",
2237         "pv1",
2238         "sdmmc1_clk_pz0",
2239
2240         "clk2_out_pw5",
2241         "clk2_req_pcc5",
2242         "hdmi_int_pn7",
2243         "ddc_scl_pv4",
2244         "ddc_sda_pv5",
2245
2246         "uart2_rts_n_pj6",
2247         "uart2_cts_n_pj5",
2248         "uart3_txd_pw6",
2249         "uart3_rxd_pw7",
2250
2251         "pu0",
2252         "pu1",
2253         "pu2",
2254
2255         "gen1_i2c_scl_pc4",
2256         "gen1_i2c_sda_pc5",
2257
2258         "dap4_fs_pp4",
2259         "dap4_dout_pp6",
2260         "dap4_din_pp5",
2261         "dap4_sclk_pp7",
2262
2263         "clk3_out_pee0",
2264         "clk3_req_pee1",
2265
2266         "pi5",
2267         "pk1",
2268         "pk2",
2269         "pg0",
2270         "pg1",
2271         "pg2",
2272         "pg3",
2273         "ph4",
2274         "ph5",
2275         "pb0",
2276         "pb1",
2277         "pk7",
2278         "pi0",
2279         "pi1",
2280         "pi2",
2281
2282         "gen2_i2c_scl_pt5",
2283         "gen2_i2c_sda_pt6",
2284
2285         "sdmmc4_cmd_pt7",
2286         "sdmmc4_dat0_paa0",
2287         "sdmmc4_dat1_paa1",
2288         "sdmmc4_dat2_paa2",
2289         "sdmmc4_dat3_paa3",
2290         "sdmmc4_dat4_paa4",
2291         "sdmmc4_dat5_paa5",
2292         "sdmmc4_dat6_paa6",
2293         "sdmmc4_dat7_paa7",
2294
2295         "jtag_rtck",
2296         "pwr_i2c_scl_pz6",
2297         "pwr_i2c_sda_pz7",
2298
2299         "kb_row0_pr0",
2300         "kb_row1_pr1",
2301         "kb_row2_pr2",
2302         "kb_row13_ps5",
2303         "kb_row14_ps6",
2304         "kb_row15_ps7",
2305
2306         "kb_col0_pq0",
2307         "kb_col1_pq1",
2308         "kb_col2_pq2",
2309         "kb_col5_pq5",
2310
2311         "clk_32k_out_pa0",
2312         "core_pwr_req",
2313         "cpu_pwr_req",
2314         "pwr_int_n",
2315         "clk_32k_in",
2316         "owr",
2317
2318         "dap1_fs_pn0",
2319         "dap1_din_pn1",
2320         "dap1_sclk_pn3",
2321         "dap_mclk1_req_pee2",
2322         "dap_mclk1_pw5",
2323
2324         "dap2_fs_pa2",
2325         "dap2_din_pa4",
2326         "dap2_dout_pa5",
2327         "dap2_sclk_pa3",
2328
2329         "dvfs_pwm_px0",
2330         "dvfs_clk_px2",
2331         "gpio_x1_aud_px1",
2332         "gpio_x3_aud_px3",
2333
2334         "gpio_x5_aud_px5",
2335         "gpio_x7_aud_px7",
2336
2337         "pex_l0_rst_n_pdd1",
2338         "pex_l0_clkreq_n_pdd2",
2339         "pex_wake_n_pdd3",
2340         "pex_l1_rst_n_pdd5",
2341         "pex_l1_clkreq_n_pdd6",
2342         "hdmi_cec_pee3",
2343
2344         "sdmmc3_cd_n_pv2",
2345         "usb_vbus_en0_pn4",
2346         "usb_vbus_en1_pn5",
2347         "sdmmc3_clk_lb_out_pee4",
2348         "sdmmc3_clk_lb_in_pee5",
2349         "gmi_clk_lb",
2350
2351         "dp_hpd_pff0",
2352         "usb_vbus_en2_pff1",
2353         "pff2",
2354 };
2355
2356 static const char * const sdmmc1_groups[] = {
2357         "sdmmc1_clk_pz0",
2358         "sdmmc1_cmd_pz1",
2359         "sdmmc1_dat3_py4",
2360         "sdmmc1_dat2_py5",
2361         "sdmmc1_dat1_py6",
2362         "sdmmc1_dat0_py7",
2363         "clk2_out_pw5",
2364         "clk2_req_pcc",
2365         "uart3_cts_n_pa1",
2366         "sdmmc1_wp_n_pv3",
2367 };
2368
2369 static const char * const sdmmc2_groups[] = {
2370         "pi5",
2371         "pk1",
2372         "pk3",
2373         "pk4",
2374         "pi6",
2375         "ph4",
2376         "ph5",
2377         "ph6",
2378         "ph7",
2379         "pi2",
2380         "cam_mclk_pcc0",
2381         "pcc1",
2382         "pbb0",
2383         "cam_i2c_scl_pbb1",
2384         "cam_i2c_sda_pbb2",
2385         "pbb3",
2386         "pbb4",
2387         "pbb5",
2388         "pbb6",
2389         "pbb7",
2390         "pcc2",
2391         "gmi_clk_lb",
2392 };
2393
2394 static const char * const sdmmc3_groups[] = {
2395         "pk0",
2396         "pcc2",
2397
2398         "kb_col4_pq4",
2399         "kb_col5_pq5",
2400
2401         "sdmmc3_clk_pa6",
2402         "sdmmc3_cmd_pa7",
2403         "sdmmc3_dat0_pb7",
2404         "sdmmc3_dat1_pb6",
2405         "sdmmc3_dat2_pb5",
2406         "sdmmc3_dat3_pb4",
2407
2408         "sdmmc3_cd_n_pv2",
2409         "sdmmc3_clk_lb_in_pee5",
2410         "sdmmc3_clk_lb_out_pee4",
2411 };
2412
2413 static const char * const sdmmc4_groups[] = {
2414         "sdmmc4_clk_pcc4",
2415         "sdmmc4_cmd_pt7",
2416         "sdmmc4_dat0_paa0",
2417         "sdmmc4_dat1_paa1",
2418         "sdmmc4_dat2_paa2",
2419         "sdmmc4_dat3_paa3",
2420         "sdmmc4_dat4_paa4",
2421         "sdmmc4_dat5_paa5",
2422         "sdmmc4_dat6_paa6",
2423         "sdmmc4_dat7_paa7",
2424 };
2425
2426 static const char * const soc_groups[] = {
2427         "pk0",
2428         "pj2",
2429         "kb_row15_ps7",
2430         "clk_32k_out_pa0",
2431 };
2432
2433 static const char * const spdif_groups[] = {
2434         "sdmmc1_cmd_pz1",
2435         "sdmmc1_dat3_py4",
2436         "uart2_rxd_pc3",
2437         "uart2_txd_pc2",
2438         "spdif_in_pk6",
2439         "spdif_out_pk5",
2440 };
2441
2442 static const char * const spi1_groups[] = {
2443         "ulpi_clk_py0",
2444         "ulpi_dir_py1",
2445         "ulpi_nxt_py2",
2446         "ulpi_stp_py3",
2447         "gpio_x3_aud_px3",
2448         "gpio_x4_aud_px4",
2449         "gpio_x5_aud_px5",
2450         "gpio_x6_aud_px6",
2451         "gpio_x7_aud_px7",
2452         "gpio_w3_aud_pw3",
2453 };
2454
2455 static const char * const spi2_groups[] = {
2456         "ulpi_data4_po5",
2457         "ulpi_data5_po6",
2458         "ulpi_data6_po7",
2459         "ulpi_data7_po0",
2460
2461         "kb_row13_ps5",
2462         "kb_row14_ps6",
2463         "kb_row15_ps7",
2464         "kb_col0_pq0",
2465         "kb_col1_pq1",
2466         "kb_col2_pq2",
2467         "kb_col6_pq6",
2468         "kb_col7_pq7",
2469         "gpio_x4_aud_px4",
2470         "gpio_x5_aud_px5",
2471         "gpio_x6_aud_px6",
2472         "gpio_x7_aud_px7",
2473         "gpio_w2_aud_pw2",
2474         "gpio_w3_aud_pw3",
2475 };
2476
2477 static const char * const spi3_groups[] = {
2478         "ulpi_data0_po1",
2479         "ulpi_data1_po2",
2480         "ulpi_data2_po3",
2481         "ulpi_data3_po4",
2482         "sdmmc4_dat0_paa0",
2483         "sdmmc4_dat1_paa1",
2484         "sdmmc4_dat2_paa2",
2485         "sdmmc4_dat3_paa3",
2486         "sdmmc4_dat4_paa4",
2487         "sdmmc4_dat5_paa5",
2488         "sdmmc4_dat6_paa6",
2489         "sdmmc3_clk_pa6",
2490         "sdmmc3_cmd_pa7",
2491         "sdmmc3_dat0_pb7",
2492         "sdmmc3_dat1_pb6",
2493         "sdmmc3_dat2_pb5",
2494         "sdmmc3_dat3_pb4",
2495 };
2496
2497 static const char * const spi4_groups[] = {
2498         "sdmmc1_cmd_pz1",
2499         "sdmmc1_dat3_py4",
2500         "sdmmc1_dat2_py5",
2501         "sdmmc1_dat1_py6",
2502         "sdmmc1_dat0_py7",
2503
2504         "uart2_rxd_pc3",
2505         "uart2_txd_pc2",
2506         "uart2_rts_n_pj6",
2507         "uart2_cts_n_pj5",
2508         "uart3_txd_pw6",
2509         "uart3_rxd_pw7",
2510
2511         "pi3",
2512         "pg4",
2513         "pg5",
2514         "pg6",
2515         "pg7",
2516         "ph3",
2517         "pi4",
2518         "sdmmc1_wp_n_pv3",
2519 };
2520
2521 static const char * const spi5_groups[] = {
2522         "ulpi_clk_py0",
2523         "ulpi_dir_py1",
2524         "ulpi_nxt_py2",
2525         "ulpi_stp_py3",
2526         "dap3_fs_pp0",
2527         "dap3_din_pp1",
2528         "dap3_dout_pp2",
2529         "dap3_sclk_pp3",
2530 };
2531
2532 static const char * const spi6_groups[] = {
2533         "dvfs_pwm_px0",
2534         "gpio_x1_aud_px1",
2535         "gpio_x3_aud_px3",
2536         "dvfs_clk_px2",
2537         "gpio_x6_aud_px6",
2538         "gpio_w2_aud_pw2",
2539         "gpio_w3_aud_pw3",
2540 };
2541
2542 static const char * const trace_groups[] = {
2543         "pi2",
2544         "pi4",
2545         "pi7",
2546         "ph0",
2547         "ph6",
2548         "ph7",
2549         "pg2",
2550         "pg3",
2551         "pk1",
2552         "pk3",
2553 };
2554
2555 static const char * const uarta_groups[] = {
2556         "ulpi_data0_po1",
2557         "ulpi_data1_po2",
2558         "ulpi_data2_po3",
2559         "ulpi_data3_po4",
2560         "ulpi_data4_po5",
2561         "ulpi_data5_po6",
2562         "ulpi_data6_po7",
2563         "ulpi_data7_po0",
2564
2565         "sdmmc1_cmd_pz1",
2566         "sdmmc1_dat3_py4",
2567         "sdmmc1_dat2_py5",
2568         "sdmmc1_dat1_py6",
2569         "sdmmc1_dat0_py7",
2570
2571
2572         "uart2_rxd_pc3",
2573         "uart2_txd_pc2",
2574         "uart2_rts_n_pj6",
2575         "uart2_cts_n_pj5",
2576
2577         "pu0",
2578         "pu1",
2579         "pu2",
2580         "pu3",
2581         "pu4",
2582         "pu5",
2583         "pu6",
2584
2585         "kb_row7_pr7",
2586         "kb_row8_ps0",
2587         "kb_row9_ps1",
2588         "kb_row10_ps2",
2589         "kb_col3_pq3",
2590         "kb_col4_pq4",
2591
2592         "sdmmc3_cmd_pa7",
2593         "sdmmc3_dat1_pb6",
2594         "sdmmc1_wp_n_pv3",
2595
2596 };
2597
2598 static const char * const uartb_groups[] = {
2599         "uart2_rts_n_pj6",
2600         "uart2_cts_n_pj5",
2601 };
2602
2603 static const char * const uartc_groups[] = {
2604         "uart3_txd_pw6",
2605         "uart3_rxd_pw7",
2606         "uart3_cts_n_pa1",
2607         "uart3_rts_n_pc0",
2608         "kb_row16_pt0",
2609         "kn_row17_pt1",
2610 };
2611
2612 static const char * const uartd_groups[] = {
2613         "ulpi_clk_py0",
2614         "ulpi_dir_py1",
2615         "ulpi_nxt_py2",
2616         "ulpi_stp_py3",
2617         "pj7",
2618         "pb0",
2619         "pb1",
2620         "pk7",
2621         "kb_col6_pq6",
2622         "kb_col7_pq7",
2623 };
2624
2625 static const char * const ulpi_groups[] = {
2626         "ulpi_data0_po1",
2627         "ulpi_data1_po2",
2628         "ulpi_data2_po3",
2629         "ulpi_data3_po4",
2630         "ulpi_data4_po5",
2631         "ulpi_data5_po6",
2632         "ulpi_data6_po7",
2633         "ulpi_data7_po0",
2634         "ulpi_clk_py0",
2635         "ulpi_dir_py1",
2636         "ulpi_nxt_py2",
2637         "ulpi_stp_py3",
2638 };
2639
2640 static const char * const usb_groups[] = {
2641         "pj0",
2642         "usb_vbus_en0_pn4",
2643         "usb_vbus_en1_pn5",
2644         "usb_vbus_en2_pff1",
2645 };
2646
2647 static const char * const vgp1_groups[] = {
2648         "cam_i2c_scl_pbb1",
2649 };
2650
2651 static const char * const vgp2_groups[] = {
2652         "cam_i2c_sda_pbb2",
2653 };
2654
2655 static const char * const vgp3_groups[] = {
2656         "pbb3",
2657 };
2658
2659 static const char * const vgp4_groups[] = {
2660         "pbb4",
2661 };
2662
2663 static const char * const vgp5_groups[] = {
2664         "pbb5",
2665 };
2666
2667 static const char * const vgp6_groups[] = {
2668         "pbb0",
2669 };
2670
2671 static const char * const vi_groups[] = {
2672         "cam_mclk_pcc0",
2673 };
2674
2675 static const char * const vi_alt1_groups[] = {
2676         "cam_mclk_pcc0",
2677 };
2678
2679 static const char * const vi_alt3_groups[] = {
2680         "cam_mclk_pcc0",
2681 };
2682
2683 static const char * const vimclk2_groups[] = {
2684         "pbb0",
2685 };
2686
2687 static const char * const vimclk2_alt_groups[] = {
2688         "pbb0",
2689 };
2690
2691 static const char * const sata_groups[] = {
2692         "dap_mclk1_req_pee2",
2693         "dap1_dout_pn2",
2694         "pff2",
2695 };
2696
2697 static const char * const ccla_groups[] = {
2698         "pk3",
2699 };
2700
2701 static const char * const rtck_groups[] = {
2702         "jtag_rtck",
2703 };
2704
2705 static const char * const sys_groups[] = {
2706         "kb_row3_pr3",
2707 };
2708
2709 static const char * const pe0_groups[] = {
2710         "pex_l0_rst_n_pdd1",
2711         "pex_l0_clkreq_n_pdd2",
2712 };
2713
2714 static const char * const pe_groups[] = {
2715         "pex_wake_n_pdd3",
2716 };
2717
2718 static const char * const pe1_groups[] = {
2719         "pex_l1_rst_n_pdd5",
2720         "pex_l1_clkreq_n_pdd6",
2721 };
2722
2723 static const char * const dp_groups[] = {
2724         "dp_hpd_pff0",
2725 };
2726
2727 static const char * const clk_groups[] = {
2728         "clk_32k_in",
2729 };
2730
2731 static const char * const tmds_groups[] = {
2732         "pg4",
2733         "ph1",
2734         "ph2",
2735 };
2736
2737 static const char * const safe_groups[] = {
2738         "ulpi_data0_po1",
2739         "ulpi_data1_po2",
2740         "ulpi_data2_po3",
2741         "ulpi_data3_po4",
2742         "ulpi_data4_po5",
2743         "ulpi_data5_po6",
2744         "ulpi_data6_po7",
2745         "ulpi_data7_po0",
2746         "ulpi_clk_py0",
2747         "ulpi_dir_py1",
2748         "ulpi_nxt_py2",
2749         "ulpi_stp_py3",
2750         "dap3_fs_pp0",
2751         "dap3_din_pp1",
2752         "dap3_dout_pp2",
2753         "dap3_sclk_pp3",
2754         "pv0",
2755         "pv1",
2756         "sdmmc1_clk_pz0",
2757         "sdmmc1_cmd_pz1",
2758         "sdmmc1_dat3_py4",
2759         "sdmmc1_dat2_py5",
2760         "sdmmc1_dat1_py6",
2761         "sdmmc1_dat0_py7",
2762         "clk2_out_pw5",
2763         "clk2_req_pcc5",
2764         "hdmi_int_pn7",
2765         "ddc_scl_pv4",
2766         "ddc_sda_pv5",
2767         "uart2_rxd_pc3",
2768         "uart2_txd_pc2",
2769         "uart2_rts_n_pj6",
2770         "uart2_cts_n_pj5",
2771         "uart3_txd_pw6",
2772         "uart3_rxd_pw7",
2773         "uart3_cts_n_pa1",
2774         "uart3_rts_n_pc0",
2775         "pu0",
2776         "pu1",
2777         "pu2",
2778         "pu3",
2779         "pu4",
2780         "pu5",
2781         "pu6",
2782         "gen1_i2c_scl_pc4",
2783         "gen1_i2c_sda_pc5",
2784         "dap4_fs_pp4",
2785         "dap4_din_pp5",
2786         "dap4_dout_pp6",
2787         "dap4_sclk_pp7",
2788         "clk3_out_pee0",
2789         "clk3_req_pee1",
2790         "pc7",
2791         "pi5",
2792         "pi7",
2793         "pk0",
2794         "pk1",
2795         "pj0",
2796         "pj2",
2797         "pk3",
2798         "pk4",
2799         "pk2",
2800         "pi3",
2801         "pi6",
2802         "pg0",
2803         "pg1",
2804         "pg2",
2805         "pg3",
2806         "pg4",
2807         "pg5",
2808         "pg6",
2809         "pg7",
2810         "ph0",
2811         "ph1",
2812         "ph2",
2813         "ph3",
2814         "ph4",
2815         "ph5",
2816         "ph6",
2817         "ph7",
2818         "pj7",
2819         "pb0",
2820         "pb1",
2821         "pk7",
2822         "pi0",
2823         "pi1",
2824         "pi2",
2825         "pi4",
2826         "gen2_i2c_scl_pt5",
2827         "gen2_i2c_sda_pt6",
2828         "sdmmc4_clk_pcc4",
2829         "sdmmc4_cmd_pt7",
2830         "sdmmc4_dat0_paa0",
2831         "sdmmc4_dat1_paa1",
2832         "sdmmc4_dat2_paa2",
2833         "sdmmc4_dat3_paa3",
2834         "sdmmc4_dat4_paa4",
2835         "sdmmc4_dat5_paa5",
2836         "sdmmc4_dat6_paa6",
2837         "sdmmc4_dat7_paa7",
2838         "cam_mclk_pcc0",
2839         "pcc1",
2840         "pbb0",
2841         "cam_i2c_scl_pbb1",
2842         "cam_i2c_sda_pbb2",
2843         "pbb3",
2844         "pbb4",
2845         "pbb5",
2846         "pbb6",
2847         "pbb7",
2848         "pcc2",
2849         "jtag_rtck",
2850         "pwr_i2c_scl_pz6",
2851         "pwr_i2c_sda_pz7",
2852         "kb_row0_pr0",
2853         "kb_row1_pr1",
2854         "kb_row2_pr2",
2855         "kb_row3_pr3",
2856         "kb_row4_pr4",
2857         "kb_row5_pr5",
2858         "kb_row6_pr6",
2859         "kb_row7_pr7",
2860         "kb_row8_ps0",
2861         "kb_row9_ps1",
2862         "kb_row10_ps2",
2863         "kb_row11_ps3",
2864         "kb_row12_ps4",
2865         "kb_row13_ps5",
2866         "kb_row14_ps6",
2867         "kb_row15_ps7",
2868         "kb_col0_pq0",
2869         "kb_col1_pq1",
2870         "kb_col2_pq2",
2871         "kb_col3_pq3",
2872         "kb_col4_pq4",
2873         "kb_col5_pq5",
2874         "kb_col6_pq6",
2875         "kb_col7_pq7",
2876         "clk_32k_out_pa0",
2877         "core_pwr_req",
2878         "cpu_pwr_req",
2879         "pwr_int_n",
2880         "clk_32k_in",
2881         "owr",
2882         "dap1_fs_pn0",
2883         "dap1_din_pn1",
2884         "dap1_dout_pn2",
2885         "dap1_sclk_pn3",
2886         "dap_mclk1_req_pee2",
2887         "dap_mclk1_pw4",
2888         "spdif_in_pk6",
2889         "spdif_out_pk5",
2890         "dap2_fs_pa2",
2891         "dap2_din_pa4",
2892         "dap2_dout_pa5",
2893         "dap2_sclk_pa3",
2894         "dvfs_pwm_px0",
2895         "gpio_x1_aud_px1",
2896         "gpio_x3_aud_px3",
2897         "dvfs_clk_px2",
2898         "gpio_x4_aud_px4",
2899         "gpio_x5_aud_px5",
2900         "gpio_x6_aud_px6",
2901         "gpio_x7_aud_px7",
2902         "sdmmc3_clk_pa6",
2903         "sdmmc3_cmd_pa7",
2904         "sdmmc3_dat0_pb7",
2905         "sdmmc3_dat1_pb6",
2906         "sdmmc3_dat2_pb5",
2907         "sdmmc3_dat3_pb4",
2908         "pex_l0_rst_n_pdd1",
2909         "pex_l0_clkreq_n_pdd2",
2910         "pex_wake_n_pdd3",
2911         "pex_l1_rst_n_pdd5",
2912         "pex_l1_clkreq_n_pdd6",
2913         "hdmi_cec_pee3",
2914         "sdmmc1_wp_n_pv3",
2915         "sdmmc3_cd_n_pv2",
2916         "gpio_w2_aud_pw2",
2917         "gpio_w3_aud_pw3",
2918         "usb_vbus_en0_pn4",
2919         "usb_vbus_en1_pn5",
2920         "sdmmc3_clk_lb_out_pee4",
2921         "sdmmc3_clk_lb_in_pee5",
2922         "gmi_clk_lb",
2923         "reset_out_n",
2924         "kb_row16_pt0",
2925         "kb_row17_pt1",
2926         "usb_vbus_en2_pff1",
2927         "pff2",
2928         "dp_hpd_pff0",
2929 };
2930
2931 #define FUNCTION(fname)                                 \
2932         {                                               \
2933                 .name = #fname,                         \
2934                 .groups = fname##_groups,               \
2935                 .ngroups = ARRAY_SIZE(fname##_groups),  \
2936         }
2937
2938 static const struct tegra_function tegra124_functions[] = {
2939         FUNCTION(safe),
2940         FUNCTION(blink),
2941         FUNCTION(cec),
2942         FUNCTION(cldvfs),
2943         FUNCTION(clk12),
2944         FUNCTION(cpu),
2945         FUNCTION(dap),
2946         FUNCTION(dap1),
2947         FUNCTION(dap2),
2948         FUNCTION(dev3),
2949         FUNCTION(displaya),
2950         FUNCTION(displaya_alt),
2951         FUNCTION(displayb),
2952         FUNCTION(dtv),
2953         FUNCTION(extperiph1),
2954         FUNCTION(extperiph2),
2955         FUNCTION(extperiph3),
2956         FUNCTION(gmi),
2957         FUNCTION(gmi_alt),
2958         FUNCTION(hda),
2959         FUNCTION(hsi),
2960         FUNCTION(i2c1),
2961         FUNCTION(i2c2),
2962         FUNCTION(i2c3),
2963         FUNCTION(i2c4),
2964         FUNCTION(i2cpwr),
2965         FUNCTION(i2s0),
2966         FUNCTION(i2s1),
2967         FUNCTION(i2s2),
2968         FUNCTION(i2s3),
2969         FUNCTION(i2s4),
2970         FUNCTION(irda),
2971         FUNCTION(kbc),
2972         FUNCTION(owr),
2973         FUNCTION(pmi),
2974         FUNCTION(pwm0),
2975         FUNCTION(pwm1),
2976         FUNCTION(pwm2),
2977         FUNCTION(pwm3),
2978         FUNCTION(pwron),
2979         FUNCTION(reset_out_n),
2980         FUNCTION(rsvd1),
2981         FUNCTION(rsvd2),
2982         FUNCTION(rsvd3),
2983         FUNCTION(rsvd4),
2984         FUNCTION(sdmmc1),
2985         FUNCTION(sdmmc2),
2986         FUNCTION(sdmmc3),
2987         FUNCTION(sdmmc4),
2988         FUNCTION(soc),
2989         FUNCTION(spdif),
2990         FUNCTION(spi1),
2991         FUNCTION(spi2),
2992         FUNCTION(spi3),
2993         FUNCTION(spi4),
2994         FUNCTION(spi5),
2995         FUNCTION(spi6),
2996         FUNCTION(trace),
2997         FUNCTION(uarta),
2998         FUNCTION(uartb),
2999         FUNCTION(uartc),
3000         FUNCTION(uartd),
3001         FUNCTION(ulpi),
3002         FUNCTION(usb),
3003         FUNCTION(vgp1),
3004         FUNCTION(vgp2),
3005         FUNCTION(vgp3),
3006         FUNCTION(vgp4),
3007         FUNCTION(vgp5),
3008         FUNCTION(vgp6),
3009         FUNCTION(vi),
3010         FUNCTION(vi_alt1),
3011         FUNCTION(vi_alt3),
3012         FUNCTION(vimclk2),
3013         FUNCTION(vimclk2_alt),
3014         FUNCTION(sata),
3015         FUNCTION(ccla),
3016         FUNCTION(pe0),
3017         FUNCTION(pe),
3018         FUNCTION(pe1),
3019         FUNCTION(dp),
3020         FUNCTION(rtck),
3021         FUNCTION(sys),
3022         FUNCTION(clk),
3023         FUNCTION(tmds),
3024         FUNCTION(csi),
3025         FUNCTION(dsi_b),
3026 };
3027
3028 #define DRV_PINGROUP_REG_A      0x868   /* bank 0 */
3029 #define PINGROUP_REG_A          0x3000  /* bank 1 */
3030 #define MIPI_PAD_CTRL_PINGROUP_REG_A   0x820   /* bank 2 */
3031
3032 #define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
3033 #define PINGROUP_REG_N(r) -1
3034
3035 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel)  \
3036         {                                                       \
3037                 .name = #pg_name,                               \
3038                 .pins = pg_name##_pins,                         \
3039                 .npins = ARRAY_SIZE(pg_name##_pins),            \
3040                 .funcs = {                                      \
3041                         TEGRA_MUX_DT_ ## f0,                    \
3042                         TEGRA_MUX_DT_ ## f1,                    \
3043                         TEGRA_MUX_DT_ ## f2,                    \
3044                         TEGRA_MUX_DT_ ## f3,                    \
3045                 },                                              \
3046                 .func_safe = TEGRA_MUX_DT_ ## f_safe,           \
3047                 .funcs_non_dt = {                               \
3048                         TEGRA_MUX_ ## f0,                       \
3049                         TEGRA_MUX_ ## f1,                       \
3050                         TEGRA_MUX_ ## f2,                       \
3051                         TEGRA_MUX_ ## f3,                       \
3052                 },                                              \
3053                 .func_safe_non_dt = TEGRA_MUX_## f_safe,        \
3054                 .mux_reg = PINGROUP_REG_Y(r),                   \
3055                 .mux_bank = 1,                                  \
3056                 .mux_bit = 0,                                   \
3057                 .pupd_reg = PINGROUP_REG_Y(r),                  \
3058                 .pupd_bank = 1,                                 \
3059                 .pupd_bit = 2,                                  \
3060                 .tri_reg = PINGROUP_REG_Y(r),                   \
3061                 .tri_bank = 1,                                  \
3062                 .tri_bit = 4,                                   \
3063                 .einput_reg = PINGROUP_REG_Y(r),                \
3064                 .einput_bank = 1,                               \
3065                 .einput_bit = 5,                                \
3066                 .odrain_reg = PINGROUP_REG_##od(r),             \
3067                 .odrain_bank = 1,                               \
3068                 .odrain_bit = 6,                                \
3069                 .lock_reg = PINGROUP_REG_Y(r),                  \
3070                 .lock_bank = 1,                                 \
3071                 .lock_bit = 7,                                  \
3072                 .ioreset_reg = PINGROUP_REG_##ior(r),           \
3073                 .ioreset_bank = 1,                              \
3074                 .ioreset_bit = 8,                               \
3075                 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r),       \
3076                 .rcv_sel_bank = 1,                              \
3077                 .rcv_sel_bit = 9,                               \
3078                 .drv_reg = -1,                                  \
3079                 .drvtype_reg = -1,                              \
3080         }
3081
3082 #define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A)
3083 #define DRV_PINGROUP_DVRTYPE_N(r) -1
3084
3085 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,      \
3086                      drvdn_b, drvdn_w, drvup_b, drvup_w,        \
3087                      slwr_b, slwr_w, slwf_b, slwf_w,            \
3088                      drvtype)                                   \
3089         {                                                       \
3090                 .name = "drive_" #pg_name,                      \
3091                 .pins = drive_##pg_name##_pins,                 \
3092                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),    \
3093                 .mux_reg = -1,                                  \
3094                 .pupd_reg = -1,                                 \
3095                 .tri_reg = -1,                                  \
3096                 .einput_reg = -1,                               \
3097                 .odrain_reg = -1,                               \
3098                 .lock_reg = -1,                                 \
3099                 .ioreset_reg = -1,                              \
3100                 .rcv_sel_reg = -1,                              \
3101                 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r),           \
3102                 .drv_bank = 0,                                  \
3103                 .hsm_bit = hsm_b,                               \
3104                 .schmitt_bit = schmitt_b,                       \
3105                 .lpmd_bit = lpmd_b,                             \
3106                 .drvdn_bit = drvdn_b,                           \
3107                 .drvdn_width = drvdn_w,                         \
3108                 .drvup_bit = drvup_b,                           \
3109                 .drvup_width = drvup_w,                         \
3110                 .slwr_bit = slwr_b,                             \
3111                 .slwr_width = slwr_w,                           \
3112                 .slwf_bit = slwf_b,                             \
3113                 .slwf_width = slwf_w,                           \
3114                 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r),       \
3115                 .drvtype_bank = 0,                              \
3116                 .drvtype_bit = 6,                               \
3117                 .drvtype_width = 2,                             \
3118         }
3119
3120 #define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
3121
3122 #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, f0, f1, f2, f3)                     \
3123 {                                                               \
3124         .name = "mipi_pad_ctrl_" #pg_name,                      \
3125         .pins = mipi_pad_ctrl_##pg_name##_pins,                 \
3126         .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins),    \
3127         .funcs = {                                              \
3128                 TEGRA_MUX_DT_ ## f0,                            \
3129                 TEGRA_MUX_DT_ ## f1,                            \
3130                 TEGRA_MUX_DT_ ## f2,                            \
3131                 TEGRA_MUX_DT_ ## f3,                            \
3132         },                                                      \
3133         .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r),             \
3134         .mux_bank = 2,                                          \
3135         .mux_bit = 1,                                           \
3136         .pupd_reg = -1,                                         \
3137         .tri_reg = -1,                                          \
3138         .einput_bit = -1,                                       \
3139         .odrain_bit = -1,                                       \
3140         .lock_bit = -1,                                         \
3141         .ioreset_bit = -1,                                      \
3142         .rcv_sel_bit = -1,                                      \
3143         .drv_reg = -1,                                          \
3144 }
3145
3146
3147 static const struct tegra_pingroup tegra124_groups[] = {
3148         /*       pg_name,                f0,         f1,         f2,           f3,          safe,     r,      od, ior, rcv_sel */
3149         /* FIXME: Fill in correct data in safe column */
3150         PINGROUP(ulpi_data0_po1,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x3000,  N,  N,  N),
3151         PINGROUP(ulpi_data1_po2,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x3004,  N,  N,  N),
3152         PINGROUP(ulpi_data2_po3,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x3008,  N,  N,  N),
3153         PINGROUP(ulpi_data3_po4,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x300c,  N,  N,  N),
3154         PINGROUP(ulpi_data4_po5,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x3010,  N,  N,  N),
3155         PINGROUP(ulpi_data5_po6,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x3014,  N,  N,  N),
3156         PINGROUP(ulpi_data6_po7,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x3018,  N,  N,  N),
3157         PINGROUP(ulpi_data7_po0,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x301c,  N,  N,  N),
3158         PINGROUP(ulpi_clk_py0,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x3020,  N,  N,  N),
3159         PINGROUP(ulpi_dir_py1,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x3024,  N,  N,  N),
3160         PINGROUP(ulpi_nxt_py2,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x3028,  N,  N,  N),
3161         PINGROUP(ulpi_stp_py3,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x302c,  N,  N,  N),
3162         PINGROUP(dap3_fs_pp0,           I2S2,           SPI5,           DISPLAYA,       DISPLAYB,       I2S2,           0x3030,  N,  N,  N),
3163         PINGROUP(dap3_din_pp1,          I2S2,           SPI5,           DISPLAYA,       DISPLAYB,       I2S2,           0x3034,  N,  N,  N),
3164         PINGROUP(dap3_dout_pp2,         I2S2,           SPI5,           DISPLAYA,       RSVD4,          I2S2,           0x3038,  N,  N,  N),
3165         PINGROUP(dap3_sclk_pp3,         I2S2,           SPI5,           RSVD3,          DISPLAYB,       I2S2,           0x303c,  N,  N,  N),
3166         PINGROUP(pv0,                   RSVD1,          RSVD2,          RSVD3,          RSVD4,          RSVD1,          0x3040,  N,  N,  N),
3167         PINGROUP(pv1,                   RSVD1,          RSVD2,          RSVD3,          RSVD4,          RSVD1,          0x3044,  N,  N,  N),
3168         PINGROUP(sdmmc1_clk_pz0,        SDMMC1,         CLK12,          RSVD3,          RSVD4,          RSVD3,          0x3048,  N,  N,  N),
3169         PINGROUP(sdmmc1_cmd_pz1,        SDMMC1,         SPDIF,          SPI4,           UARTA,          SDMMC1,         0x304c,  N,  N,  N),
3170         PINGROUP(sdmmc1_dat3_py4,       SDMMC1,         SPDIF,          SPI4,           UARTA,          SDMMC1,         0x3050,  N,  N,  N),
3171         PINGROUP(sdmmc1_dat2_py5,       SDMMC1,         PWM0,           SPI4,           UARTA,          SDMMC1,         0x3054,  N,  N,  N),
3172         PINGROUP(sdmmc1_dat1_py6,       SDMMC1,         PWM1,           SPI4,           UARTA,          SDMMC1,         0x3058,  N,  N,  N),
3173         PINGROUP(sdmmc1_dat0_py7,       SDMMC1,         RSVD2,          SPI4,           UARTA,          SDMMC1,         0x305c,  N,  N,  N),
3174         PINGROUP(clk2_out_pw5,          EXTPERIPH2,     RSVD2,          RSVD3,          RSVD4,          EXTPERIPH2,     0x3068,  N,  N,  N),
3175         PINGROUP(clk2_req_pcc5,         DAP,            RSVD2,          RSVD3,          RSVD4,          DAP,            0x306c,  N,  N,  N),
3176         PINGROUP(hdmi_int_pn7,          RSVD1,          RSVD2,          RSVD3,          RSVD4,          RSVD1,          0x3110,  N,  N,  Y),
3177         PINGROUP(ddc_scl_pv4,           I2C4,           RSVD2,          RSVD3,          RSVD4,          I2C4,           0x3114,  N,  N,  Y),
3178         PINGROUP(ddc_sda_pv5,           I2C4,           RSVD2,          RSVD3,          RSVD4,          I2C4,           0x3118,  N,  N,  Y),
3179         PINGROUP(uart2_rxd_pc3,         IRDA,           SPDIF,          UARTA,          SPI4,           IRDA,           0x3164,  N,  N,  N),
3180         PINGROUP(uart2_txd_pc2,         IRDA,           SPDIF,          UARTA,          SPI4,           IRDA,           0x3168,  N,  N,  N),
3181         PINGROUP(uart2_rts_n_pj6,       UARTA,          UARTB,          GMI,            SPI4,           UARTA,          0x316c,  N,  N,  N),
3182         PINGROUP(uart2_cts_n_pj5,       UARTA,          UARTB,          GMI,            SPI4,           UARTA,          0x3170,  N,  N,  N),
3183         PINGROUP(uart3_txd_pw6,         UARTC,          RSVD2,          GMI,            SPI4,           UARTC,          0x3174,  N,  N,  N),
3184         PINGROUP(uart3_rxd_pw7,         UARTC,          RSVD2,          GMI,            SPI4,           UARTC,          0x3178,  N,  N,  N),
3185         PINGROUP(uart3_cts_n_pa1,       UARTC,          SDMMC1,         DTV,            GMI,            UARTC,          0x317c,  N,  N,  N),
3186         PINGROUP(uart3_rts_n_pc0,       UARTC,          PWM0,           DTV,            GMI,            UARTC,          0x3180,  N,  N,  N),
3187         PINGROUP(pu0,                   OWR,            UARTA,          GMI,            RSVD4,          RSVD4,          0x3184,  N,  N,  N),
3188         PINGROUP(pu1,                   RSVD1,          UARTA,          GMI,            RSVD4,          RSVD4,          0x3188,  N,  N,  N),
3189         PINGROUP(pu2,                   RSVD1,          UARTA,          GMI,            RSVD4,          RSVD4,          0x318c,  N,  N,  N),
3190         PINGROUP(pu3,                   PWM0,           UARTA,          GMI,            DISPLAYB,       PWM0,           0x3190,  N,  N,  N),
3191         PINGROUP(pu4,                   PWM1,           UARTA,          GMI,            DISPLAYB,       PWM1,           0x3194,  N,  N,  N),
3192         PINGROUP(pu5,                   PWM2,           UARTA,          GMI,            DISPLAYB,       PWM2,           0x3198,  N,  N,  N),
3193         PINGROUP(pu6,                   PWM3,           UARTA,          RSVD3,          GMI,            RSVD3,          0x319c,  N,  N,  N),
3194         PINGROUP(gen1_i2c_scl_pc4,      I2C1,           RSVD2,          RSVD3,          RSVD4,          I2C1,           0x31a0,  Y,  N,  N),
3195         PINGROUP(gen1_i2c_sda_pc5,      I2C1,           RSVD2,          RSVD3,          RSVD4,          I2C1,           0x31a4,  Y,  N,  N),
3196         PINGROUP(dap4_fs_pp4,           I2S3,           GMI,            DTV,            RSVD4,          I2S3,           0x31a8,  N,  N,  N),
3197         PINGROUP(dap4_din_pp5,          I2S3,           GMI,            RSVD3,          RSVD4,          I2S3,           0x31ac,  N,  N,  N),
3198         PINGROUP(dap4_dout_pp6,         I2S3,           GMI,            DTV,            RSVD4,          I2S3,           0x31b0,  N,  N,  N),
3199         PINGROUP(dap4_sclk_pp7,         I2S3,           GMI,            RSVD3,          RSVD4,          I2S3,           0x31b4,  N,  N,  N),
3200         PINGROUP(clk3_out_pee0,         EXTPERIPH3,     RSVD2,          RSVD3,          RSVD4,          RSVD3,          0x31b8,  N,  N,  N),
3201         PINGROUP(clk3_req_pee1,         DEV3,           RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x31bc,  N,  N,  N),
3202         PINGROUP(pc7,                   RSVD1,          RSVD2,          GMI,            GMI_ALT,        RSVD1,          0x31c0,  N,  N,  N),
3203         PINGROUP(pi5,                   SDMMC2,         RSVD2,          GMI,            RSVD4,          GMI,            0x31c4,  N,  N,  N),
3204         PINGROUP(pi7,                   RSVD1,          TRACE,          GMI,            DTV,            RSVD1,          0x31c8,  N,  N,  N),
3205         PINGROUP(pk0,                   RSVD1,          SDMMC3,         GMI,            SOC,            RSVD1,          0x31cc,  N,  N,  N),
3206         PINGROUP(pk1,                   SDMMC2,         TRACE,          GMI,            RSVD4,          GMI,            0x31d0,  N,  N,  N),
3207         PINGROUP(pj0,                   RSVD1,          RSVD2,          GMI,            USB,            RSVD1,          0x31d4,  N,  N,  N),
3208         PINGROUP(pj2,                   RSVD1,          RSVD2,          GMI,            SOC,            RSVD1,          0x31d8,  N,  N,  N),
3209         PINGROUP(pk3,                   SDMMC2,         TRACE,          GMI,            CCLA,           GMI,            0x31dc,  N,  N,  N),
3210         PINGROUP(pk4,                   SDMMC2,         RSVD2,          GMI,            GMI_ALT,        GMI,            0x31e0,  N,  N,  N),
3211         PINGROUP(pk2,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x31e4,  N,  N,  N),
3212         PINGROUP(pi3,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x31e8,  N,  N,  N),
3213         PINGROUP(pi6,                   RSVD1,          RSVD2,          GMI,            SDMMC2,         RSVD1,          0x31ec,  N,  N,  N),
3214         PINGROUP(pg0,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x31f0,  N,  N,  N),
3215         PINGROUP(pg1,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x31f4,  N,  N,  N),
3216         PINGROUP(pg2,                   RSVD1,          TRACE,          GMI,            RSVD4,          RSVD4,          0x31f8,  N,  N,  N),
3217         PINGROUP(pg3,                   RSVD1,          TRACE,          GMI,            RSVD4,          RSVD4,          0x31fc,  N,  N,  N),
3218         PINGROUP(pg4,                   RSVD1,          TMDS,           GMI,            SPI4,           RSVD1,          0x3200,  N,  N,  N),
3219         PINGROUP(pg5,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x3204,  N,  N,  N),
3220         PINGROUP(pg6,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x3208,  N,  N,  N),
3221         PINGROUP(pg7,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x320c,  N,  N,  N),
3222         PINGROUP(ph0,                   PWM0,           TRACE,          GMI,            DTV,            GMI,            0x3210,  N,  N,  N),
3223         PINGROUP(ph1,                   PWM1,           TMDS,           GMI,            DISPLAYA,       GMI,            0x3214,  N,  N,  N),
3224         PINGROUP(ph2,                   PWM2,           TMDS,           GMI,            CLDVFS,         GMI,            0x3218,  N,  N,  N),
3225         PINGROUP(ph3,                   PWM3,           SPI4,           GMI,            CLDVFS,         GMI,            0x321c,  N,  N,  N),
3226         PINGROUP(ph4,                   SDMMC2,         RSVD2,          GMI,            RSVD4,          GMI,            0x3220,  N,  N,  N),
3227         PINGROUP(ph5,                   SDMMC2,         RSVD2,          GMI,            RSVD4,          GMI,            0x3224,  N,  N,  N),
3228         PINGROUP(ph6,                   SDMMC2,         TRACE,          GMI,            DTV,            GMI,            0x3228,  N,  N,  N),
3229         PINGROUP(ph7,                   SDMMC2,         TRACE,          GMI,            DTV,            GMI,            0x322c,  N,  N,  N),
3230         PINGROUP(pj7,                   UARTD,          RSVD2,          GMI,            GMI_ALT,        RSVD2,          0x3230,  N,  N,  N),
3231         PINGROUP(pb0,                   UARTD,          RSVD2,          GMI,            RSVD4,          RSVD2,          0x3234,  N,  N,  N),
3232         PINGROUP(pb1,                   UARTD,          RSVD2,          GMI,            RSVD4,          RSVD2,          0x3238,  N,  N,  N),
3233         PINGROUP(pk7,                   UARTD,          RSVD2,          GMI,            RSVD4,          RSVD2,          0x323c,  N,  N,  N),
3234         PINGROUP(pi0,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x3240,  N,  N,  N),
3235         PINGROUP(pi1,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD1,          0x3244,  N,  N,  N),
3236         PINGROUP(pi2,                   SDMMC2,         TRACE,          GMI,            RSVD4,          GMI,            0x3248,  N,  N,  N),
3237         PINGROUP(pi4,                   SPI4,           TRACE,          GMI,            DISPLAYA,       GMI,            0x324c,  N,  N,  N),
3238         PINGROUP(gen2_i2c_scl_pt5,      I2C2,           RSVD2,          GMI,            RSVD4,          RSVD2,          0x3250,  Y,  N,  N),
3239         PINGROUP(gen2_i2c_sda_pt6,      I2C2,           RSVD2,          GMI,            RSVD4,          RSVD2,          0x3254,  Y,  N,  N),
3240         PINGROUP(sdmmc4_clk_pcc4,       SDMMC4,         RSVD2,          GMI,            RSVD4,          RSVD2,          0x3258,  N,  Y,  N),
3241         PINGROUP(sdmmc4_cmd_pt7,        SDMMC4,         RSVD2,          GMI,            RSVD4,          RSVD2,          0x325c,  N,  Y,  N),
3242         PINGROUP(sdmmc4_dat0_paa0,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3260,  N,  Y,  N),
3243         PINGROUP(sdmmc4_dat1_paa1,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3264,  N,  Y,  N),
3244         PINGROUP(sdmmc4_dat2_paa2,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3268,  N,  Y,  N),
3245         PINGROUP(sdmmc4_dat3_paa3,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x326c,  N,  Y,  N),
3246         PINGROUP(sdmmc4_dat4_paa4,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3270,  N,  Y,  N),
3247         PINGROUP(sdmmc4_dat5_paa5,      SDMMC4,         SPI3,           RSVD3,          RSVD4,          SDMMC4,         0x3274,  N,  Y,  N),
3248         PINGROUP(sdmmc4_dat6_paa6,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3278,  N,  Y,  N),
3249         PINGROUP(sdmmc4_dat7_paa7,      SDMMC4,         RSVD1,          GMI,            RSVD4,          SDMMC4,         0x327c,  N,  Y,  N),
3250         PINGROUP(cam_mclk_pcc0,         VI,             VI_ALT1,        VI_ALT3,        SDMMC2,         VI,             0x3284,  N,  N,  N),
3251         PINGROUP(pcc1,                  I2S4,           RSVD2,          RSVD3,          SDMMC2,         I2S4,           0x3288,  N,  N,  N),
3252         PINGROUP(pbb0,                  VGP6,           VIMCLK2,        SDMMC2,         VIMCLK2_ALT,    VGP6,           0x328c,  N,  N,  N),
3253         PINGROUP(cam_i2c_scl_pbb1,      VGP1,           I2C3,           RSVD3,          SDMMC2,         VGP1,           0x3290,  Y,  N,  N),
3254         PINGROUP(cam_i2c_sda_pbb2,      VGP2,           I2C3,           RSVD3,          SDMMC2,         VGP2,           0x3294,  Y,  N,  N),
3255         PINGROUP(pbb3,                  VGP3,           DISPLAYA,       DISPLAYB,       SDMMC2,         VGP3,           0x3298,  N,  N,  N),
3256         PINGROUP(pbb4,                  VGP4,           DISPLAYA,       DISPLAYB,       SDMMC2,         VGP4,           0x329c,  N,  N,  N),
3257         PINGROUP(pbb5,                  VGP5,           DISPLAYA,       RSVD3,          SDMMC2,         VGP5,           0x32a0,  N,  N,  N),
3258         PINGROUP(pbb6,                  I2S4,           RSVD2,          DISPLAYB,       SDMMC2,         I2S4,           0x32a4,  N,  N,  N),
3259         PINGROUP(pbb7,                  I2S4,           RSVD2,          RSVD3,          SDMMC2,         I2S4,           0x32a8,  N,  N,  N),
3260         PINGROUP(pcc2,                  I2S4,           RSVD2,          SDMMC3,         SDMMC2,         I2S4,           0x32ac,  N,  N,  N),
3261         PINGROUP(jtag_rtck,             RTCK,           RSVD2,          RSVD3,          RSVD4,          RTCK,           0x32b0,  N,  N,  N),
3262         PINGROUP(pwr_i2c_scl_pz6,       I2CPWR,         RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x32b4,  Y,  N,  N),
3263         PINGROUP(pwr_i2c_sda_pz7,       I2CPWR,         RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x32b8,  Y,  N,  N),
3264         PINGROUP(kb_row0_pr0,           KBC,            RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x32bc,  N,  N,  N),
3265         PINGROUP(kb_row1_pr1,           KBC,            RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x32c0,  N,  N,  N),
3266         PINGROUP(kb_row2_pr2,           KBC,            RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x32c4,  N,  N,  N),
3267         PINGROUP(kb_row3_pr3,           KBC,            DISPLAYA,       SYS,            DISPLAYB,       KBC,            0x32c8,  N,  N,  N),
3268         PINGROUP(kb_row4_pr4,           KBC,            DISPLAYA,       RSVD3,          DISPLAYB,       RSVD3,          0x32cc,  N,  N,  N),
3269         PINGROUP(kb_row5_pr5,           KBC,            DISPLAYA,       RSVD3,          DISPLAYB,       RSVD3,          0x32d0,  N,  N,  N),
3270         PINGROUP(kb_row6_pr6,           KBC,            DISPLAYA,       DISPLAYA_ALT,   DISPLAYB,       KBC,            0x32d4,  N,  N,  N),
3271         PINGROUP(kb_row7_pr7,           KBC,            RSVD2,          CLDVFS,         UARTA,          RSVD2,          0x32d8,  N,  N,  N),
3272         PINGROUP(kb_row8_ps0,           KBC,            RSVD2,          CLDVFS,         UARTA,          RSVD2,          0x32dc,  N,  N,  N),
3273         PINGROUP(kb_row9_ps1,           KBC,            RSVD2,          RSVD3,          UARTA,          KBC,            0x32e0,  N,  N,  N),
3274         PINGROUP(kb_row10_ps2,          KBC,            RSVD2,          RSVD3,          UARTA,          KBC,            0x32e4,  N,  N,  N),
3275         PINGROUP(kb_row11_ps3,          KBC,            RSVD2,          RSVD3,          IRDA,           RSVD3,          0x32e8,  N,  N,  N),
3276         PINGROUP(kb_row12_ps4,          KBC,            RSVD2,          RSVD3,          IRDA,           RSVD3,          0x32ec,  N,  N,  N),
3277         PINGROUP(kb_row13_ps5,          KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x32f0,  N,  N,  N),
3278         PINGROUP(kb_row14_ps6,          KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x32f4,  N,  N,  N),
3279         PINGROUP(kb_row15_ps7,          KBC,            SOC,            RSVD3,          RSVD4,          KBC,            0x32f8,  N,  N,  N),
3280         PINGROUP(kb_col0_pq0,           KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x32fc,  N,  N,  N),
3281         PINGROUP(kb_col1_pq1,           KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x3300,  N,  N,  N),
3282         PINGROUP(kb_col2_pq2,           KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x3304,  N,  N,  N),
3283         PINGROUP(kb_col3_pq3,           KBC,            DISPLAYA,       PWM2,           UARTA,          KBC,            0x3308,  N,  N,  N),
3284         PINGROUP(kb_col4_pq4,           KBC,            OWR,            SDMMC3,         UARTA,          KBC,            0x330c,  N,  N,  N),
3285         PINGROUP(kb_col5_pq5,           KBC,            RSVD2,          SDMMC3,         RSVD4,          RSVD4,          0x3310,  N,  N,  N),
3286         PINGROUP(kb_col6_pq6,           KBC,            RSVD2,          SPI2,           UARTD,          RSVD2,          0x3314,  N,  N,  N),
3287         PINGROUP(kb_col7_pq7,           KBC,            RSVD2,          SPI2,           UARTD,          RSVD2,          0x3318,  N,  N,  N),
3288         PINGROUP(clk_32k_out_pa0,       BLINK,          SOC,            RSVD3,          RSVD4,          RSVD3,          0x331c,  N,  N,  N),
3289         PINGROUP(core_pwr_req,          PWRON,          RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3324,  N,  N,  N),
3290         PINGROUP(cpu_pwr_req,           CPU,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3328,  N,  N,  N),
3291         PINGROUP(pwr_int_n,             PMI,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x332c,  N,  N,  N),
3292         PINGROUP(clk_32k_in,            CLK,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3330,  N,  N,  N),
3293         PINGROUP(owr,                   OWR,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3334,  N,  N,  Y),
3294         PINGROUP(dap1_fs_pn0,           I2S0,           HDA,            GMI,            RSVD4,          RSVD4,          0x3338,  N,  N,  N),
3295         PINGROUP(dap1_din_pn1,          I2S0,           HDA,            GMI,            RSVD4,          RSVD4,          0x333c,  N,  N,  N),
3296         PINGROUP(dap1_dout_pn2,         I2S0,           HDA,            GMI,            SATA,           I2S0,           0x3340,  N,  N,  N),
3297         PINGROUP(dap1_sclk_pn3,         I2S0,           HDA,            GMI,            RSVD4,          I2S0,           0x3344,  N,  N,  N),
3298         PINGROUP(dap_mclk1_req_pee2,    DAP,            DAP1,           SATA,           RSVD4,          DAP,            0x3348,  N,  N,  N),
3299         PINGROUP(dap_mclk1_pw4,         EXTPERIPH1,     DAP2,           RSVD3,          RSVD4,          RSVD3,          0x334c,  N,  N,  N),
3300         PINGROUP(spdif_in_pk6,          SPDIF,          RSVD2,          RSVD3,          I2C3,           RSVD3,          0x3350,  N,  N,  N),
3301         PINGROUP(spdif_out_pk5,         SPDIF,          RSVD2,          RSVD3,          I2C3,           RSVD3,          0x3354,  N,  N,  N),
3302         PINGROUP(dap2_fs_pa2,           I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x3358,  N,  N,  N),
3303         PINGROUP(dap2_din_pa4,          I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x335c,  N,  N,  N),
3304         PINGROUP(dap2_dout_pa5,         I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x3360,  N,  N,  N),
3305         PINGROUP(dap2_sclk_pa3,         I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x3364,  N,  N,  N),
3306         PINGROUP(dvfs_pwm_px0,          SPI6,           CLDVFS,         GMI,            RSVD4,          SPI6,           0x3368,  N,  N,  N),
3307         PINGROUP(gpio_x1_aud_px1,       SPI6,           RSVD2,          GMI,            RSVD4,          SPI6,           0x336c,  N,  N,  N),
3308         PINGROUP(gpio_x3_aud_px3,       SPI6,           SPI1,           GMI,            RSVD4,          SPI6,           0x3370,  N,  N,  N),
3309         PINGROUP(dvfs_clk_px2,          SPI6,           CLDVFS,         GMI,            RSVD4,          SPI6,           0x3374,  N,  N,  N),
3310         PINGROUP(gpio_x4_aud_px4,       GMI,            SPI1,           SPI2,           DAP2,           SPI1,           0x3378,  N,  N,  N),
3311         PINGROUP(gpio_x5_aud_px5,       GMI,            SPI1,           SPI2,           RSVD4,          SPI1,           0x337c,  N,  N,  N),
3312         PINGROUP(gpio_x6_aud_px6,       SPI6,           SPI1,           SPI2,           GMI,            SPI1,           0x3380,  N,  N,  N),
3313         PINGROUP(gpio_x7_aud_px7,       RSVD1,          SPI1,           SPI2,           RSVD4,          SPI1,           0x3384,  N,  N,  N),
3314         PINGROUP(sdmmc3_clk_pa6,        SDMMC3,         RSVD2,          RSVD3,          SPI3,           SDMMC3,         0x3390,  N,  N,  N),
3315         PINGROUP(sdmmc3_cmd_pa7,        SDMMC3,         PWM3,           UARTA,          SPI3,           SDMMC3,         0x3394,  N,  N,  N),
3316         PINGROUP(sdmmc3_dat0_pb7,       SDMMC3,         RSVD2,          RSVD3,          SPI3,           SDMMC3,         0x3398,  N,  N,  N),
3317         PINGROUP(sdmmc3_dat1_pb6,       SDMMC3,         PWM2,           UARTA,          SPI3,           SDMMC3,         0x339c,  N,  N,  N),
3318         PINGROUP(sdmmc3_dat2_pb5,       SDMMC3,         PWM1,           DISPLAYA,       SPI3,           SDMMC3,         0x33a0,  N,  N,  N),
3319         PINGROUP(sdmmc3_dat3_pb4,       SDMMC3,         PWM0,           DISPLAYB,       SPI3,           SDMMC3,         0x33a4,  N,  N,  N),
3320         PINGROUP(pex_l0_rst_n_pdd1,     PE0,            RSVD2,          RSVD3,          RSVD4,          PE0,            0x33bc,  N,  N,  N),
3321         PINGROUP(pex_l0_clkreq_n_pdd2,  PE0,            RSVD2,          RSVD3,          RSVD4,          PE0,            0x33c0,  N,  N,  N),
3322         PINGROUP(pex_wake_n_pdd3,       PE,             RSVD2,          RSVD3,          RSVD4,          PE,             0x33c4,  N,  N,  N),
3323         PINGROUP(pex_l1_rst_n_pdd5,     PE1,            RSVD2,          RSVD3,          RSVD4,          PE1,            0x33cc,  N,  N,  N),
3324         PINGROUP(pex_l1_clkreq_n_pdd6,  PE1,            RSVD2,          RSVD3,          RSVD4,          PE1,            0x33d0,  N,  N,  N),
3325         PINGROUP(hdmi_cec_pee3,         CEC,            RSVD2,          RSVD3,          RSVD4,          CEC,            0x33e0,  Y,  N,  N),
3326         PINGROUP(sdmmc1_wp_n_pv3,       SDMMC1,         CLK12,          SPI4,           UARTA,          SDMMC1,         0x33e4,  N,  N,  N),
3327         PINGROUP(sdmmc3_cd_n_pv2,       SDMMC3,         OWR,            RSVD3,          RSVD4,          SDMMC3,         0x33e8,  N,  N,  N),
3328         PINGROUP(gpio_w2_aud_pw2,       SPI6,           RSVD2,          SPI2,           I2C1,           RSVD2,          0x33ec,  N,  N,  N),
3329         PINGROUP(gpio_w3_aud_pw3,       SPI6,           SPI1,           SPI2,           I2C1,           SPI1,           0x33f0,  N,  N,  N),
3330         PINGROUP(usb_vbus_en0_pn4,      USB,            RSVD2,          RSVD3,          RSVD4,          USB,            0x33f4,  Y,  N,  N),
3331         PINGROUP(usb_vbus_en1_pn5,      USB,            RSVD2,          RSVD3,          RSVD4,          USB,            0x33f8,  Y,  N,  N),
3332         PINGROUP(sdmmc3_clk_lb_out_pee4,        SDMMC3, RSVD2,          RSVD3,          RSVD4,          SDMMC3,         0x33fc,  N,  N,  N),
3333         PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3,         RSVD2,          RSVD3,          RSVD4,          SDMMC3,         0x3400,  N,  N,  N),
3334         PINGROUP(gmi_clk_lb,            SDMMC2,         RSVD2,          GMI,            RSVD4,          SDMMC2,         0x3404,  N,  N,  N),
3335         PINGROUP(reset_out_n,           RSVD1,          RSVD2,          RSVD3,          RESET_OUT_N,    RSVD1,          0x3408,  N,  N,  N),
3336         PINGROUP(kb_row16_pt0,          KBC,            RSVD2,          RSVD3,          UARTC,          KBC,            0x340c,  N,  N,  N),
3337         PINGROUP(kb_row17_pt1,          KBC,            RSVD2,          RSVD3,          UARTC,          KBC,            0x3410,  N,  N,  N),
3338         PINGROUP(usb_vbus_en2_pff1,     USB,            RSVD2,          RSVD3,          RSVD4,          USB,            0x3414,  Y,  N,  N),
3339         PINGROUP(pff2,                  SATA,           RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3418,  Y,  N,  N),
3340         PINGROUP(dp_hpd_pff0,           DP,             RSVD2,          RSVD3,          RSVD4,          DP,             0x3430,  N,  N,  N),
3341
3342         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
3343         DRV_PINGROUP(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3344         DRV_PINGROUP(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3345         DRV_PINGROUP(at1,   0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3346         DRV_PINGROUP(at2,   0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3347         DRV_PINGROUP(at3,   0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3348         DRV_PINGROUP(at4,   0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3349         DRV_PINGROUP(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3350         DRV_PINGROUP(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3351         DRV_PINGROUP(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3352         DRV_PINGROUP(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3353         DRV_PINGROUP(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3354         DRV_PINGROUP(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3355         DRV_PINGROUP(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3356         DRV_PINGROUP(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3357         DRV_PINGROUP(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
3358         DRV_PINGROUP(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3359         DRV_PINGROUP(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3360         DRV_PINGROUP(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3361         DRV_PINGROUP(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3362         DRV_PINGROUP(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3363         DRV_PINGROUP(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
3364         DRV_PINGROUP(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3365         DRV_PINGROUP(gma,   0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
3366         DRV_PINGROUP(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3367         DRV_PINGROUP(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3368         DRV_PINGROUP(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3369         DRV_PINGROUP(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3370         DRV_PINGROUP(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3371         DRV_PINGROUP(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3372         DRV_PINGROUP(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3373         DRV_PINGROUP(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3374         DRV_PINGROUP(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3375         DRV_PINGROUP(at6,   0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3376         DRV_PINGROUP(dap5,  0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3377         DRV_PINGROUP(usb_vbus_en,  0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3378         DRV_PINGROUP(ao3,   0x9a8,  2,  3,  4,  12,  5,  -1,  -1,  28,  2,  -1,  -1,  N),
3379         DRV_PINGROUP(ao0,   0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3380         DRV_PINGROUP(hv0,   0x9b4,  2,  3,  4,  12,  5,  -1,  -1,  28,  2,  -1,  -1,  N),
3381         DRV_PINGROUP(sdio4, 0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3382         DRV_PINGROUP(ao4,   0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3383
3384         /*pg_name,      r,      f0,     f1,     f2,     f3 */
3385         MIPI_PAD_CTRL_PINGROUP(dsi_b,   0x820,  CSI, DSI_B, RSVD3, RSVD4)
3386 };
3387
3388 static int tegra124_pinctrl_suspend(u32 *pg_data)
3389 {
3390         int i;
3391         u32 *ctx = pg_data;
3392
3393         for (i = 0; i <  ARRAY_SIZE(tegra124_groups); i++) {
3394                 if (tegra124_groups[i].drv_reg < 0)
3395                         *ctx++ = tegra_pinctrl_readl(tegra124_groups[i].mux_bank,
3396                                                 tegra124_groups[i].mux_reg);
3397                 else
3398                         *ctx++ = tegra_pinctrl_readl(tegra124_groups[i].drv_bank,
3399                                                 tegra124_groups[i].drv_reg);
3400         }
3401
3402         return 0;
3403 }
3404
3405 static void tegra124_pinctrl_resume(u32 *pg_data)
3406 {
3407         int i;
3408         u32 *ctx = pg_data;
3409
3410         if (tegra_is_dpd_mode) {
3411                 u32 *tmp = pg_data;
3412                 u32 reg_value;
3413                 for (i = 0; i < ARRAY_SIZE(tegra124_groups); i++) {
3414                         if (tegra124_groups[i].drv_reg < 0) {
3415                                 reg_value = *tmp++;
3416                                 reg_value |= BIT(4);
3417                                 tegra_pinctrl_writel(reg_value,
3418                                                 tegra124_groups[i].mux_bank,
3419                                                 tegra124_groups[i].mux_reg);
3420                         }
3421                 }
3422
3423                 tegra_pmc_remove_dpd_req();
3424                 tegra_is_dpd_mode = false;
3425         }
3426         for (i = 0; i <  ARRAY_SIZE(tegra124_groups); i++) {
3427                 if (tegra124_groups[i].drv_reg < 0)
3428                         tegra_pinctrl_writel(*ctx++, tegra124_groups[i].mux_bank,
3429                                                 tegra124_groups[i].mux_reg);
3430                 else
3431                         tegra_pinctrl_writel(*ctx++, tegra124_groups[i].drv_bank,
3432                                                 tegra124_groups[i].drv_reg);
3433         }
3434         /* Clear DPD sample */
3435         tegra_pmc_clear_dpd_sample();
3436 }
3437
3438 static struct tegra_pinctrl_group_config_data t124_pin_drv_group_soc_data[] = {
3439         TEGRA_PINCTRL_SET_DRIVE(dap2, 0, 1, 3, 5, 6, 0, 0, 0),
3440         TEGRA_PINCTRL_SET_DRIVE(dap1, 0, 1, 3, 5, 6, 0, 0, 0),
3441         TEGRA_PINCTRL_SET_DRIVE(dap3, 0, 1, 3, 5, 6, 0, 0, 0),
3442         TEGRA_PINCTRL_SET_DRIVE(dap4, 0, 1, 3, 5, 6, 0, 0, 0),
3443         TEGRA_PINCTRL_SET_DRIVE(dap5, 0, 1, 3, 5, 6, 0, 0, 0),
3444         TEGRA_PINCTRL_SET_DRIVE(dbg, 1, 1, 0, 5, 5, 0, 0, 0),
3445         TEGRA_PINCTRL_SET_DRIVE(at5, 1, 1, 0, 5, 5, 0, 0, 0),
3446         TEGRA_PINCTRL_SET_DRIVE(gme, 1, 1, 0, 5, 5, 0, 0, 0),
3447         TEGRA_PINCTRL_SET_DRIVE(ddc, 1, 1, 0, 5, 5, 0, 0, 0),
3448         TEGRA_PINCTRL_SET_DRIVE(ao1, 1, 1, 0, 5, 5, 0, 0, 0),
3449         TEGRA_PINCTRL_SET_DRIVE(uart2, 0, 0, 3, 0, 0, 3, 3, 0),
3450         TEGRA_PINCTRL_SET_DRIVE(uart3, 0, 0, 3, 0, 0, 3, 3, 0),
3451         TEGRA_PINCTRL_SET_DRIVE(at2, 0, 0, 0, 55, 63, 0, 0, 0),
3452         TEGRA_PINCTRL_SET_DRIVE(uda, 0, 0, 0, 23, 23, 3, 3, 0),
3453         TEGRA_PINCTRL_SET_DRIVE(uaa, 0, 0, 0, 23, 23, 3, 3, 0),
3454 };
3455
3456 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
3457         .ngpios = NUM_GPIOS,
3458         .pins = tegra124_pins,
3459         .npins = ARRAY_SIZE(tegra124_pins),
3460         .functions = tegra124_functions,
3461         .nfunctions = ARRAY_SIZE(tegra124_functions),
3462         .groups = tegra124_groups,
3463         .ngroups = ARRAY_SIZE(tegra124_groups),
3464         .suspend = tegra124_pinctrl_suspend,
3465         .resume = tegra124_pinctrl_resume,
3466         .config_data = t124_pin_drv_group_soc_data,
3467         .nconfig_data = ARRAY_SIZE(t124_pin_drv_group_soc_data),
3468 };
3469
3470 static int tegra124_pinctrl_probe(struct platform_device *pdev)
3471 {
3472         return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
3473 }
3474
3475 static struct of_device_id tegra124_pinctrl_of_match[] = {
3476         { .compatible = "nvidia,tegra124-pinmux", },
3477         { },
3478 };
3479 MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
3480
3481 static struct platform_driver tegra124_pinctrl_driver = {
3482         .driver = {
3483                 .name = "tegra124-pinctrl",
3484                 .owner = THIS_MODULE,
3485                 .of_match_table = tegra124_pinctrl_of_match,
3486         },
3487         .probe = tegra124_pinctrl_probe,
3488         .remove = tegra_pinctrl_remove,
3489 };
3490
3491 static int __init tegra124_pinctrl_init(void)
3492 {
3493         return platform_driver_register(&tegra124_pinctrl_driver);
3494 }
3495 postcore_initcall_sync(tegra124_pinctrl_init);
3496
3497 static void __exit tegra124_pinctrl_exit(void)
3498 {
3499         platform_driver_unregister(&tegra124_pinctrl_driver);
3500 }
3501 module_exit(tegra124_pinctrl_exit);
3502
3503 MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
3504 MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
3505 MODULE_LICENSE("GPL v2");