drivers/video/tegra/dc/sor.c

   1 /*
   2  * drivers/video/tegra/dc/sor.c
   3  *
   4  * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/nvhost.h>
  20 #include <linux/kernel.h>
  21 #include <linux/fb.h>
  22 #include <linux/delay.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/debugfs.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27
  28 #include <mach/dc.h>
  29 #include <mach/io_dpd.h>
  30
  31 #include "sor.h"
  32 #include "sor_regs.h"
  33 #include "dc_priv.h"
  34 #include "dp.h"
  35
  36 #include "../../../../arch/arm/mach-tegra/iomap.h"
  37
  38 #define APBDEV_PMC_DPD_SAMPLE                           (0x20)
  39 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE                (0)
  40 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE                 (1)
  41 #define APBDEV_PMC_SEL_DPD_TIM                          (0x1c8)
  42 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT      (0x7f)
  43 #define APBDEV_PMC_IO_DPD2_REQ                          (0x1c0)
  44 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT               (25)
  45 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF                 (0 << 25)
  46 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON                  (1 << 25)
  47 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT               (30)
  48 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK        (0x3 << 30)
  49 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE                (0 << 30)
  50 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF             (1 << 30)
  51 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON              (2 << 30)
  52 #define APBDEV_PMC_IO_DPD2_STATUS                       (0x1c4)
  53 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT            (25)
  54 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF              (0 << 25)
  55 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON               (1 << 25)
  56
  57 static unsigned long
  58 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
  59                                 u32 reg, u32 mask, u32 exp_val,
  60                                 u32 poll_interval_us, u32 timeout_ms)
  61 {
  62         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
  63         u32 reg_val = 0;
  64
  65         if (tegra_platform_is_linsim())
  66                 return 0;
  67         do {
  68                 reg_val = tegra_sor_readl(sor, reg);
  69                 if ((reg_val & mask) == exp_val)
  70                         return 0;       /* success */
  71
  72                 udelay(poll_interval_us);
  73         } while (time_after(timeout_jf, jiffies));
  74
  75         dev_err(&sor->dc->ndev->dev,
  76                 "sor_poll_register 0x%x: timeout\n", reg);
  77         return jiffies - timeout_jf + 1;
  78 }
  79
  80 void tegra_sor_config_safe_clk(struct tegra_dc_sor_data *sor)
  81 {
  82         int flag = tegra_is_clk_enabled(sor->sor_clk);
  83
  84         if (sor->clk_type == TEGRA_SOR_SAFE_CLK || tegra_platform_is_linsim())
  85                 return;
  86
  87         /*
  88          * HW bug 1425607
  89          * Disable clocks to avoid glitch when switching
  90          * between safe clock and macro pll clock
  91          */
  92         if (flag)
  93                 clk_disable_unprepare(sor->sor_clk);
  94
  95         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 0);
  96
  97         if (flag)
  98                 clk_prepare_enable(sor->sor_clk);
  99
 100         sor->clk_type = TEGRA_SOR_SAFE_CLK;
 101 }
 102
 103 void tegra_sor_config_dp_clk(struct tegra_dc_sor_data *sor)
 104 {
 105         int flag = tegra_is_clk_enabled(sor->sor_clk);
 106         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(sor->dc);
 107
 108         if (sor->clk_type == TEGRA_SOR_MACRO_CLK)
 109                 return;
 110
 111         tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
 112                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
 113                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
 114         tegra_dc_sor_set_link_bandwidth(sor, dp->link_cfg.link_bw ? :
 115                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62);
 116
 117         /*
 118          * HW bug 1425607
 119          * Disable clocks to avoid glitch when switching
 120          * between safe clock and macro pll clock
 121          *
 122          * Select alternative -- DP -- DVFS table for SOR clock (if SOR clock
 123          * has single DVFS table for all modes, nothing changes).
 124          */
 125         if (flag)
 126                 clk_disable_unprepare(sor->sor_clk);
 127
 128         tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, true);
 129
 130         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 1);
 131
 132         if (flag)
 133                 clk_prepare_enable(sor->sor_clk);
 134
 135         sor->clk_type = TEGRA_SOR_MACRO_CLK;
 136 }
 137
 138 #ifdef CONFIG_DEBUG_FS
 139 static int dbg_sor_show(struct seq_file *s, void *unused)
 140 {
 141         struct tegra_dc_sor_data *sor = s->private;
 142
 143 #define DUMP_REG(a) seq_printf(s, "%-32s  %03x  %08x\n",                \
 144                 #a, a, tegra_sor_readl(sor, a));
 145
 146         if (!tegra_powergate_is_powered(TEGRA_POWERGATE_SOR)) {
 147                 seq_puts(s, "SOR is powergated\n");
 148                 return 0;
 149         }
 150
 151         tegra_dc_io_start(sor->dc);
 152         tegra_sor_clk_enable(sor);
 153
 154         DUMP_REG(NV_SOR_SUPER_STATE0);
 155         DUMP_REG(NV_SOR_SUPER_STATE1);
 156         DUMP_REG(NV_SOR_STATE0);
 157         DUMP_REG(NV_SOR_STATE1);
 158         DUMP_REG(NV_HEAD_STATE0(0));
 159         DUMP_REG(NV_HEAD_STATE0(1));
 160         DUMP_REG(NV_HEAD_STATE1(0));
 161         DUMP_REG(NV_HEAD_STATE1(1));
 162         DUMP_REG(NV_HEAD_STATE2(0));
 163         DUMP_REG(NV_HEAD_STATE2(1));
 164         DUMP_REG(NV_HEAD_STATE3(0));
 165         DUMP_REG(NV_HEAD_STATE3(1));
 166         DUMP_REG(NV_HEAD_STATE4(0));
 167         DUMP_REG(NV_HEAD_STATE4(1));
 168         DUMP_REG(NV_HEAD_STATE5(0));
 169         DUMP_REG(NV_HEAD_STATE5(1));
 170         DUMP_REG(NV_SOR_CRC_CNTRL);
 171         DUMP_REG(NV_SOR_CLK_CNTRL);
 172         DUMP_REG(NV_SOR_CAP);
 173         DUMP_REG(NV_SOR_PWR);
 174         DUMP_REG(NV_SOR_TEST);
 175         DUMP_REG(NV_SOR_PLL0);
 176         DUMP_REG(NV_SOR_PLL1);
 177         DUMP_REG(NV_SOR_PLL2);
 178         DUMP_REG(NV_SOR_PLL3);
 179         DUMP_REG(NV_SOR_CSTM);
 180         DUMP_REG(NV_SOR_LVDS);
 181         DUMP_REG(NV_SOR_CRCA);
 182         DUMP_REG(NV_SOR_CRCB);
 183         DUMP_REG(NV_SOR_SEQ_CTL);
 184         DUMP_REG(NV_SOR_LANE_SEQ_CTL);
 185         DUMP_REG(NV_SOR_SEQ_INST(0));
 186         DUMP_REG(NV_SOR_SEQ_INST(1));
 187         DUMP_REG(NV_SOR_SEQ_INST(2));
 188         DUMP_REG(NV_SOR_SEQ_INST(3));
 189         DUMP_REG(NV_SOR_SEQ_INST(4));
 190         DUMP_REG(NV_SOR_SEQ_INST(5));
 191         DUMP_REG(NV_SOR_SEQ_INST(6));
 192         DUMP_REG(NV_SOR_SEQ_INST(7));
 193         DUMP_REG(NV_SOR_SEQ_INST(8));
 194         DUMP_REG(NV_SOR_PWM_DIV);
 195         DUMP_REG(NV_SOR_PWM_CTL);
 196         DUMP_REG(NV_SOR_MSCHECK);
 197         DUMP_REG(NV_SOR_XBAR_CTRL);
 198         DUMP_REG(NV_SOR_XBAR_POL);
 199         DUMP_REG(NV_SOR_DP_LINKCTL(0));
 200         DUMP_REG(NV_SOR_DP_LINKCTL(1));
 201         DUMP_REG(NV_SOR_DC(0));
 202         DUMP_REG(NV_SOR_DC(1));
 203         DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
 204         DUMP_REG(NV_SOR_LANE4_DRIVE_CURRENT(0));
 205         DUMP_REG(NV_SOR_PR(0));
 206         DUMP_REG(NV_SOR_LANE_PREEMPHASIS(0));
 207         DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
 208         DUMP_REG(NV_SOR_POSTCURSOR(0));
 209         DUMP_REG(NV_SOR_DP_CONFIG(0));
 210         DUMP_REG(NV_SOR_DP_CONFIG(1));
 211         DUMP_REG(NV_SOR_DP_MN(0));
 212         DUMP_REG(NV_SOR_DP_MN(1));
 213         DUMP_REG(NV_SOR_DP_PADCTL(0));
 214         DUMP_REG(NV_SOR_DP_PADCTL(1));
 215         DUMP_REG(NV_SOR_DP_DEBUG(0));
 216         DUMP_REG(NV_SOR_DP_DEBUG(1));
 217         DUMP_REG(NV_SOR_DP_SPARE(0));
 218         DUMP_REG(NV_SOR_DP_SPARE(1));
 219         DUMP_REG(NV_SOR_DP_TPG);
 220         DUMP_REG(NV_SOR_HDMI2_CTRL);
 221         if (sor->dc->ndev->id == 1) { /* sor1 */
 222                 DUMP_REG(NV_SOR_DP_AUDIO_CTRL);
 223
 224                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_HEADER);
 225                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(0));
 226                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(1));
 227                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(2));
 228                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(3));
 229                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(4));
 230                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(5));
 231                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(6));
 232
 233                 DUMP_REG(NV_SOR_DP_OUTPUT_CHANNEL_STATUS1);
 234                 DUMP_REG(NV_SOR_DP_OUTPUT_CHANNEL_STATUS2);
 235
 236                 DUMP_REG(NV_SOR_HDMI_AUDIO_N);
 237                 DUMP_REG(NV_SOR_HDMI2_CTRL);
 238
 239                 DUMP_REG(NV_SOR_AUDIO_NVAL_0320);
 240                 DUMP_REG(NV_SOR_AUDIO_NVAL_0441);
 241                 DUMP_REG(NV_SOR_AUDIO_NVAL_0882);
 242                 DUMP_REG(NV_SOR_AUDIO_NVAL_1764);
 243                 DUMP_REG(NV_SOR_AUDIO_NVAL_0480);
 244                 DUMP_REG(NV_SOR_AUDIO_NVAL_0960);
 245                 DUMP_REG(NV_SOR_AUDIO_NVAL_1920);
 246
 247                 DUMP_REG(NV_SOR_AUDIO_AVAL_0320);
 248                 DUMP_REG(NV_SOR_AUDIO_AVAL_0441);
 249                 DUMP_REG(NV_SOR_AUDIO_AVAL_0882);
 250                 DUMP_REG(NV_SOR_AUDIO_AVAL_1764);
 251                 DUMP_REG(NV_SOR_AUDIO_AVAL_0480);
 252                 DUMP_REG(NV_SOR_AUDIO_AVAL_0960);
 253                 DUMP_REG(NV_SOR_AUDIO_AVAL_1920);
 254
 255                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0320);
 256                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0441);
 257                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0882);
 258                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_1764);
 259                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0480);
 260                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0960);
 261                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_1920);
 262
 263
 264         }
 265
 266         tegra_sor_clk_disable(sor);
 267         tegra_dc_io_end(sor->dc);
 268
 269         return 0;
 270 }
 271
 272 static int dbg_sor_open(struct inode *inode, struct file *file)
 273 {
 274         return single_open(file, dbg_sor_show, inode->i_private);
 275 }
 276
 277 static const struct file_operations dbg_fops = {
 278         .open           = dbg_sor_open,
 279         .read           = seq_read,
 280         .llseek         = seq_lseek,
 281         .release        = single_release,
 282 };
 283
 284 static int sor_crc_show(struct seq_file *s, void *unused)
 285 {
 286         struct tegra_dc_sor_data *sor = s->private;
 287         struct tegra_dc *dc = sor->dc;
 288         u32 reg_val;
 289         int i = 0;
 290
 291         tegra_dc_io_start(sor->dc);
 292         tegra_sor_clk_enable(sor);
 293
 294         reg_val = tegra_sor_readl(sor, NV_SOR_CRC_CNTRL);
 295         reg_val &= NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DEFAULT_MASK;
 296         if (reg_val == NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO) {
 297                 pr_err("SOR CRC is DISABLED, aborting with CRC=0\n");
 298                 seq_printf(s, "NV_SOR[%d]_CRCB = 0x%08x\n",
 299                         sor->dc->ctrl_num, reg_val);
 300                 goto exit;
 301         }
 302
 303         do {
 304                 if (tegra_dc_sor_poll_register(sor, NV_SOR_CRCA,
 305                                 NV_SOR_CRCA_VALID_DEFAULT_MASK,
 306                                 NV_SOR_CRCA_VALID_TRUE,
 307                                 100, TEGRA_SOR_TIMEOUT_MS)) {
 308                         dev_err(&sor->dc->ndev->dev,
 309                                 "NV_SOR[%d]_CRCA_VALID_TRUE timeout\n", i);
 310                         goto exit;
 311                 }
 312                 mutex_lock(&dc->lock);
 313                 reg_val = tegra_sor_readl(sor, NV_SOR_CRCB);
 314                 mutex_unlock(&dc->lock);
 315                 seq_printf(s, "NV_SOR[%x]_CRCB = 0x%08x\n",
 316                         sor->dc->ctrl_num, reg_val);
 317                 i++;
 318         } while (i < sor->portnum);
 319
 320 exit:
 321         tegra_sor_clk_disable(sor);
 322         tegra_dc_io_end(sor->dc);
 323
 324         return 0;
 325 }
 326
 327 static int sor_crc_open(struct inode *inode, struct file *file)
 328 {
 329         return single_open(file, sor_crc_show, inode->i_private);
 330 }
 331
 332 static ssize_t sor_crc_write(struct file *file,
 333                                 const char  *buf, size_t count, loff_t *off)
 334 {
 335         struct seq_file *s = file->private_data;
 336         struct tegra_dc_sor_data *sor = s->private;
 337         struct tegra_dc *dc = sor->dc;
 338         u32 reg_val;
 339         u32    data;
 340         int    i = 0;
 341         static u8 asy_crcmode;
 342
 343         if (sscanf(buf, "%x", &data) != 1)
 344                 return -EINVAL;
 345         /* at this point:
 346          * data[0:0] = 1|0: enable|disable CRC
 347          * data[5:4] contains ASY_CRCMODE */
 348
 349         tegra_dc_io_start(sor->dc);
 350         tegra_sor_clk_enable(sor);
 351
 352         asy_crcmode = data & (NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK >> 2);
 353         asy_crcmode >>= 4;  /* asy_crcmode[1:0] = ASY_CRCMODE */
 354         data &= 1;          /* data[0:0] = enable|disable CRC */
 355         mutex_lock(&dc->lock);
 356         do {
 357                 if (data == 1) {
 358                         reg_val = tegra_sor_readl(sor, NV_SOR_CRCA);
 359                         if (reg_val & NV_SOR_CRCA_VALID_TRUE) {
 360                                 tegra_sor_write_field(sor,
 361                                         NV_SOR_CRCA,
 362                                         NV_SOR_CRCA_VALID_DEFAULT_MASK,
 363                                         NV_SOR_CRCA_VALID_RST << NV_SOR_CRCA_VALID_SHIFT);
 364                         }
 365                         tegra_sor_write_field(sor,
 366                                 NV_SOR_TEST,
 367                                 NV_SOR_TEST_CRC_DEFAULT_MASK,
 368                                 NV_SOR_TEST_CRC_PRE_SERIALIZE << NV_SOR_TEST_CRC_SHIFT);
 369                         tegra_sor_write_field(sor, NV_SOR_STATE1,
 370                                 NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK,
 371                                 asy_crcmode << NV_SOR_STATE1_ASY_CRCMODE_SHIFT);
 372                         tegra_sor_write_field(sor,
 373                                 NV_SOR_STATE0,
 374                                 NV_SOR_STATE0_UPDATE_DEFAULT_MASK,
 375                                 NV_SOR_STATE0_UPDATE_UPDATE << NV_SOR_STATE0_UPDATE_SHIFT);
 376                 }
 377                 reg_val = tegra_sor_readl(sor, NV_SOR_CRC_CNTRL);
 378                 tegra_sor_write_field(sor,
 379                         NV_SOR_CRC_CNTRL,
 380                         NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DEFAULT_MASK,
 381                         data << NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT);
 382                 reg_val = tegra_sor_readl(sor, NV_SOR_CRC_CNTRL);
 383                 i++;
 384         } while (i < sor->portnum);
 385
 386         mutex_unlock(&dc->lock);
 387         tegra_sor_clk_disable(sor);
 388         tegra_dc_io_end(sor->dc);
 389
 390         return count;
 391 }
 392
 393 static const struct file_operations crc_fops = {
 394         .open           = sor_crc_open,
 395         .read           = seq_read,
 396         .write          = sor_crc_write,
 397         .llseek         = seq_lseek,
 398         .release        = single_release,
 399 };
 400
 401 static struct dentry *sordir;
 402
 403 static void tegra_dc_sor_debug_create(struct tegra_dc_sor_data *sor,
 404         const char *res_name)
 405 {
 406         struct dentry *retval;
 407         char sor_path[16];
 408
 409         BUG_ON(!res_name);
 410         snprintf(sor_path, sizeof(sor_path), "tegra_%s", res_name ? : "sor");
 411         sordir = debugfs_create_dir(sor_path, NULL);
 412         if (!sordir)
 413                 return;
 414         retval = debugfs_create_file("regs", S_IRUGO, sordir, sor, &dbg_fops);
 415         if (!retval)
 416                 goto free_out;
 417
 418         retval = debugfs_create_file("crc", S_IWUGO|S_IRUGO, sordir,
 419                 sor, &crc_fops);
 420         if (!retval)
 421                 goto free_out;
 422
 423         return;
 424 free_out:
 425         debugfs_remove_recursive(sordir);
 426         sordir = NULL;
 427         return;
 428 }
 429 EXPORT_SYMBOL(tegra_dc_sor_debug_create);
 430 #else
 431 static inline void tegra_dc_sor_debug_create(struct tegra_dc_sor_data *sor,
 432         const char *res_name)
 433 { }
 434 #endif
 435
 436 struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
 437                                 const struct tegra_dc_dp_link_config *cfg)
 438 {
 439         struct tegra_dc_sor_data *sor;
 440         struct resource *res;
 441         struct resource *base_res;
 442         struct resource of_sor_res;
 443         void __iomem *base;
 444         struct clk *clk;
 445         int err, i;
 446         struct clk *safe_clk = NULL;
 447         struct clk *brick_clk = NULL;
 448         struct clk *src_clk = NULL;
 449         struct device_node *np = dc->ndev->dev.of_node;
 450         struct device_node *np_sor =
 451                 dc->ndev->id ? of_find_node_by_path(SOR1_NODE) :
 452                 of_find_node_by_path(SOR_NODE);
 453         const char *res_name = dc->ndev->id ? "sor1" : "sor0";
 454
 455         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
 456                 of_node_put(np_sor);
 457                 np_sor = of_find_node_by_path(SOR1_NODE);
 458                 res_name = "sor1";
 459         }
 460
 461         sor = devm_kzalloc(&dc->ndev->dev, sizeof(*sor), GFP_KERNEL);
 462         if (!sor) {
 463                 err = -ENOMEM;
 464                 goto err_allocate;
 465         }
 466
 467         if (np) {
 468                 if (np_sor && (of_device_is_available(np_sor) ||
 469                         (dc->out->type == TEGRA_DC_OUT_FAKE_DP))) {
 470                         of_address_to_resource(np_sor, 0,
 471                                 &of_sor_res);
 472                         res = &of_sor_res;
 473                 } else {
 474                         err = -EINVAL;
 475                         goto err_free_sor;
 476                 }
 477         } else {
 478                 res = platform_get_resource_byname(dc->ndev,
 479                         IORESOURCE_MEM, res_name);
 480                 if (!res) {
 481                         dev_err(&dc->ndev->dev,
 482                                 "sor: no mem resource\n");
 483                         err = -ENOENT;
 484                         goto err_free_sor;
 485                 }
 486         }
 487
 488         base_res = devm_request_mem_region(&dc->ndev->dev,
 489                 res->start, resource_size(res),
 490                 dc->ndev->name);
 491         if (!base_res) {
 492                 dev_err(&dc->ndev->dev, "sor: request_mem_region failed\n");
 493                 err = -EBUSY;
 494                 goto err_free_sor;
 495         }
 496
 497         base = devm_ioremap(&dc->ndev->dev,
 498                         res->start, resource_size(res));
 499         if (!base) {
 500                 dev_err(&dc->ndev->dev, "sor: registers can't be mapped\n");
 501                 err = -ENOENT;
 502                 goto err_release_resource_reg;
 503         }
 504
 505         clk = clk_get(NULL, res_name);
 506         if (IS_ERR_OR_NULL(clk)) {
 507                 dev_err(&dc->ndev->dev, "sor: can't get clock\n");
 508                 err = -ENOENT;
 509                 goto err_iounmap_reg;
 510         }
 511
 512 #ifndef CONFIG_ARCH_TEGRA_12x_SOC
 513         safe_clk = clk_get(NULL, "sor_safe");
 514         if (IS_ERR_OR_NULL(safe_clk)) {
 515                 dev_err(&dc->ndev->dev, "sor: can't get safe clock\n");
 516                 err = -ENOENT;
 517                 goto err_safe;
 518         }
 519 #ifndef CONFIG_TEGRA_NVDISPLAY
 520         if (!strcmp(res_name, "sor1")) {
 521                 brick_clk = clk_get(NULL, "sor1_brick");
 522                 if (IS_ERR_OR_NULL(brick_clk)) {
 523                         dev_err(&dc->ndev->dev, "sor: can't get brick clock\n");
 524                         err = -ENOENT;
 525                         goto err_brick;
 526                 }
 527                 src_clk = clk_get(NULL, "sor1_src");
 528                 if (IS_ERR_OR_NULL(src_clk)) {
 529                         dev_err(&dc->ndev->dev, "sor: can't get src clock\n");
 530                         err = -ENOENT;
 531                         goto err_src;
 532                 }
 533         }
 534 #endif
 535 #endif
 536
 537         for (i = 0; i < sizeof(sor->xbar_ctrl)/sizeof(u32); i++)
 538                 sor->xbar_ctrl[i] = i;
 539         if (np_sor && of_device_is_available(np_sor))
 540                 of_property_read_u32_array(np_sor, "nvidia,xbar-ctrl",
 541                         sor->xbar_ctrl, sizeof(sor->xbar_ctrl)/sizeof(u32));
 542
 543         sor->dc = dc;
 544         sor->base = base;
 545         sor->res = res;
 546         sor->base_res = base_res;
 547         sor->sor_clk = clk;
 548         sor->safe_clk = safe_clk;
 549         sor->brick_clk = brick_clk;
 550         sor->src_switch_clk = src_clk;
 551         sor->link_cfg = cfg;
 552         sor->portnum = 0;
 553         sor->sor_state = SOR_DETACHED;
 554
 555         tegra_dc_sor_debug_create(sor, res_name);
 556         of_node_put(np_sor);
 557
 558         return sor;
 559
 560 err_src: __maybe_unused
 561         clk_put(brick_clk);
 562 err_brick: __maybe_unused
 563         clk_put(safe_clk);
 564 err_safe: __maybe_unused
 565         clk_put(clk);
 566 err_iounmap_reg:
 567         devm_iounmap(&dc->ndev->dev, base);
 568 err_release_resource_reg:
 569         devm_release_mem_region(&dc->ndev->dev,
 570                 res->start, resource_size(res));
 571         if (!np_sor || !of_device_is_available(np_sor))
 572                 release_resource(res);
 573 err_free_sor:
 574         devm_kfree(&dc->ndev->dev, sor);
 575 err_allocate:
 576         of_node_put(np_sor);
 577         return ERR_PTR(err);
 578 }
 579
 580 int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
 581 {
 582         u32 reg_val;
 583         u32 orig_val;
 584
 585         orig_val = tegra_sor_readl(sor, NV_SOR_PWR);
 586
 587         reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU :
 588                 NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */
 589
 590         if (reg_val == orig_val)
 591                 return 0;       /* No update needed */
 592
 593         reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER;
 594         tegra_sor_writel(sor, NV_SOR_PWR, reg_val);
 595
 596         /* Poll to confirm it is done */
 597         if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
 598                         NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
 599                         NV_SOR_PWR_SETTING_NEW_DONE,
 600                         100, TEGRA_SOR_TIMEOUT_MS)) {
 601                 dev_err(&sor->dc->ndev->dev,
 602                         "dc timeout waiting for SOR_PWR = NEW_DONE\n");
 603                 return -EFAULT;
 604         }
 605         return 0;
 606 }
 607
 608
 609 void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor)
 610 {
 611         struct device_node *np_sor = (sor->dc->ndev->id) ?
 612                 of_find_node_by_path(SOR1_NODE) :
 613                 of_find_node_by_path(SOR_NODE);
 614
 615         if (sor->dc->out->type == TEGRA_DC_OUT_HDMI) {
 616                 of_node_put(np_sor);
 617                 np_sor = of_find_node_by_path(SOR1_NODE);
 618         }
 619
 620         clk_put(sor->sor_clk);
 621         if (sor->safe_clk)
 622                 clk_put(sor->safe_clk);
 623         if (sor->brick_clk)
 624                 clk_put(sor->brick_clk);
 625         if (sor->src_switch_clk)
 626                 clk_put(sor->src_switch_clk);
 627         devm_iounmap(&sor->dc->ndev->dev, sor->base);
 628         devm_release_mem_region(&sor->dc->ndev->dev,
 629                 sor->res->start, resource_size(sor->res));
 630
 631         if (!np_sor || !of_device_is_available(np_sor))
 632                 release_resource(sor->res);
 633         devm_kfree(&sor->dc->ndev->dev, sor);
 634         of_node_put(np_sor);
 635 }
 636
 637 void tegra_sor_tpg(struct tegra_dc_sor_data *sor, u32 tp, u32 n_lanes)
 638 {
 639         u32 const tbl[][2] = {
 640                 /* ansi8b/10b encoded, scrambled */
 641                 {1, 1}, /* no pattern, training not in progress */
 642                 {1, 0}, /* training pattern 1 */
 643                 {1, 0}, /* training pattern 2 */
 644                 {1, 0}, /* training pattern 3 */
 645         };
 646         u32 cnt;
 647         u32 val = 0;
 648
 649         for (cnt = 0; cnt < n_lanes; cnt++) {
 650                 u32 tp_shift = NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT * cnt;
 651                 val |= tp << tp_shift |
 652                         tbl[tp][0] << (tp_shift +
 653                         NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT) |
 654                         tbl[tp][1] << (tp_shift +
 655                         NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT);
 656         }
 657
 658         tegra_sor_writel(sor, NV_SOR_DP_TPG, val);
 659 }
 660
 661 void tegra_sor_port_enable(struct tegra_dc_sor_data *sor, bool enb)
 662 {
 663         tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
 664                         NV_SOR_DP_LINKCTL_ENABLE_YES,
 665                         (enb ? NV_SOR_DP_LINKCTL_ENABLE_YES :
 666                         NV_SOR_DP_LINKCTL_ENABLE_NO));
 667 }
 668
 669 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, bool ena,
 670         u8 training_pattern, const struct tegra_dc_dp_link_config *cfg)
 671 {
 672         u32 reg_val;
 673
 674         reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
 675
 676         if (ena)
 677                 reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES;
 678         else
 679                 reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO;
 680
 681         reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK;
 682         reg_val |= (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT);
 683
 684         if (cfg->enhanced_framing)
 685                 reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE;
 686
 687         tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
 688
 689         switch (training_pattern) {
 690         case TRAINING_PATTERN_1:
 691                 tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141);
 692                 break;
 693         case TRAINING_PATTERN_2:
 694         case TRAINING_PATTERN_3:
 695                 reg_val = (cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
 696                         0x43434343 : 0x42424242;
 697                 tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val);
 698                 break;
 699         default:
 700                 tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050);
 701                 break;
 702         }
 703 }
 704
 705 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
 706                                                         bool pu, bool is_lvds)
 707 {
 708         u32 reg_val;
 709
 710         /* SOR lane sequencer */
 711         if (pu)
 712                 reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 713                         NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 714                         NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU;
 715         else
 716                 reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 717                         NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 718                         NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD;
 719
 720         if (is_lvds)
 721                 reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
 722         else
 723                 reg_val |= 5 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
 724
 725         if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
 726                         NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY,
 727                         NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE,
 728                         100, TEGRA_SOR_SEQ_BUSY_TIMEOUT_MS)) {
 729                 dev_dbg(&sor->dc->ndev->dev,
 730                         "dp: timeout, sor lane sequencer busy\n");
 731                 return -EFAULT;
 732         }
 733
 734         tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val);
 735
 736         if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
 737                         NV_SOR_LANE_SEQ_CTL_SETTING_MASK,
 738                         NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE,
 739                         100, TEGRA_SOR_TIMEOUT_MS)) {
 740                 dev_dbg(&sor->dc->ndev->dev,
 741                         "dp: timeout, SOR lane sequencer power up/down\n");
 742                 return -EFAULT;
 743         }
 744         return 0;
 745 }
 746
 747 int tegra_sor_power_lanes(struct tegra_dc_sor_data *sor,
 748                                         u32 lane_count, bool pu)
 749 {
 750         u32 val = 0;
 751         u8 pd_txd_0_no = NV_SOR_DP_PADCTL_PD_TXD_0_NO,
 752                 pd_txd_2_no = NV_SOR_DP_PADCTL_PD_TXD_2_NO;
 753
 754 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_TEGRA_NVDISPLAY)
 755         pd_txd_0_no = NV_SOR_DP_PADCTL_PD_TXD_2_NO;
 756         pd_txd_2_no = NV_SOR_DP_PADCTL_PD_TXD_0_NO;
 757 #endif
 758
 759         if (pu) {
 760                 switch (lane_count) {
 761                 /* T210 boards need to swap lanes 0 and 2 - bug 1545275 */
 762                 case 4:
 763                         val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | pd_txd_2_no);
 764                         /* fall through */
 765                 case 2:
 766                         val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
 767                 case 1:
 768                         val |= pd_txd_0_no;
 769                         break;
 770                 default:
 771                         dev_dbg(&sor->dc->ndev->dev,
 772                                 "dp: invalid lane number %d\n", lane_count);
 773                         return -EFAULT;
 774                 }
 775
 776                 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
 777                                                 NV_SOR_DP_PADCTL_PD_TXD_MASK, val);
 778                 tegra_dc_sor_set_lane_count(sor, lane_count);
 779         }
 780
 781         return tegra_dc_sor_enable_lane_sequencer(sor, pu, false);
 782 }
 783
 784 /* power on/off pad calibration logic */
 785 void tegra_sor_pad_cal_power(struct tegra_dc_sor_data *sor,
 786                                         bool power_up)
 787 {
 788         u32 val = power_up ? NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP :
 789                         NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
 790
 791         /* !!TODO: need to enable panel power through GPIO operations */
 792         /* Check bug 790854 for HW progress */
 793
 794         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
 795                                 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, val);
 796 }
 797
 798 void tegra_dc_sor_termination_cal(struct tegra_dc_sor_data *sor)
 799 {
 800         u32 termadj;
 801         u32 cur_try;
 802         u32 reg_val;
 803
 804         termadj = cur_try = 0x8;
 805
 806         tegra_sor_write_field(sor, NV_SOR_PLL1,
 807                 NV_SOR_PLL1_TMDS_TERMADJ_DEFAULT_MASK |
 808                 NV_SOR_PLL1_TMDS_TERM_ENABLE,
 809                 NV_SOR_PLL1_TMDS_TERM_ENABLE |
 810                 termadj << NV_SOR_PLL1_TMDS_TERMADJ_SHIFT);
 811
 812         while (cur_try) {
 813                 /* binary search the right value */
 814                 usleep_range(100, 200);
 815                 reg_val = tegra_sor_readl(sor, NV_SOR_PLL1);
 816
 817                 if (reg_val & NV_SOR_PLL1_TERM_COMPOUT_HIGH)
 818                         termadj -= cur_try;
 819                 cur_try >>= 1;
 820                 termadj += cur_try;
 821
 822                 tegra_sor_write_field(sor, NV_SOR_PLL1,
 823                         NV_SOR_PLL1_TMDS_TERMADJ_DEFAULT_MASK,
 824                         termadj << NV_SOR_PLL1_TMDS_TERMADJ_SHIFT);
 825         }
 826 }
 827
 828 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
 829         u32 pwm_dutycycle)
 830 {
 831         tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div);
 832         tegra_sor_writel(sor, NV_SOR_PWM_CTL,
 833                 (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) |
 834                 NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER);
 835
 836         if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL,
 837                         NV_SOR_PWM_CTL_SETTING_NEW_SHIFT,
 838                         NV_SOR_PWM_CTL_SETTING_NEW_DONE,
 839                         100, TEGRA_SOR_TIMEOUT_MS)) {
 840                 dev_dbg(&sor->dc->ndev->dev,
 841                         "dp: timeout while waiting for SOR PWM setting\n");
 842         }
 843 }
 844
 845 void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
 846         const struct tegra_dc_dp_link_config *cfg)
 847 {
 848         u32 reg_val;
 849
 850         BUG_ON(!cfg || !cfg->is_valid);
 851
 852         tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
 853
 854         tegra_dc_sor_set_dp_linkctl(sor, true, TRAINING_PATTERN_DISABLE, cfg);
 855         reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
 856         reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
 857         reg_val |= cfg->watermark;
 858         reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
 859         reg_val |= (cfg->active_count <<
 860                 NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
 861         reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
 862         reg_val |= (cfg->active_frac <<
 863                 NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
 864         if (cfg->activepolarity)
 865                 reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 866         else
 867                 reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 868         reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
 869                 NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
 870
 871         tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
 872
 873         /* program h/vblank sym */
 874         tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
 875                 NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, cfg->hblank_sym);
 876
 877         tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
 878                 NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, cfg->vblank_sym);
 879 }
 880
 881 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
 882 {
 883         tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
 884         tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 1);
 885         tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
 886 }
 887
 888 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
 889 {
 890         tegra_sor_writel(sor, NV_SOR_STATE0, 0);
 891         tegra_sor_writel(sor, NV_SOR_STATE0, 1);
 892         tegra_sor_writel(sor, NV_SOR_STATE0, 0);
 893 }
 894
 895 static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, bool up)
 896 {
 897         u32 reg_val;
 898         static void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 899         unsigned long timeout_jf;
 900
 901         if (tegra_platform_is_linsim())
 902                 return;
 903
 904         if (up) {
 905                 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
 906                         pmc_base + APBDEV_PMC_DPD_SAMPLE);
 907                 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
 908         }
 909
 910         reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 911         reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
 912                 APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
 913
 914         reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
 915                 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
 916                 APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
 917                 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
 918
 919         writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 920
 921         /* Polling */
 922         timeout_jf = jiffies + msecs_to_jiffies(10);
 923         do {
 924                 usleep_range(20, 40);
 925                 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
 926         } while (((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) &&
 927                 time_after(timeout_jf, jiffies));
 928
 929         if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0)
 930                 dev_err(&sor->dc->ndev->dev,
 931                         "PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
 932
 933         if (up)
 934                 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
 935                         pmc_base + APBDEV_PMC_DPD_SAMPLE);
 936 }
 937
 938 /* hdmi uses sor sequencer for pad power up */
 939 void tegra_sor_hdmi_pad_power_up(struct tegra_dc_sor_data *sor)
 940 {
 941         struct tegra_io_dpd hdmi_dpd = {
 942                 .name = "hdmi",
 943                 .io_dpd_reg_index = 0,
 944                 .io_dpd_bit = 28,
 945         };
 946         /* seamless */
 947         if (sor->dc->initialized)
 948                 return;
 949         tegra_io_dpd_disable(&hdmi_dpd);
 950         mdelay(50);
 951
 952         tegra_sor_write_field(sor, NV_SOR_PLL2,
 953                                 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE,
 954                                 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE);
 955         tegra_sor_write_field(sor, NV_SOR_PLL2,
 956                                 NV_SOR_PLL2_AUX2_MASK,
 957                                 NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN);
 958         tegra_sor_write_field(sor, NV_SOR_PLL2,
 959                                 NV_SOR_PLL2_AUX1_SEQ_MASK,
 960                                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE);
 961         tegra_sor_write_field(sor, NV_SOR_PLL2,
 962                                 NV_SOR_PLL2_AUX0_MASK,
 963                                 NV_SOR_PLL2_AUX0_SEQ_PLL_PULLDOWN_OVERRIDE);
 964         mdelay(100);
 965
 966         tegra_sor_write_field(sor, NV_SOR_PLL0, NV_SOR_PLL0_PWR_MASK,
 967                                                 NV_SOR_PLL0_PWR_ON);
 968         tegra_sor_write_field(sor, NV_SOR_PLL0, NV_SOR_PLL0_VCOPD_MASK,
 969                                                 NV_SOR_PLL0_VCOPD_RESCIND);
 970         mdelay(100);
 971
 972         tegra_sor_write_field(sor, NV_SOR_PLL2,
 973                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 974                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 975         tegra_sor_write_field(sor, NV_SOR_PLL2,
 976                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 977                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 978         tegra_sor_write_field(sor, NV_SOR_PLL2,
 979                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
 980                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 981         tegra_sor_write_field(sor, NV_SOR_PLL2,
 982                                 NV_SOR_PLL2_CLKGEN_MODE_MASK,
 983                                 NV_SOR_PLL2_CLKGEN_MODE_DP_TMDS);
 984         mdelay(100);
 985
 986         tegra_sor_write_field(sor, NV_SOR_PLL1,
 987                                 NV_SOR_PLL1_TMDS_TERM_ENABLE,
 988                                 NV_SOR_PLL1_TMDS_TERM_ENABLE);
 989 }
 990
 991 void tegra_sor_hdmi_pad_power_down(struct tegra_dc_sor_data *sor)
 992 {
 993         struct tegra_io_dpd hdmi_dpd = {
 994                 .name = "hdmi",
 995                 .io_dpd_reg_index = 0,
 996                 .io_dpd_bit = 28,
 997         };
 998
 999         tegra_sor_write_field(sor, NV_SOR_PLL2,
1000                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
1001                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE);
1002         usleep_range(25, 30);
1003
1004         tegra_sor_write_field(sor, NV_SOR_PLL0, NV_SOR_PLL0_PWR_MASK |
1005                                 NV_SOR_PLL0_VCOPD_MASK, NV_SOR_PLL0_PWR_OFF |
1006                                 NV_SOR_PLL0_VCOPD_ASSERT);
1007         tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX1_SEQ_MASK |
1008                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1009                                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
1010                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
1011         usleep_range(25, 30);
1012
1013         tegra_sor_write_field(sor, NV_SOR_PLL2,
1014                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1015                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE);
1016
1017         tegra_io_dpd_enable(&hdmi_dpd);
1018 }
1019
1020 void tegra_sor_config_hdmi_clk(struct tegra_dc_sor_data *sor)
1021 {
1022         int flag = tegra_is_clk_enabled(sor->sor_clk);
1023
1024         if (sor->clk_type == TEGRA_SOR_MACRO_CLK)
1025                 return;
1026
1027         tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
1028                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
1029                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK);
1030         tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_G2_7);
1031
1032         /*
1033          * HW bug 1425607
1034          * Disable clocks to avoid glitch when switching
1035          * between safe clock and macro pll clock
1036          */
1037         if (flag)
1038                 clk_disable_unprepare(sor->sor_clk);
1039
1040         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
1041
1042         if (flag)
1043                 clk_prepare_enable(sor->sor_clk);
1044
1045         sor->clk_type = TEGRA_SOR_MACRO_CLK;
1046 }
1047
1048 /* The SOR power sequencer does not work for t124 so SW has to
1049    go through the power sequence manually */
1050 /* Power up steps from spec: */
1051 /* STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL */
1052 /* 1    1       1       1       1       1       1       1 */
1053 /* 2    1       1       1       1       1       0       1 */
1054 /* 3    1       1       0       1       1       0       1 */
1055 /* 4    1       0       0       0       0       0       1 */
1056 /* 5    0       0       0       0       0       0       1 */
1057 static void tegra_sor_pad_power_up(struct tegra_dc_sor_data *sor,
1058                                         bool is_lvds)
1059 {
1060         if (sor->power_is_up)
1061                 return;
1062
1063         /* step 1 */
1064         tegra_sor_write_field(sor, NV_SOR_PLL2,
1065                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
1066                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
1067                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
1068                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE |
1069                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
1070                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
1071         tegra_sor_write_field(sor, NV_SOR_PLL0,
1072                 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
1073                 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
1074                 NV_SOR_PLL0_PWR_OFF |
1075                 NV_SOR_PLL0_VCOPD_ASSERT);
1076         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
1077                 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
1078                 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN);
1079
1080         /* step 2 */
1081         tegra_dc_sor_io_set_dpd(sor, true);
1082         usleep_range(5, 100);   /* sleep > 5us */
1083
1084         /* step 3 */
1085         tegra_sor_write_field(sor, NV_SOR_PLL2,
1086                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1087                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
1088         usleep_range(20, 100);  /* sleep > 20 us */
1089
1090         /* step 4 */
1091         tegra_sor_write_field(sor, NV_SOR_PLL0,
1092                 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
1093                 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
1094                 NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
1095         tegra_sor_write_field(sor, NV_SOR_PLL2,
1096                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
1097                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
1098         usleep_range(200, 1000);
1099
1100         /* step 5 */
1101         tegra_sor_write_field(sor, NV_SOR_PLL2,
1102                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
1103                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
1104
1105         sor->power_is_up = true;
1106 }
1107
1108 /* Powerdown steps from the spec: */
1109 /* STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL */
1110 /* 1    0       0       0       0       0       0       1 */
1111 /* 2    1       0       0       0       0       0       1 */
1112 /* 3    1       1       0       1       1       0       1 */
1113 /* 4    1       1       1       1       1       0       1 */
1114 /* 5    1       1       1       1       1       1       1 */
1115 static void tegra_dc_sor_power_down(struct tegra_dc_sor_data *sor)
1116 {
1117         if (!sor->power_is_up)
1118                 return;
1119
1120         /* step 1 -- not necessary */
1121
1122         /* step 2 */
1123         tegra_sor_write_field(sor, NV_SOR_PLL2,
1124                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
1125                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE);
1126         udelay(5);      /* sleep > 5us */
1127
1128         /* step 3 */
1129         tegra_sor_write_field(sor, NV_SOR_PLL0,
1130                 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
1131                 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
1132                 NV_SOR_PLL0_PWR_OFF | NV_SOR_PLL0_VCOPD_ASSERT);
1133         tegra_sor_write_field(sor, NV_SOR_PLL2,
1134                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
1135                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
1136         udelay(5);      /* sleep > 5us */
1137
1138         /* step 4 */
1139         tegra_sor_write_field(sor, NV_SOR_PLL2,
1140                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1141                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE);
1142         udelay(5);
1143
1144         /* step 5 */
1145         tegra_dc_sor_io_set_dpd(sor, false);
1146
1147         sor->power_is_up = false;
1148 }
1149
1150
1151 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
1152                                                 bool is_lvds)
1153 {
1154         struct tegra_dc *dc = sor->dc;
1155         const struct tegra_dc_mode *dc_mode = &dc->mode;
1156         int head_num = dc->ctrl_num;
1157         u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
1158         u32 vtotal, htotal;
1159         u32 vsync_end, hsync_end;
1160         u32 vblank_end, hblank_end;
1161         u32 vblank_start, hblank_start;
1162         int out_type = dc->out->type;
1163
1164         if (out_type == TEGRA_DC_OUT_HDMI)
1165                 reg_val |= NV_SOR_STATE1_ASY_PROTOCOL_SINGLE_TMDS_A;
1166         else if ((out_type == TEGRA_DC_OUT_DP) ||
1167                 (out_type == TEGRA_DC_OUT_NVSR_DP) ||
1168                 (out_type == TEGRA_DC_OUT_FAKE_DP))
1169                 reg_val |= NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
1170         else
1171                 reg_val |= NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM;
1172
1173         reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE |
1174                 NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER;
1175
1176         if (dc_mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1177                 reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
1178         else
1179                 reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE;
1180
1181         if (dc_mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1182                 reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
1183         else
1184                 reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE;
1185
1186         reg_val |= (dc->out->depth > 18 || !dc->out->depth) ?
1187                 NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
1188                 NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
1189
1190         tegra_sor_writel(sor, NV_SOR_STATE1, reg_val);
1191
1192         /* Skipping programming NV_HEAD_STATE0, assuming:
1193            interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */
1194
1195         BUG_ON(!dc_mode);
1196         vtotal = dc_mode->v_sync_width + dc_mode->v_back_porch +
1197                 dc_mode->v_active + dc_mode->v_front_porch;
1198         htotal = dc_mode->h_sync_width + dc_mode->h_back_porch +
1199                 dc_mode->h_active + dc_mode->h_front_porch;
1200         tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
1201                 vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
1202                 htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
1203
1204         vsync_end = dc_mode->v_sync_width - 1;
1205         hsync_end = dc_mode->h_sync_width - 1;
1206         tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
1207                 vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
1208                 hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
1209
1210         vblank_end = vsync_end + dc_mode->v_back_porch;
1211         hblank_end = hsync_end + dc_mode->h_back_porch;
1212         tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
1213                 vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
1214                 hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
1215
1216         vblank_start = vblank_end + dc_mode->v_active;
1217         hblank_start = hblank_end + dc_mode->h_active;
1218         tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
1219                 vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
1220                 hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
1221
1222         /* TODO: adding interlace mode support */
1223         tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
1224
1225         tegra_sor_write_field(sor, NV_SOR_CSTM,
1226                 NV_SOR_CSTM_ROTCLK_DEFAULT_MASK |
1227                 NV_SOR_CSTM_LVDS_EN_ENABLE,
1228                 2 << NV_SOR_CSTM_ROTCLK_SHIFT |
1229                 is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
1230                 NV_SOR_CSTM_LVDS_EN_DISABLE);
1231
1232         tegra_dc_sor_config_pwm(sor, 1024, 1024);
1233
1234         tegra_dc_sor_update(sor);
1235 }
1236
1237 static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
1238 {
1239         struct tegra_dc *dc = sor->dc;
1240         u32 reg_val;
1241
1242         tegra_dc_get(dc);
1243
1244         reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1245 #ifndef CONFIG_TEGRA_NVDISPLAY
1246         tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1247 #else
1248         tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1249 #endif /* CONFIG_TEGRA_NVDISPLAY */
1250
1251         if (tegra_platform_is_fpga()) {
1252                 tegra_dc_writel(dc, 0, DC_DISP_DISP_CLOCK_CONTROL);
1253                 tegra_dc_writel(dc, 0xe, DC_DISP_DC_MCCIF_FIFOCTRL);
1254         }
1255
1256 #ifndef CONFIG_TEGRA_NVDISPLAY
1257         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
1258 #endif
1259
1260         /* Enable DC */
1261         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1262         tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
1263
1264         tegra_dc_put(dc);
1265 }
1266
1267 static void tegra_dc_sor_attach_lvds(struct tegra_dc_sor_data *sor)
1268 {
1269         /* Set head owner */
1270         tegra_sor_write_field(sor, NV_SOR_STATE1,
1271                 NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK,
1272                 NV_SOR_STATE1_ASY_SUBOWNER_BOTH);
1273
1274         tegra_dc_sor_update(sor);
1275
1276         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1277                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1278                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1279                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1280         tegra_dc_sor_super_update(sor);
1281
1282         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1283                         NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
1284                         NV_SOR_TEST_ATTACHED_TRUE,
1285                         100, TEGRA_SOR_TIMEOUT_MS)) {
1286                 dev_err(&sor->dc->ndev->dev,
1287                         "dc timeout waiting for ATTACHED = TRUE\n");
1288                 return;
1289         }
1290
1291         /* OR mode: normal */
1292         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1293                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1294                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1295                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1296         tegra_dc_sor_super_update(sor);
1297
1298         /* then awake */
1299         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1300                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1301                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1302                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1303         tegra_dc_sor_super_update(sor);
1304
1305 }
1306
1307 static void tegra_sor_dp_cal(struct tegra_dc_sor_data *sor)
1308 {
1309         tegra_sor_pad_cal_power(sor, true);
1310
1311         tegra_sor_write_field(sor, NV_SOR_PLL2,
1312                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1313                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
1314         usleep_range(20, 100);
1315
1316         tegra_sor_write_field(sor, NV_SOR_PLL3,
1317                 NV_SOR_PLL3_PLLVDD_MODE_MASK,
1318                 NV_SOR_PLL3_PLLVDD_MODE_V3_3);
1319         tegra_sor_writel(sor, NV_SOR_PLL0,
1320                 0x1 << NV_SOR_PLL0_ICHPMP_SHFIT |
1321                 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT |
1322                 NV_SOR_PLL0_PLLREG_LEVEL_V45 |
1323                 NV_SOR_PLL0_RESISTORSEL_EXT |
1324                 NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
1325         tegra_sor_write_field(sor, NV_SOR_PLL2,
1326                 NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
1327                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1328                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
1329                 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
1330                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
1331         tegra_sor_writel(sor, NV_SOR_PLL1,
1332                 NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE |
1333                 0x0 << NV_SOR_PLL1_LVDSCM_SHIFT);
1334
1335         if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2,
1336                         NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1337                         NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
1338                         100, TEGRA_SOR_TIMEOUT_MS)) {
1339                 dev_err(&sor->dc->ndev->dev, "DP failed to lock PLL\n");
1340                 return;
1341         }
1342
1343         tegra_sor_write_field(sor, NV_SOR_PLL2,
1344                 NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
1345                 NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
1346                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
1347
1348         tegra_dc_sor_termination_cal(sor);
1349
1350         tegra_sor_pad_cal_power(sor, false);
1351 }
1352
1353 static inline void tegra_sor_reset(struct tegra_dc_sor_data *sor)
1354 {
1355         if (tegra_platform_is_linsim())
1356                 return;
1357
1358         tegra_periph_reset_assert(sor->sor_clk);
1359         mdelay(2);
1360         tegra_periph_reset_deassert(sor->sor_clk);
1361         mdelay(1);
1362 }
1363
1364 void tegra_sor_config_xbar(struct tegra_dc_sor_data *sor)
1365 {
1366         u32 val = 0, mask = 0, shift = 0;
1367         u32 i = 0;
1368
1369         mask = (NV_SOR_XBAR_BYPASS_MASK | NV_SOR_XBAR_LINK_SWAP_MASK);
1370         for (i = 0, shift = 2; i < sizeof(sor->xbar_ctrl)/sizeof(u32);
1371                 shift += 3, i++) {
1372                 mask |= NV_SOR_XBAR_LINK_SWAP_MASK << shift;
1373                 val |= sor->xbar_ctrl[i] << shift;
1374         }
1375
1376         tegra_sor_write_field(sor, NV_SOR_XBAR_CTRL, mask, val);
1377         tegra_sor_writel(sor, NV_SOR_XBAR_POL, 0);
1378 }
1379
1380 void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
1381 {
1382         tegra_sor_reset(sor);
1383
1384         tegra_sor_config_safe_clk(sor);
1385         tegra_sor_clk_enable(sor);
1386
1387         tegra_sor_dp_cal(sor);
1388
1389         tegra_sor_pad_power_up(sor, false);
1390 }
1391
1392 static void tegra_dc_sor_enable_sor(struct tegra_dc_sor_data *sor, bool enable)
1393 {
1394         struct tegra_dc *dc = sor->dc;
1395         u32 reg_val = tegra_dc_readl(sor->dc, DC_DISP_DISP_WIN_OPTIONS);
1396         u32 enb = dc->ndev->id ? SOR1_ENABLE : SOR_ENABLE;
1397
1398         /* Do not disable SOR during seamless boot */
1399         if (sor->dc->initialized && !enable)
1400                 return;
1401
1402         if (sor->dc->out->type == TEGRA_DC_OUT_HDMI)
1403                 enb = SOR1_ENABLE;
1404
1405         if (dc->out->type == TEGRA_DC_OUT_HDMI)
1406                 enb |= SOR1_TIMING_CYA;
1407
1408         reg_val = enable ? reg_val | enb : reg_val & ~enb;
1409
1410         tegra_dc_writel(dc, reg_val, DC_DISP_DISP_WIN_OPTIONS);
1411 }
1412
1413 void tegra_sor_start_dc(struct tegra_dc_sor_data *sor)
1414 {
1415         struct tegra_dc *dc = sor->dc;
1416         u32 reg_val;
1417
1418         if (sor->sor_state == SOR_ATTACHED)
1419                 return;
1420
1421         tegra_dc_get(dc);
1422         reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1423 #ifndef CONFIG_TEGRA_NVDISPLAY
1424         tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1425 #else
1426         tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1427 #endif /* CONFIG_TEGRA_NVDISPLAY */
1428         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1429         tegra_dc_sor_enable_sor(sor, true);
1430
1431         tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
1432         tegra_dc_put(dc);
1433 }
1434
1435 void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
1436 {
1437         struct tegra_dc *dc = sor->dc;
1438         u32 reg_val;
1439
1440         if (sor->sor_state == SOR_ATTACHED)
1441                 return;
1442
1443         tegra_dc_get(dc);
1444
1445         reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1446 #ifndef CONFIG_TEGRA_NVDISPLAY
1447         tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1448 #else
1449         tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1450 #endif /* CONFIG_TEGRA_NVDISPLAY */
1451
1452         tegra_dc_sor_config_panel(sor, false);
1453
1454         /* WAR for bug 1428181 */
1455         tegra_dc_sor_enable_sor(sor, true);
1456         tegra_dc_sor_enable_sor(sor, false);
1457
1458 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
1459         /* Awake request */
1460         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1461                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1462                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1463                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1464         tegra_dc_sor_super_update(sor);
1465
1466         tegra_dc_sor_enable_dc(sor);
1467
1468         tegra_dc_sor_enable_sor(sor, true);
1469
1470         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1471                 NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
1472                 NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE,
1473                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1474                 dev_err(&dc->ndev->dev,
1475                         "dc timeout waiting for OPMOD = AWAKE\n");
1476         }
1477 #else
1478         tegra_dc_sor_update(sor);
1479
1480         /* Sleep request */
1481         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1482                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1483                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1484                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1485         tegra_dc_sor_super_update(sor);
1486
1487         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1488                 NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
1489                 NV_SOR_TEST_ATTACHED_TRUE,
1490                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1491                 dev_err(&dc->ndev->dev,
1492                         "dc timeout waiting for ATTACH = TRUE\n");
1493         }
1494
1495         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1496                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1497                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1498                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1499         tegra_dc_sor_super_update(sor);
1500
1501         tegra_dc_sor_enable_dc(sor);
1502
1503         tegra_dc_sor_enable_sor(sor, true);
1504
1505         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1506                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1507                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1508                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1509         tegra_dc_sor_super_update(sor);
1510
1511 #endif
1512
1513         tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
1514         tegra_dc_put(dc);
1515
1516         sor->sor_state = SOR_ATTACHED;
1517 }
1518
1519 static struct tegra_dc_mode min_mode = {
1520         .h_ref_to_sync = 0,
1521         .v_ref_to_sync = 1,
1522         .h_sync_width = 1,
1523         .v_sync_width = 1,
1524         .h_back_porch = 20,
1525         .v_back_porch = 0,
1526         .h_active = 16,
1527         .v_active = 16,
1528         .h_front_porch = 1,
1529         .v_front_porch = 2,
1530 };
1531
1532 /* Disable windows and set minimum raster timings */
1533 static void
1534 tegra_dc_sor_disable_win_short_raster(struct tegra_dc *dc, int *dc_reg_ctx)
1535 {
1536         int selected_windows, i;
1537
1538         if (tegra_platform_is_linsim())
1539                 return;
1540         selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
1541
1542         /* Store and clear window options */
1543         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1544                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1545                         DC_CMD_DISPLAY_WINDOW_HEADER);
1546                 dc_reg_ctx[i] = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
1547                 tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1548                 tegra_dc_writel(dc, WIN_A_ACT_REQ << i, DC_CMD_STATE_CONTROL);
1549         }
1550
1551         tegra_dc_writel(dc, selected_windows, DC_CMD_DISPLAY_WINDOW_HEADER);
1552
1553         /* Store current raster timings and set minimum timings */
1554         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
1555         tegra_dc_writel(dc, min_mode.h_ref_to_sync |
1556                 (min_mode.v_ref_to_sync << 16), DC_DISP_REF_TO_SYNC);
1557
1558         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_SYNC_WIDTH);
1559         tegra_dc_writel(dc, min_mode.h_sync_width |
1560                 (min_mode.v_sync_width << 16), DC_DISP_SYNC_WIDTH);
1561
1562         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_BACK_PORCH);
1563         tegra_dc_writel(dc, min_mode.h_back_porch |
1564                 ((min_mode.v_back_porch - min_mode.v_ref_to_sync) << 16),
1565                 DC_DISP_BACK_PORCH);
1566
1567         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_FRONT_PORCH);
1568         tegra_dc_writel(dc, min_mode.h_front_porch |
1569                 ((min_mode.v_front_porch + min_mode.v_ref_to_sync) << 16),
1570                 DC_DISP_FRONT_PORCH);
1571
1572         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_DISP_ACTIVE);
1573         tegra_dc_writel(dc, min_mode.h_active | (min_mode.v_active << 16),
1574                         DC_DISP_DISP_ACTIVE);
1575
1576         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1577 }
1578
1579 /* Restore previous windows status and raster timings */
1580 static void
1581 tegra_dc_sor_restore_win_and_raster(struct tegra_dc *dc, int *dc_reg_ctx)
1582 {
1583         int selected_windows, i;
1584
1585         if (tegra_platform_is_linsim())
1586                 return;
1587
1588         selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
1589
1590         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1591                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1592                         DC_CMD_DISPLAY_WINDOW_HEADER);
1593                 tegra_dc_writel(dc, dc_reg_ctx[i], DC_WIN_WIN_OPTIONS);
1594                 tegra_dc_writel(dc, WIN_A_ACT_REQ << i, DC_CMD_STATE_CONTROL);
1595         }
1596
1597         tegra_dc_writel(dc, selected_windows, DC_CMD_DISPLAY_WINDOW_HEADER);
1598
1599         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_REF_TO_SYNC);
1600         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_SYNC_WIDTH);
1601         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_BACK_PORCH);
1602         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_FRONT_PORCH);
1603         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_DISP_ACTIVE);
1604
1605         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1606 }
1607
1608 void tegra_sor_stop_dc(struct tegra_dc_sor_data *sor)
1609 {
1610         struct tegra_dc *dc = sor->dc;
1611
1612         tegra_dc_get(dc);
1613
1614 #if defined(CONFIG_TEGRA_NVDISPLAY)
1615         /*SOR should be attached if the Display command != STOP */
1616         /* Stop DC */
1617         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1618         tegra_dc_enable_general_act(dc);
1619
1620         /* Stop DC->SOR path */
1621         tegra_dc_sor_enable_sor(sor, false);
1622 #else
1623         /* Stop DC->SOR path */
1624         tegra_dc_sor_enable_sor(sor, false);
1625         tegra_dc_enable_general_act(dc);
1626
1627         /* Stop DC */
1628         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1629 #endif
1630         tegra_dc_enable_general_act(dc);
1631
1632         tegra_dc_put(dc);
1633 }
1634
1635 void tegra_dc_sor_pre_detach(struct tegra_dc_sor_data *sor)
1636 {
1637         struct tegra_dc *dc = sor->dc;
1638
1639         if (sor->sor_state != SOR_ATTACHED)
1640                 return;
1641
1642         tegra_dc_get(dc);
1643
1644 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
1645         /* Sleep mode */
1646         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1647                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1648                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1649                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1650         tegra_dc_sor_super_update(sor);
1651 #else
1652         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1653                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1654                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1655                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1656         tegra_dc_sor_super_update(sor);
1657
1658         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1659                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1660                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1661                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1662         tegra_dc_sor_super_update(sor);
1663 #endif
1664
1665         tegra_dc_sor_disable_win_short_raster(dc, sor->dc_reg_ctx);
1666
1667         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1668                 NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
1669                 NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP,
1670                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1671                 dev_err(&dc->ndev->dev,
1672                         "dc timeout waiting for OPMOD = SLEEP\n");
1673         }
1674
1675         sor->sor_state = SOR_DETACHING;
1676         tegra_dc_put(dc);
1677 }
1678
1679 void tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
1680 {
1681         struct tegra_dc *dc = sor->dc;
1682         unsigned long dc_int_mask;
1683
1684         if (sor->sor_state == SOR_DETACHED)
1685                 return;
1686
1687         tegra_dc_get(dc);
1688
1689         /* Mask DC interrupts during the 2 dummy frames required for detach */
1690         dc_int_mask = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1691         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1692
1693         if (sor->sor_state != SOR_DETACHING)
1694                 tegra_dc_sor_pre_detach(sor);
1695
1696         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1697                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1698                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1699                 NV_SOR_SUPER_STATE1_ATTACHED_NO);
1700         tegra_dc_sor_super_update(sor);
1701
1702         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1703                 NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
1704                 NV_SOR_TEST_ATTACHED_FALSE,
1705                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1706                 dev_err(&dc->ndev->dev,
1707                         "dc timeout waiting for ATTACH = FALSE\n");
1708         }
1709
1710         tegra_sor_writel(sor, NV_SOR_STATE1,
1711                 NV_SOR_STATE1_ASY_OWNER_NONE |
1712                 NV_SOR_STATE1_ASY_SUBOWNER_NONE |
1713                 NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM);
1714         tegra_dc_sor_update(sor);
1715
1716         tegra_sor_stop_dc(sor);
1717
1718         tegra_dc_sor_restore_win_and_raster(dc, sor->dc_reg_ctx);
1719
1720         tegra_dc_writel(dc, dc_int_mask, DC_CMD_INT_MASK);
1721         sor->sor_state = SOR_DETACHED;
1722         tegra_dc_put(dc);
1723 }
1724
1725 static void tegra_sor_config_lvds_clk(struct tegra_dc_sor_data *sor)
1726 {
1727         int flag = tegra_is_clk_enabled(sor->sor_clk);
1728
1729         if (sor->clk_type == TEGRA_SOR_MACRO_CLK)
1730                 return;
1731
1732         tegra_sor_writel(sor, NV_SOR_CLK_CNTRL,
1733                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK |
1734                 NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS);
1735
1736         tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
1737
1738         /*
1739          * HW bug 1425607
1740          * Disable clocks to avoid glitch when switching
1741          * between safe clock and macro pll clock
1742          */
1743         if (flag)
1744                 clk_disable_unprepare(sor->sor_clk);
1745
1746         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 1);
1747
1748         if (flag)
1749                 clk_prepare_enable(sor->sor_clk);
1750
1751         sor->clk_type = TEGRA_SOR_MACRO_CLK;
1752 }
1753 void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
1754         bool balanced, bool conforming)
1755 {
1756         u32 reg_val;
1757
1758         tegra_dc_sor_enable_dc(sor);
1759         tegra_dc_sor_config_panel(sor, true);
1760         tegra_dc_writel(sor->dc, 0x9f00, DC_CMD_STATE_CONTROL);
1761         tegra_dc_writel(sor->dc, 0x9f, DC_CMD_STATE_CONTROL);
1762
1763         tegra_dc_writel(sor->dc, SOR_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1764
1765         tegra_sor_write_field(sor, NV_SOR_PLL3,
1766                 NV_SOR_PLL3_PLLVDD_MODE_MASK,
1767                 NV_SOR_PLL3_PLLVDD_MODE_V1_8);
1768
1769         tegra_sor_writel(sor, NV_SOR_PLL1,
1770                          (NV_SOR_PLL1_TMDS_TERMADJ_OHM500 |
1771                           (2 << NV_SOR_PLL1_LVDSCM_SHIFT) |
1772                           (2 << NV_SOR_PLL1_LOADADJ_SHIFT)));
1773         tegra_sor_write_field(sor, NV_SOR_PLL2,
1774                 NV_SOR_PLL2_AUX1_SEQ_MASK |
1775                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1776                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
1777                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
1778
1779
1780         reg_val = NV_SOR_LVDS_LINKACTB_DISABLE |
1781                 NV_SOR_LVDS_LINKACTA_ENABLE |
1782                 NV_SOR_LVDS_UPPER_TRUE |
1783                 NV_SOR_LVDS_PD_TXCB_DISABLE |
1784                 NV_SOR_LVDS_PD_TXDB_3_DISABLE |
1785                 NV_SOR_LVDS_PD_TXDB_2_DISABLE |
1786                 NV_SOR_LVDS_PD_TXDB_1_DISABLE |
1787                 NV_SOR_LVDS_PD_TXDB_0_DISABLE |
1788                 NV_SOR_LVDS_PD_TXDA_2_ENABLE |
1789                 NV_SOR_LVDS_PD_TXDA_1_ENABLE |
1790                 NV_SOR_LVDS_PD_TXDA_0_ENABLE;
1791         if (!conforming && (sor->dc->pdata->default_out->depth == 18))
1792                 reg_val |= (NV_SOR_LVDS_PD_TXDA_3_DISABLE);
1793
1794         tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
1795         tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
1796                 (NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 |
1797                  NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 |
1798                  NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 |
1799                  NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0));
1800         reg_val = tegra_sor_readl(sor,
1801                                   NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum));
1802         reg_val &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK;
1803         tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum),
1804                  reg_val | NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0);
1805
1806         tegra_sor_writel(sor, NV_SOR_LANE_PREEMPHASIS(sor->portnum),
1807                          (NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL4 |
1808                           NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL4 |
1809                           NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL4 |
1810                           NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL4));
1811         reg_val = tegra_sor_readl(sor,
1812                  NV_SOR_LANE4_PREEMPHASIS(sor->portnum));
1813         reg_val &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK;
1814         tegra_sor_writel(sor, NV_SOR_LANE4_PREEMPHASIS(sor->portnum),
1815                          reg_val | NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL4);
1816
1817 #if 0
1818         tegra_sor_write_field(sor, NV_SOR_LVDS,
1819                 NV_SOR_LVDS_BALANCED_DEFAULT_MASK,
1820                 balanced ? NV_SOR_LVDS_BALANCED_ENABLE :
1821                 NV_SOR_LVDS_BALANCED_DISABLE);
1822         tegra_sor_write_field(sor, NV_SOR_LVDS,
1823                 NV_SOR_LVDS_ROTDAT_DEFAULT_MASK,
1824                 conforming ? 6 << NV_SOR_LVDS_ROTDAT_SHIFT :
1825                 0 << NV_SOR_LVDS_ROTDAT_SHIFT);
1826 #endif
1827
1828         tegra_sor_pad_power_up(sor, true);
1829
1830         tegra_sor_writel(sor, NV_SOR_SEQ_INST(0),
1831                 NV_SOR_SEQ_INST_LANE_SEQ_RUN |
1832                 NV_SOR_SEQ_INST_HALT_TRUE);
1833         tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum),
1834                 NV_SOR_DP_SPARE_SEQ_ENABLE_YES |
1835                 NV_SOR_DP_SPARE_PANEL_INTERNAL |
1836                 NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK);
1837
1838         tegra_dc_sor_enable_lane_sequencer(sor, true, true);
1839
1840         tegra_sor_config_lvds_clk(sor);
1841
1842         tegra_dc_sor_attach_lvds(sor);
1843
1844         if ((tegra_dc_sor_set_power_state(sor, 1))) {
1845                 dev_err(&sor->dc->ndev->dev,
1846                         "Failed to power up SOR sequencer for LVDS\n");
1847                 return;
1848         }
1849
1850         if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
1851                         NV_SOR_PWR_MODE_DEFAULT_MASK,
1852                         NV_SOR_PWR_MODE_NORMAL,
1853                         100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1854                 dev_err(&sor->dc->ndev->dev,
1855                         "dc timeout waiting for ATTACHED = TRUE\n");
1856                 return;
1857         }
1858 }
1859
1860 void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds)
1861 {
1862         struct tegra_dc *dc = sor->dc;
1863
1864         tegra_sor_config_safe_clk(sor);
1865
1866         tegra_dc_sor_power_down(sor);
1867
1868         /* Power down DP lanes */
1869         if (!is_lvds && tegra_sor_power_lanes(sor, 4, false)) {
1870                 dev_err(&dc->ndev->dev,
1871                         "Failed to power down dp lanes\n");
1872                 return;
1873         }
1874
1875         if (tegra_platform_is_linsim())
1876                 return;
1877
1878         tegra_sor_clk_disable(sor);
1879         /* Reset SOR clk */
1880         tegra_periph_reset_assert(sor->sor_clk);
1881 }
1882
1883 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, bool is_int)
1884 {
1885         u32 reg_val;
1886
1887         reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum));
1888         if (is_int)
1889                 reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL;
1890         else
1891                 reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL;
1892
1893         reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
1894                 NV_SOR_DP_SPARE_SEQ_ENABLE_YES;
1895
1896         tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val);
1897
1898         if (sor->dc->out->type == TEGRA_DC_OUT_HDMI)
1899                 tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
1900                                 NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_ENABLE,
1901                                 NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_ENABLE);
1902 }
1903
1904 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
1905                                    u8 *lane_count)
1906 {
1907         u32 reg_val;
1908
1909         reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
1910         *link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK)
1911                 >> NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT;
1912         reg_val = tegra_sor_readl(sor,
1913                 NV_SOR_DP_LINKCTL(sor->portnum));
1914
1915         switch (reg_val & NV_SOR_DP_LINKCTL_LANECOUNT_MASK) {
1916         case NV_SOR_DP_LINKCTL_LANECOUNT_ZERO:
1917                 *lane_count = 0;
1918                 break;
1919         case NV_SOR_DP_LINKCTL_LANECOUNT_ONE:
1920                 *lane_count = 1;
1921                 break;
1922         case NV_SOR_DP_LINKCTL_LANECOUNT_TWO:
1923                 *lane_count = 2;
1924                 break;
1925         case NV_SOR_DP_LINKCTL_LANECOUNT_FOUR:
1926                 *lane_count = 4;
1927                 break;
1928         default:
1929                 dev_err(&sor->dc->ndev->dev, "Unknown lane count\n");
1930         }
1931 }
1932
1933 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
1934 {
1935         WARN_ON(sor->sor_state == SOR_ATTACHED);
1936
1937         tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
1938                 NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,
1939                 link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
1940
1941         /* It can take upto 200us for PLLs in analog macro to settle */
1942         udelay(300);
1943 }
1944
1945 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
1946 {
1947         u32 reg_lane_cnt = 0;
1948
1949         switch (lane_count) {
1950         case 0:
1951                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_ZERO;
1952                 break;
1953         case 1:
1954                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_ONE;
1955                 break;
1956         case 2:
1957                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_TWO;
1958                 break;
1959         case 4:
1960                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_FOUR;
1961                 break;
1962         default:
1963                 /* 0 should be handled earlier. */
1964                 dev_err(&sor->dc->ndev->dev, "dp: Invalid lane count %d\n",
1965                         lane_count);
1966                 return;
1967         }
1968
1969         tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
1970                                 NV_SOR_DP_LINKCTL_LANECOUNT_MASK,
1971                                 reg_lane_cnt);
1972 }
1973
1974 void tegra_sor_setup_clk(struct tegra_dc_sor_data *sor, struct clk *clk,
1975         bool is_lvds)
1976 {
1977         struct clk *dc_parent_clk;
1978         struct tegra_dc *dc = sor->dc;
1979
1980         if (tegra_platform_is_linsim())
1981                 return;
1982         if (clk == dc->clk) {
1983                 dc_parent_clk = clk_get_parent(clk);
1984                 BUG_ON(!dc_parent_clk);
1985
1986                 if (dc->mode.pclk != clk_get_rate(dc_parent_clk))
1987                         clk_set_rate(dc_parent_clk, dc->mode.pclk);
1988         }
1989 }
1990
1991 void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor)
1992 {
1993         const struct tegra_dc_dp_link_config *cfg = sor->link_cfg;
1994         u32 val = 0;
1995
1996         switch (cfg->lane_count) {
1997         /* T210 boards need to swap lanes 0 and 2 */
1998         case 4:
1999                 val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
2000 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_TEGRA_NVDISPLAY)
2001                         NV_SOR_DP_PADCTL_PD_TXD_0_NO);
2002 #else
2003                         NV_SOR_DP_PADCTL_PD_TXD_2_NO);
2004 #endif
2005                 /* fall through */
2006         case 2:
2007                 val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
2008         case 1:
2009 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_TEGRA_NVDISPLAY)
2010                 val |= NV_SOR_DP_PADCTL_PD_TXD_2_NO;
2011 #else
2012                 val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
2013 #endif
2014                 break;
2015         default:
2016                 dev_dbg(&sor->dc->ndev->dev,
2017                         "dp: invalid lane number %d\n", cfg->lane_count);
2018                 return;
2019         }
2020
2021         /* force lanes to output common mode voltage */
2022         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
2023                 (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
2024                 (val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
2025
2026         /* precharge for atleast 10us */
2027         usleep_range(20, 100);
2028
2029         /* fallback to normal operation */
2030         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
2031                 (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0);
2032 }
2033
2034 void tegra_dc_sor_modeset_notifier(struct tegra_dc_sor_data *sor, bool is_lvds)
2035 {
2036         if (!sor->clk_type)
2037                 tegra_sor_config_safe_clk(sor);
2038
2039         tegra_sor_clk_enable(sor);
2040
2041         tegra_dc_sor_config_panel(sor, is_lvds);
2042         tegra_dc_sor_update(sor);
2043         tegra_dc_sor_super_update(sor);
2044
2045         tegra_sor_clk_disable(sor);
2046 }
2047