2 * drivers/video/tegra/dc/dc_priv.h
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_H
21 #define __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_H
23 #include "dc_priv_defs.h"
24 #ifndef CREATE_TRACE_POINTS
25 # include <trace/events/display.h>
26 #define WIN_IS_BLOCKLINEAR(win) ((win)->flags & TEGRA_WIN_FLAG_BLOCKLINEAR)
28 #include <linux/tegra-powergate.h>
29 #include <video/tegra_dc_ext.h>
32 #define WIN_IS_TILED(win) ((win)->flags & TEGRA_WIN_FLAG_TILED)
33 #define WIN_IS_ENABLED(win) ((win)->flags & TEGRA_WIN_FLAG_ENABLED)
34 #define WIN_IS_FB(win) ((win)->flags & TEGRA_WIN_FLAG_FB)
36 #define WIN_IS_INTERLACE(win) ((win)->flags & TEGRA_WIN_FLAG_INTERLACE)
38 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
39 #define WIN_ALL_ACT_REQ (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | \
40 WIN_D_ACT_REQ | WIN_H_ACT_REQ)
42 #define WIN_ALL_ACT_REQ (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ)
46 * Second definition is needed to prevent inadvertent sanity failures
49 #ifndef CONFIG_ARCH_TEGRA_VCM30T124
50 #define tegra_dc_hotplug_supported(dc) (dc && dc->out ? \
51 (dc->out->hotplug_gpio >= 0 && \
52 !(dc->out->type == TEGRA_DC_OUT_DP && \
53 !tegra_dc_is_ext_dp_panel(dc))) : 0)
55 #define tegra_dc_hotplug_supported(dc) (dc && dc->out ? \
56 (dc->out->hotplug_gpio >= 0 || \
57 dc->out->type == TEGRA_DC_OUT_DP) : 0)
60 static inline int tegra_dc_io_start(struct tegra_dc *dc)
63 ret = nvhost_module_busy_ext(dc->ndev);
65 dev_warn(&dc->ndev->dev,
66 "Host1x powerup failed with err=%d\n", ret);
71 static inline void tegra_dc_io_end(struct tegra_dc *dc)
73 nvhost_module_idle_ext(dc->ndev);
76 static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
81 if (likely(tegra_platform_is_silicon())) {
82 BUG_ON(!nvhost_module_powered_ext(dc->ndev));
83 if (WARN(!tegra_is_clk_enabled(dc->clk),
84 "DC is clock-gated.\n") ||
85 WARN(!tegra_powergate_is_powered(
86 dc->powergate_id), "DC is power-gated.\n"))
90 ret = readl(dc->base + reg * 4);
91 trace_display_readl(dc, ret, dc->base + reg * 4);
95 static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long val,
98 if (likely(tegra_platform_is_silicon())) {
99 BUG_ON(!nvhost_module_powered_ext(dc->ndev));
100 if (WARN(!tegra_is_clk_enabled(dc->clk),
101 "DC is clock-gated.\n") ||
102 WARN(!tegra_powergate_is_powered(
103 dc->powergate_id), "DC is power-gated.\n"))
107 trace_display_writel(dc, val, dc->base + reg * 4);
108 writel(val, dc->base + reg * 4);
111 static inline void tegra_dc_power_on(struct tegra_dc *dc)
113 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
114 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
115 DC_CMD_DISPLAY_POWER_CONTROL);
118 static inline void _tegra_dc_write_table(struct tegra_dc *dc, const u32 *table,
123 for (i = 0; i < len; i++)
124 tegra_dc_writel(dc, table[i * 2 + 1], table[i * 2]);
127 #define tegra_dc_write_table(dc, table) \
128 _tegra_dc_write_table(dc, table, ARRAY_SIZE(table) / 2)
130 static inline void tegra_dc_set_outdata(struct tegra_dc *dc, void *data)
135 static inline void *tegra_dc_get_outdata(struct tegra_dc *dc)
140 static inline unsigned long tegra_dc_get_default_emc_clk_rate(
143 return dc->pdata->emc_clk_rate ? dc->pdata->emc_clk_rate : ULONG_MAX;
146 /* return the color format field */
147 static inline int tegra_dc_fmt(int fmt)
149 return (fmt & TEGRA_DC_EXT_FMT_MASK) >> TEGRA_DC_EXT_FMT_SHIFT;
152 /* return the byte swap field */
153 static inline int tegra_dc_fmt_byteorder(int fmt)
155 return (fmt & TEGRA_DC_EXT_FMT_BYTEORDER_MASK) >>
156 TEGRA_DC_EXT_FMT_BYTEORDER_SHIFT;
159 static inline int tegra_dc_fmt_bpp(int fmt)
161 switch (tegra_dc_fmt(fmt)) {
162 case TEGRA_WIN_FMT_P1:
165 case TEGRA_WIN_FMT_P2:
168 case TEGRA_WIN_FMT_P4:
171 case TEGRA_WIN_FMT_P8:
174 case TEGRA_WIN_FMT_B4G4R4A4:
175 case TEGRA_WIN_FMT_B5G5R5A:
176 case TEGRA_WIN_FMT_B5G6R5:
177 case TEGRA_WIN_FMT_R5G6B5:
178 case TEGRA_WIN_FMT_AB5G5R5:
179 case TEGRA_WIN_FMT_T_R4G4B4A4:
182 case TEGRA_WIN_FMT_B8G8R8A8:
183 case TEGRA_WIN_FMT_R8G8B8A8:
184 case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
185 case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
186 case TEGRA_WIN_FMT_T_A2R10G10B10:
187 case TEGRA_WIN_FMT_T_A2B10G10R10:
188 case TEGRA_WIN_FMT_T_X2BL10GL10RL10_XRBIAS:
189 case TEGRA_WIN_FMT_T_X2BL10GL10RL10_XVYCC:
192 /* for planar formats, size of the Y plane, 8bit */
193 case TEGRA_WIN_FMT_YCbCr420P:
194 case TEGRA_WIN_FMT_YUV420P:
195 case TEGRA_WIN_FMT_YCbCr422P:
196 case TEGRA_WIN_FMT_YUV422P:
197 case TEGRA_WIN_FMT_YCbCr422R:
198 case TEGRA_WIN_FMT_YUV422R:
199 case TEGRA_WIN_FMT_YCbCr422RA:
200 case TEGRA_WIN_FMT_YUV422RA:
201 case TEGRA_WIN_FMT_YCbCr444P:
202 case TEGRA_WIN_FMT_YUV444P:
203 case TEGRA_WIN_FMT_YUV422SP:
204 case TEGRA_WIN_FMT_YUV420SP:
205 case TEGRA_WIN_FMT_YCbCr420SP:
206 case TEGRA_WIN_FMT_YCbCr422SP:
207 case TEGRA_WIN_FMT_T_Y10___U10___V10_N420:
208 case TEGRA_WIN_FMT_T_Y10___U10___V10_N444:
209 case TEGRA_WIN_FMT_T_Y10___V10U10_N420:
210 case TEGRA_WIN_FMT_T_Y10___U10V10_N422:
211 case TEGRA_WIN_FMT_T_Y10___U10V10_N422R:
212 case TEGRA_WIN_FMT_T_Y10___U10V10_N444:
213 case TEGRA_WIN_FMT_T_Y12___U12___V12_N420:
214 case TEGRA_WIN_FMT_T_Y12___U12___V12_N444:
215 case TEGRA_WIN_FMT_T_Y12___V12U12_N420:
216 case TEGRA_WIN_FMT_T_Y12___U12V12_N422:
217 case TEGRA_WIN_FMT_T_Y12___U12V12_N422R:
218 case TEGRA_WIN_FMT_T_Y12___U12V12_N444:
221 /* YUV packed into 32-bits */
222 case TEGRA_WIN_FMT_YCbCr422:
223 case TEGRA_WIN_FMT_YUV422:
226 /* RGB with 64-bits size */
227 case TEGRA_WIN_FMT_T_R16_G16_B16_A16:
234 static inline bool tegra_dc_is_yuv(int fmt)
236 switch (tegra_dc_fmt(fmt)) {
237 case TEGRA_WIN_FMT_YUV420P:
238 case TEGRA_WIN_FMT_YCbCr420P:
239 case TEGRA_WIN_FMT_YCbCr422P:
240 case TEGRA_WIN_FMT_YUV422P:
241 case TEGRA_WIN_FMT_YCbCr422:
242 case TEGRA_WIN_FMT_YUV422:
243 case TEGRA_WIN_FMT_YCbCr422R:
244 case TEGRA_WIN_FMT_YUV422R:
245 case TEGRA_WIN_FMT_YCbCr422RA:
246 case TEGRA_WIN_FMT_YUV422RA:
247 case TEGRA_WIN_FMT_YCbCr444P:
248 case TEGRA_WIN_FMT_YUV444P:
249 case TEGRA_WIN_FMT_YUV422SP:
250 case TEGRA_WIN_FMT_YCbCr422SP:
251 case TEGRA_WIN_FMT_YCbCr420SP:
252 case TEGRA_WIN_FMT_YUV420SP:
254 case TEGRA_WIN_FMT_T_Y10___U10___V10_N420:
255 case TEGRA_WIN_FMT_T_Y10___U10___V10_N444:
256 case TEGRA_WIN_FMT_T_Y10___V10U10_N420:
257 case TEGRA_WIN_FMT_T_Y10___U10V10_N422:
258 case TEGRA_WIN_FMT_T_Y10___U10V10_N422R:
259 case TEGRA_WIN_FMT_T_Y10___U10V10_N444:
260 case TEGRA_WIN_FMT_T_Y12___U12___V12_N420:
261 case TEGRA_WIN_FMT_T_Y12___U12___V12_N444:
262 case TEGRA_WIN_FMT_T_Y12___V12U12_N420:
263 case TEGRA_WIN_FMT_T_Y12___U12V12_N422:
264 case TEGRA_WIN_FMT_T_Y12___U12V12_N422R:
265 case TEGRA_WIN_FMT_T_Y12___U12V12_N444:
272 static inline bool tegra_dc_is_yuv_planar(int fmt)
274 switch (tegra_dc_fmt(fmt)) {
275 case TEGRA_WIN_FMT_YUV420P:
276 case TEGRA_WIN_FMT_YCbCr420P:
277 case TEGRA_WIN_FMT_YCbCr422P:
278 case TEGRA_WIN_FMT_YUV422P:
279 case TEGRA_WIN_FMT_YCbCr422R:
280 case TEGRA_WIN_FMT_YUV422R:
281 case TEGRA_WIN_FMT_YCbCr422RA:
282 case TEGRA_WIN_FMT_YUV422RA:
283 case TEGRA_WIN_FMT_YCbCr444P:
284 case TEGRA_WIN_FMT_YUV444P:
285 case TEGRA_WIN_FMT_T_Y10___U10___V10_N420:
286 case TEGRA_WIN_FMT_T_Y10___U10___V10_N444:
287 case TEGRA_WIN_FMT_T_Y10___V10U10_N420:
288 case TEGRA_WIN_FMT_T_Y10___U10V10_N422:
289 case TEGRA_WIN_FMT_T_Y10___U10V10_N422R:
290 case TEGRA_WIN_FMT_T_Y10___U10V10_N444:
291 case TEGRA_WIN_FMT_T_Y12___U12___V12_N420:
292 case TEGRA_WIN_FMT_T_Y12___U12___V12_N444:
293 case TEGRA_WIN_FMT_T_Y12___V12U12_N420:
294 case TEGRA_WIN_FMT_T_Y12___U12V12_N422:
295 case TEGRA_WIN_FMT_T_Y12___U12V12_N422R:
296 case TEGRA_WIN_FMT_T_Y12___U12V12_N444:
302 static inline bool tegra_dc_is_yuv_full_planar(int fmt)
305 case TEGRA_WIN_FMT_YCbCr444P:
306 case TEGRA_WIN_FMT_YUV444P:
307 case TEGRA_WIN_FMT_T_Y10___U10___V10_N420:
308 case TEGRA_WIN_FMT_T_Y10___U10___V10_N444:
309 case TEGRA_WIN_FMT_T_Y12___U12___V12_N420:
310 case TEGRA_WIN_FMT_T_Y12___U12___V12_N444:
316 static inline bool tegra_dc_is_yuv_semi_planar(int fmt)
319 case TEGRA_WIN_FMT_YUV420SP:
320 case TEGRA_WIN_FMT_YCbCr420SP:
321 case TEGRA_WIN_FMT_YCbCr422SP:
322 case TEGRA_WIN_FMT_YUV422SP:
323 case TEGRA_WIN_FMT_T_Y10___V10U10_N420:
324 case TEGRA_WIN_FMT_T_Y10___U10V10_N422:
325 case TEGRA_WIN_FMT_T_Y10___U10V10_N422R:
326 case TEGRA_WIN_FMT_T_Y10___U10V10_N444:
327 case TEGRA_WIN_FMT_T_Y12___V12U12_N420:
328 case TEGRA_WIN_FMT_T_Y12___U12V12_N422:
329 case TEGRA_WIN_FMT_T_Y12___U12V12_N422R:
330 case TEGRA_WIN_FMT_T_Y12___U12V12_N444:
336 static inline u32 tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
340 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
341 tegra_dc_writel(dc, val | int_val, DC_CMD_INT_MASK);
345 static inline u32 tegra_dc_flush_interrupt(struct tegra_dc *dc, u32 val)
349 local_irq_save(flag);
351 tegra_dc_writel(dc, val, DC_CMD_INT_STATUS);
353 local_irq_restore(flag);
358 static inline u32 tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
362 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
363 tegra_dc_writel(dc, val & ~int_val, DC_CMD_INT_MASK);
367 static inline void tegra_dc_restore_interrupt(struct tegra_dc *dc, u32 val)
369 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
372 static inline unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
374 if (!tegra_platform_is_silicon())
375 return dc->mode.pclk;
377 return clk_get_rate(dc->clk);
380 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
381 static inline void tegra_dc_powergate_locked(struct tegra_dc *dc)
383 tegra_powergate_partition(dc->powergate_id);
386 static inline void tegra_dc_unpowergate_locked(struct tegra_dc *dc)
389 ret = tegra_unpowergate_partition(dc->powergate_id);
391 dev_err(&dc->ndev->dev, "%s: could not unpowergate %d\n",
395 static inline bool tegra_dc_is_powered(struct tegra_dc *dc)
397 return tegra_powergate_is_powered(dc->powergate_id);
400 static inline void tegra_dc_set_edid(struct tegra_dc *dc,
401 struct tegra_edid *edid)
406 void tegra_dc_powergate_locked(struct tegra_dc *dc);
407 void tegra_dc_unpowergate_locked(struct tegra_dc *dc);
409 static inline void tegra_dc_powergate_locked(struct tegra_dc *dc) { }
410 static inline void tegra_dc_unpowergate_locked(struct tegra_dc *dc) { }
411 static inline bool tegra_dc_is_powered(struct tegra_dc *dc)
417 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
418 static inline u32 tegra_dc_reg_l32(dma_addr_t v)
420 return v & 0xffffffff;
423 static inline u32 tegra_dc_reg_h32(dma_addr_t v)
428 static inline u32 tegra_dc_reg_l32(dma_addr_t v)
433 static inline u32 tegra_dc_reg_h32(dma_addr_t v)
438 extern struct tegra_dc_out_ops tegra_dc_rgb_ops;
439 extern struct tegra_dc_out_ops tegra_dc_dsi_ops;
441 #if defined(CONFIG_TEGRA_HDMI2_0)
442 extern struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops;
443 #elif defined(CONFIG_TEGRA_HDMI)
444 extern struct tegra_dc_out_ops tegra_dc_hdmi_ops;
447 #ifdef CONFIG_TEGRA_DP
448 extern struct tegra_dc_out_ops tegra_dc_dp_ops;
450 #ifdef CONFIG_TEGRA_LVDS
451 extern struct tegra_dc_out_ops tegra_dc_lvds_ops;
453 #ifdef CONFIG_TEGRA_NVSR
454 extern struct tegra_dc_out_ops tegra_dc_nvsr_ops;
457 extern struct tegra_dc_out_ops tegra_dc_null_ops;
459 /* defined in dc_sysfs.c, used by dc.c */
460 void tegra_dc_remove_sysfs(struct device *dev);
461 void tegra_dc_create_sysfs(struct device *dev);
463 /* defined in dc.c, used by dc_sysfs.c */
464 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable);
465 bool tegra_dc_stats_get(struct tegra_dc *dc);
467 /* defined in dc.c, used by dc_sysfs.c */
468 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc);
469 void tegra_dc_enable_crc(struct tegra_dc *dc);
470 void tegra_dc_disable_crc(struct tegra_dc *dc);
472 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
473 const struct tegra_dc_out_pin *pins,
474 const unsigned int n_pins);
475 /* defined in dc.c, used in bandwidth.c and ext/dev.c */
476 unsigned int tegra_dc_has_multiple_dc(void);
478 /* defined in dc.c, used in hdmihdcp.c */
479 int tegra_dc_ddc_enable(struct tegra_dc *dc, bool enabled);
481 /* defined in dc.c, used in dsi.c */
482 void tegra_dc_clk_enable(struct tegra_dc *dc);
483 void tegra_dc_clk_disable(struct tegra_dc *dc);
485 /* defined in dc.c, used in nvsd.c and dsi.c */
486 void tegra_dc_get(struct tegra_dc *dc);
487 void tegra_dc_put(struct tegra_dc *dc);
489 /* defined in dc.c, used in tegra_adf.c */
490 void tegra_dc_hold_dc_out(struct tegra_dc *dc);
491 void tegra_dc_release_dc_out(struct tegra_dc *dc);
493 /* defined in dc.c, used in ext/dev.c */
494 void tegra_dc_call_flip_callback(void);
496 /* defined in dc.c, used in sor.c */
497 unsigned long tegra_dc_poll_register(struct tegra_dc *dc,
498 u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us,
500 void tegra_dc_enable_general_act(struct tegra_dc *dc);
502 /* defined in dc.c, used by ext/dev.c */
505 /* defined in dc.c, used in ext/dev.c */
506 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable);
508 /* defined in dc.c, used in dsi.c */
509 int _tegra_dc_wait_for_frame_end(struct tegra_dc *dc,
512 /* defined in bandwidth.c, used in dc.c */
513 void tegra_dc_clear_bandwidth(struct tegra_dc *dc);
514 void tegra_dc_program_bandwidth(struct tegra_dc *dc, bool use_new);
515 int tegra_dc_set_dynamic_emc(struct tegra_dc *dc);
516 #ifdef CONFIG_TEGRA_ISOMGR
517 int tegra_dc_bandwidth_negotiate_bw(struct tegra_dc *dc,
518 struct tegra_dc_win *windows[], int n);
519 void tegra_dc_bandwidth_renegotiate(void *p, u32 avail_bw);
521 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n);
522 long tegra_dc_calc_min_bandwidth(struct tegra_dc *dc);
524 /* defined in mode.c, used in dc.c, window.c and hdmi2.0.c */
525 int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode);
526 int tegra_dc_calc_refresh(const struct tegra_dc_mode *m);
527 int tegra_dc_calc_fb_refresh(const struct fb_videomode *fbmode);
528 int tegra_dc_update_mode(struct tegra_dc *dc);
529 u32 tegra_dc_get_aspect_ratio(struct tegra_dc *dc);
531 /* defined in clock.c, used in dc.c, rgb.c, dsi.c and hdmi.c */
532 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk);
533 unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk);
534 unsigned long tegra_dc_pclk_predict_rate(
535 int out_type, struct clk *parent, int pclk);
537 /* defined in lut.c, used in dc.c */
538 void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut);
539 void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win *win);
541 /* defined in csc.c, used in dc.c */
542 void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc);
543 void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc);
545 /* defined in window.c, used in dc.c */
546 void tegra_dc_trigger_windows(struct tegra_dc *dc);
548 void tegra_dc_set_color_control(struct tegra_dc *dc);
549 #ifdef CONFIG_TEGRA_DC_CMU
550 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable);
551 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu);
552 int tegra_dc_update_cmu_aligned(struct tegra_dc *dc, struct tegra_dc_cmu *cmu);
555 struct device_node *tegra_get_panel_node_out_type_check
556 (struct tegra_dc *dc, u32 out_type);
558 struct tegra_dc_platform_data
559 *of_dc_parse_platform_data(struct platform_device *ndev);
561 /* defined in dc.c, used in dc.c and dev.c */
562 void tegra_dc_set_act_vfp(struct tegra_dc *dc, int vfp);
564 /* defined in dc.c, used in dc.c and window.c */
565 bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask);
566 int tegra_dc_get_v_count(struct tegra_dc *dc);
568 /* defined in dc.c, used in vrr.c */
569 s32 tegra_dc_calc_v_front_porch(struct tegra_dc_mode *mode,
572 /* defined in cursor.c, used in dc.c and ext/cursor.c */
573 int tegra_dc_cursor_image(struct tegra_dc *dc,
574 enum tegra_dc_cursor_format format, enum tegra_dc_cursor_size size,
575 u32 fg, u32 bg, dma_addr_t phys_addr);
576 int tegra_dc_cursor_set(struct tegra_dc *dc, bool enable, int x, int y);
577 int tegra_dc_cursor_clip(struct tegra_dc *dc, unsigned clip);
578 int tegra_dc_cursor_suspend(struct tegra_dc *dc);
579 int tegra_dc_cursor_resume(struct tegra_dc *dc);
580 void tegra_dc_win_partial_update(struct tegra_dc *dc, struct tegra_dc_win *win,
581 unsigned int xoff, unsigned int yoff, unsigned int width,
582 unsigned int height);
583 int tegra_dc_slgc_disp0(struct notifier_block *nb, unsigned long unused0,
586 #ifdef CONFIG_TEGRA_NVDISPLAY
587 int tegra_nvdisp_init(struct tegra_dc *dc);
588 int tegra_nvdisp_update_windows(struct tegra_dc *dc,
589 struct tegra_dc_win *windows[], int n,
590 u16 *dirty_rect, bool wait_for_vblank);
591 int tegra_nvdisp_head_enable(struct tegra_dc *dc);
592 int tegra_nvdisp_head_disable(struct tegra_dc *dc);
593 int tegra_nvdisp_get_linestride(struct tegra_dc *dc, int win);
594 void tegra_nvdisp_enable_crc(struct tegra_dc *dc);
595 void tegra_nvdisp_disable_crc(struct tegra_dc *dc);
596 u32 tegra_nvdisp_read_rg_crc(struct tegra_dc *dc);
597 int tegra_nvdisp_program_mode(struct tegra_dc *dc,
598 struct tegra_dc_mode *mode);
600 struct tegra_fb_info *tegra_nvdisp_fb_register(struct platform_device *ndev,
601 struct tegra_dc *dc, struct tegra_fb_data *fb_data,
602 struct resource *fb_mem);
604 void nvdisp_dc_feature_register(struct tegra_dc *dc);
605 int nvdisp_set_cursor_position(struct tegra_dc *dc, s16 x, s16 y);