arch/arm/mach-tegra/board-panel.c

   1 /*
   2  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of.h>
  20 #include <linux/delay.h>
  21 #include <linux/gpio.h>
  22 #include <linux/clk.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/export.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28
  29 #include <mach/dc.h>
  30
  31 #include "board-panel.h"
  32 #include "board.h"
  33 #include "iomap.h"
  34 #include <linux/platform/tegra/dvfs.h>
  35 #include <linux/platform_data/lp855x.h>
  36
  37 #define PRISM_THRESHOLD         50
  38 #define HYST_VAL                25
  39
  40 atomic_t sd_brightness = ATOMIC_INIT(255);
  41 EXPORT_SYMBOL(sd_brightness);
  42
  43 struct tegra_panel_ops *fixed_primary_panel_ops;
  44 struct tegra_panel_ops *fixed_secondary_panel_ops;
  45 const char *fixed_primary_panel_compatible;
  46 const char *fixed_secondary_panel_compatible;
  47 struct pwm_bl_data_dt_ops *fixed_pwm_bl_ops;
  48
  49 void tegra_dsi_resources_init(u8 dsi_instance,
  50                         struct resource *resources, int n_resources)
  51 {
  52         int i;
  53         for (i = 0; i < n_resources; i++) {
  54                 struct resource *r = &resources[i];
  55                 if (resource_type(r) == IORESOURCE_MEM &&
  56                         !strcmp(r->name, "dsi_regs")) {
  57                         switch (dsi_instance) {
  58                         case DSI_INSTANCE_0:
  59                                 r->start = TEGRA_DSI_BASE;
  60                                 r->end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1;
  61                                 break;
  62                         case DSI_INSTANCE_1:
  63                         default:
  64                                 r->start = TEGRA_DSIB_BASE;
  65                                 r->end = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1;
  66                                 break;
  67                         }
  68                 }
  69                 if (resource_type(r) == IORESOURCE_MEM &&
  70                         !strcmp(r->name, "ganged_dsia_regs")) {
  71                         r->start = TEGRA_DSI_BASE;
  72                         r->end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1;
  73                 }
  74                 if (resource_type(r) == IORESOURCE_MEM &&
  75                         !strcmp(r->name, "ganged_dsib_regs")) {
  76                         r->start = TEGRA_DSIB_BASE;
  77                         r->end = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1;
  78                 }
  79         }
  80 }
  81
  82 void tegra_dsi_update_init_cmd_gpio_rst(
  83         struct tegra_dc_out *dsi_disp1_out)
  84 {
  85         int i;
  86         for (i = 0; i < dsi_disp1_out->dsi->n_init_cmd; i++) {
  87                 if (dsi_disp1_out->dsi->dsi_init_cmd[i].cmd_type ==
  88                                         TEGRA_DSI_GPIO_SET)
  89                         dsi_disp1_out->dsi->dsi_init_cmd[i].sp_len_dly.gpio
  90                                 = dsi_disp1_out->dsi->dsi_panel_rst_gpio;
  91         }
  92 }
  93
  94 int tegra_panel_reset(struct tegra_panel_of *panel, unsigned int delay_ms)
  95 {
  96         int gpio = panel->panel_gpio[TEGRA_GPIO_RESET];
  97
  98         if (!gpio_is_valid(gpio))
  99                 return -ENOENT;
 100
 101         gpio_direction_output(gpio, 1);
 102         usleep_range(1000, 5000);
 103         gpio_set_value(gpio, 0);
 104         usleep_range(1000, 5000);
 105         gpio_set_value(gpio, 1);
 106         msleep(delay_ms);
 107
 108         return 0;
 109 }
 110
 111
 112 static int tegra_bl_notify(struct device *dev, int brightness)
 113 {
 114         int cur_sd_brightness;
 115
 116         struct lp855x *lp = NULL;
 117         struct platform_device *pdev = NULL;
 118         struct device *dc_dev;
 119         u8 *bl_measured = NULL;
 120         u8 *bl_curve = NULL;
 121
 122         pdev = to_platform_device(bus_find_device_by_name(
 123                 &platform_bus_type, NULL, "tegradc.0"));
 124         dc_dev = &pdev->dev;
 125
 126         if (dc_dev) {
 127                 if (brightness <= PRISM_THRESHOLD)
 128                         nvsd_enbl_dsbl_prism(dc_dev, false);
 129                 else if (brightness > PRISM_THRESHOLD + HYST_VAL)
 130                         nvsd_enbl_dsbl_prism(dc_dev, true);
 131         }
 132
 133         /* Apply any backlight response curve */
 134         if (brightness > 255)
 135                 pr_info("Error: Brightness > 255!\n");
 136         else if (of_device_is_compatible(dev->of_node,
 137                                 "ti,lp8550") ||
 138                 of_device_is_compatible(dev->of_node,
 139                                 "ti,lp8551") ||
 140                 of_device_is_compatible(dev->of_node,
 141                                 "ti,lp8552") ||
 142                 of_device_is_compatible(dev->of_node,
 143                                 "ti,lp8553") ||
 144                 of_device_is_compatible(dev->of_node,
 145                                 "ti,lp8554") ||
 146                 of_device_is_compatible(dev->of_node,
 147                                 "ti,lp8555") ||
 148                 of_device_is_compatible(dev->of_node,
 149                                 "ti,lp8556") ||
 150                 of_device_is_compatible(dev->of_node,
 151                                 "ti,lp8557")) {
 152                 lp = (struct lp855x *)dev_get_drvdata(dev);
 153                 if (lp && lp->pdata) {
 154                         bl_measured = lp->pdata->bl_measured;
 155                         bl_curve = lp->pdata->bl_curve;
 156                 }
 157         }
 158
 159         if (bl_curve)
 160                 brightness = bl_curve[brightness];
 161
 162         cur_sd_brightness = atomic_read(&sd_brightness);
 163         /* SD brightness is a percentage */
 164         brightness = (brightness * cur_sd_brightness) / 255;
 165
 166         if (bl_measured)
 167                 brightness = bl_measured[brightness];
 168
 169         return brightness;
 170 }
 171
 172 static struct generic_bl_data_dt_ops generic_bl_ops = {
 173         .notify = tegra_bl_notify,
 174 };
 175
 176 int tegra_panel_gpio_get_dt(const char *comp_str,
 177                                 struct tegra_panel_of *panel)
 178 {
 179         int cnt = 0;
 180         char *label = NULL;
 181         int err = 0;
 182         struct device_node *node =
 183                 of_find_compatible_node(NULL, NULL, comp_str);
 184
 185         /*
 186          * If gpios are already populated, just return.
 187          */
 188         if (panel->panel_gpio_populated)
 189                 return 0;
 190
 191         if (!node) {
 192                 pr_info("%s panel dt support not available\n", comp_str);
 193                 err = -ENOENT;
 194                 goto fail;
 195         }
 196
 197         panel->panel_gpio[TEGRA_GPIO_RESET] =
 198                 of_get_named_gpio(node, "nvidia,panel-rst-gpio", 0);
 199
 200         panel->panel_gpio[TEGRA_GPIO_PANEL_EN] =
 201                 of_get_named_gpio(node, "nvidia,panel-en-gpio", 0);
 202
 203         panel->panel_gpio[TEGRA_GPIO_BL_ENABLE] =
 204                 of_get_named_gpio(node, "nvidia,panel-bl-en-gpio", 0);
 205
 206         panel->panel_gpio[TEGRA_GPIO_PWM] =
 207                 of_get_named_gpio(node, "nvidia,panel-bl-pwm-gpio", 0);
 208
 209         panel->panel_gpio[TEGRA_GPIO_BRIDGE_EN_0] =
 210                 of_get_named_gpio(node, "nvidia,panel-bridge-en-0-gpio", 0);
 211
 212         panel->panel_gpio[TEGRA_GPIO_BRIDGE_EN_1] =
 213                 of_get_named_gpio(node, "nvidia,panel-bridge-en-1-gpio", 0);
 214
 215         panel->panel_gpio[TEGRA_GPIO_BRIDGE_REFCLK_EN] =
 216                 of_get_named_gpio(node,
 217                         "nvidia,panel-bridge-refclk-en-gpio", 0);
 218
 219         for (cnt = 0; cnt < TEGRA_N_GPIO_PANEL; cnt++) {
 220                 if (gpio_is_valid(panel->panel_gpio[cnt])) {
 221                         switch (cnt) {
 222                         case TEGRA_GPIO_RESET:
 223                                 label = "tegra-panel-reset";
 224                                 break;
 225                         case TEGRA_GPIO_PANEL_EN:
 226                                 label = "tegra-panel-en";
 227                                 break;
 228                         case TEGRA_GPIO_BL_ENABLE:
 229                                 label = "tegra-panel-bl-enable";
 230                                 break;
 231                         case TEGRA_GPIO_PWM:
 232                                 label = "tegra-panel-pwm";
 233                                 break;
 234                         case TEGRA_GPIO_BRIDGE_EN_0:
 235                                 label = "tegra-panel-bridge-en-0";
 236                                 break;
 237                         case TEGRA_GPIO_BRIDGE_EN_1:
 238                                 label = "tegra-panel-bridge-en-1";
 239                                 break;
 240                         case TEGRA_GPIO_BRIDGE_REFCLK_EN:
 241                                 label = "tegra-panel-bridge-refclk-en";
 242                                 break;
 243                         default:
 244                                 pr_err("tegra panel no gpio entry\n");
 245                         }
 246                         if (label) {
 247                                 gpio_request(panel->panel_gpio[cnt],
 248                                         label);
 249                                 label = NULL;
 250                         }
 251                 }
 252         }
 253         if (gpio_is_valid(panel->panel_gpio[TEGRA_GPIO_PWM]))
 254                 gpio_free(panel->panel_gpio[TEGRA_GPIO_PWM]);
 255         panel->panel_gpio_populated = true;
 256 fail:
 257         of_node_put(node);
 258         return err;
 259 }
 260
 261 void tegra_set_fixed_panel_ops(bool is_primary,
 262         struct tegra_panel_ops *p_ops, char *panel_compatible)
 263 {
 264         if (is_primary) {
 265                 fixed_primary_panel_ops = p_ops;
 266                 fixed_primary_panel_compatible =
 267                         (const char *)panel_compatible;
 268         } else {
 269                 fixed_secondary_panel_ops = p_ops;
 270                 fixed_secondary_panel_compatible =
 271                         (const char *)panel_compatible;
 272         }
 273 }
 274
 275 void tegra_set_fixed_pwm_bl_ops(struct pwm_bl_data_dt_ops *p_ops)
 276 {
 277         fixed_pwm_bl_ops = p_ops;
 278 }
 279
 280 static bool tegra_available_pwm_bl_ops_register(struct device *dev)
 281 {
 282         struct device_node *np_bl = NULL;
 283         struct device_node *np_parent = NULL;
 284         const char *pn_compat = NULL;
 285         bool ret = false;
 286
 287         np_parent = of_find_node_by_path("/backlight");
 288         if (np_parent) {
 289                 for_each_available_child_of_node(np_parent, np_bl) {
 290                         if (np_bl)
 291                                 break;
 292                 }
 293         }
 294
 295         if (!np_bl) {
 296                 pr_info("no avaiable target backlight node\n");
 297                 goto end;
 298         }
 299
 300         pn_compat = of_get_property(np_bl, "compatible", NULL);
 301         if (!pn_compat) {
 302                 WARN(1, "No compatible prop in backlight node\n");
 303                 goto end;
 304         }
 305
 306         if (of_device_is_compatible(np_bl, "p,wuxga-10-1-bl")) {
 307                 dev_set_drvdata(dev, dsi_p_wuxga_10_1_ops.pwm_bl_ops);
 308         } else if (of_device_is_compatible(np_bl, "lg,wxga-7-bl")) {
 309                 dev_set_drvdata(dev, dsi_lgd_wxga_7_0_ops.pwm_bl_ops);
 310         } else if (of_device_is_compatible(np_bl, "s,wqxga-10-1-bl")) {
 311                 dev_set_drvdata(dev, dsi_s_wqxga_10_1_ops.pwm_bl_ops);
 312         } else if (of_device_is_compatible(np_bl, "c,wxga-14-0-bl")) {
 313                 dev_set_drvdata(dev, lvds_c_1366_14_ops.pwm_bl_ops);
 314         } else if (of_device_is_compatible(np_bl, "a,1080p-14-0-bl")) {
 315                 dev_set_drvdata(dev, dsi_a_1080p_14_0_ops.pwm_bl_ops);
 316         } else if (of_device_is_compatible(np_bl, "j,1440-810-5-8-bl")) {
 317                 dev_set_drvdata(dev, dsi_j_1440_810_5_8_ops.pwm_bl_ops);
 318         } else if (of_device_is_compatible(np_bl, "s,wuxga-7-0-bl")) {
 319                 dev_set_drvdata(dev, dsi_s_wuxga_7_0_ops.pwm_bl_ops);
 320         } else if (of_device_is_compatible(np_bl, "s,wuxga-8-0-bl")) {
 321                 dev_set_drvdata(dev, dsi_s_wuxga_8_0_ops.pwm_bl_ops);
 322         } else if (of_device_is_compatible(np_bl, "a,wuxga-8-0-bl")) {
 323                 dev_set_drvdata(dev, dsi_a_1200_1920_8_0_ops.pwm_bl_ops);
 324         } else if (of_device_is_compatible(np_bl, "a,wxga-8-0-bl")) {
 325                 dev_set_drvdata(dev, dsi_a_1200_800_8_0_ops.pwm_bl_ops);
 326         } else if (of_device_is_compatible(np_bl, "i-edp,1080p-11-6-bl")) {
 327                 dev_set_drvdata(dev, edp_i_1080p_11_6_ops.pwm_bl_ops);
 328         } else if (of_device_is_compatible(np_bl, "a-edp,1080p-14-0-bl")) {
 329                 dev_set_drvdata(dev, edp_a_1080p_14_0_ops.pwm_bl_ops);
 330         } else if (of_device_is_compatible(np_bl, "j,720p-5-0-bl")) {
 331                 dev_set_drvdata(dev, dsi_j_720p_5_ops.pwm_bl_ops);
 332         } else if (of_device_is_compatible(np_bl, "l,720p-5-0-bl")) {
 333                 dev_set_drvdata(dev, dsi_l_720p_5_loki_ops.pwm_bl_ops);
 334         } else if (of_device_is_compatible(np_bl, "s-edp,uhdtv-15-6-bl")) {
 335                 dev_set_drvdata(dev, edp_s_uhdtv_15_6_ops.pwm_bl_ops);
 336         } else {
 337                 pr_info("invalid compatible for backlight node\n");
 338                 goto end;
 339         }
 340
 341         ret = true;
 342 end:
 343         of_node_put(np_parent);
 344         of_node_put(np_bl);
 345         return ret;
 346 }
 347 static void tegra_pwm_bl_ops_reg_based_on_disp_board_id(struct device *dev)
 348 {
 349         struct board_info display_board;
 350
 351         bool is_dsi_a_1200_1920_8_0 = false;
 352         bool is_dsi_a_1200_800_8_0 = false;
 353         bool is_edp_i_1080p_11_6 = false;
 354         bool is_edp_a_1080p_14_0 = false;
 355         bool is_edp_s_2160p_15_6 = false;
 356
 357         tegra_get_display_board_info(&display_board);
 358
 359         switch (display_board.board_id) {
 360         case BOARD_E1627:
 361         case BOARD_E1797:
 362                 dev_set_drvdata(dev, dsi_p_wuxga_10_1_ops.pwm_bl_ops);
 363                 break;
 364         case BOARD_E1549:
 365                 dev_set_drvdata(dev, dsi_lgd_wxga_7_0_ops.pwm_bl_ops);
 366                 break;
 367         case BOARD_E1639:
 368         case BOARD_E1813:
 369         case BOARD_E2145:
 370                 dev_set_drvdata(dev, dsi_s_wqxga_10_1_ops.pwm_bl_ops);
 371                 break;
 372         case BOARD_PM366:
 373                 dev_set_drvdata(dev, lvds_c_1366_14_ops.pwm_bl_ops);
 374                 break;
 375         case BOARD_PM354:
 376                 dev_set_drvdata(dev, dsi_a_1080p_14_0_ops.pwm_bl_ops);
 377                 break;
 378         case BOARD_E2129:
 379                 dev_set_drvdata(dev, dsi_j_1440_810_5_8_ops.pwm_bl_ops);
 380                 break;
 381         case BOARD_E2534:
 382                 if (display_board.fab == 0x2)
 383                         dev_set_drvdata(dev,
 384                                 dsi_j_720p_5_ops.pwm_bl_ops);
 385                 else if (display_board.fab == 0x1)
 386                         dev_set_drvdata(dev,
 387                                 dsi_j_1440_810_5_8_ops.pwm_bl_ops);
 388                 else
 389                         dev_set_drvdata(dev,
 390                                 dsi_l_720p_5_loki_ops.pwm_bl_ops);
 391                 break;
 392         case BOARD_E1937:
 393         case BOARD_E2149:
 394                 is_dsi_a_1200_1920_8_0 = true;
 395                 break;
 396         case BOARD_E1807:
 397                 is_dsi_a_1200_800_8_0 = true;
 398                 break;
 399         case BOARD_P1761:
 400                 if (tegra_get_board_panel_id())
 401                         is_dsi_a_1200_1920_8_0 = true;
 402                 else
 403                         is_dsi_a_1200_800_8_0 = true;
 404                 break;
 405         case BOARD_PM363:
 406         case BOARD_E1824:
 407                 if (of_machine_is_compatible("nvidia,jetson-cv"))
 408                         is_edp_s_2160p_15_6 = true;
 409                 else if (display_board.sku == 1200)
 410                         is_edp_i_1080p_11_6 = true;
 411                 else
 412                         is_edp_a_1080p_14_0 = true;
 413                 break;
 414         default:
 415                 /* TODO
 416                  * Finally, check if there's fixed_pwm_bl_ops
 417                  */
 418                 if (fixed_pwm_bl_ops)
 419                         dev_set_drvdata(dev, fixed_pwm_bl_ops);
 420                 else
 421                         pr_info("pwm_bl_ops are not required\n");
 422         };
 423
 424         if (is_dsi_a_1200_1920_8_0)
 425                 dev_set_drvdata(dev, dsi_a_1200_1920_8_0_ops.pwm_bl_ops);
 426         if (is_dsi_a_1200_800_8_0)
 427                 dev_set_drvdata(dev, dsi_a_1200_800_8_0_ops.pwm_bl_ops);
 428
 429         if (is_edp_i_1080p_11_6)
 430                 dev_set_drvdata(dev, edp_i_1080p_11_6_ops.pwm_bl_ops);
 431         if (is_edp_a_1080p_14_0)
 432                 dev_set_drvdata(dev, edp_a_1080p_14_0_ops.pwm_bl_ops);
 433         if (is_edp_s_2160p_15_6)
 434                 dev_set_drvdata(dev, edp_s_uhdtv_15_6_ops.pwm_bl_ops);
 435 }
 436
 437 void tegra_pwm_bl_ops_register(struct device *dev)
 438 {
 439         bool ret = 0;
 440         ret = tegra_available_pwm_bl_ops_register(dev);
 441         if (!ret)
 442                 tegra_pwm_bl_ops_reg_based_on_disp_board_id(dev);
 443 }
 444
 445 void ti_lp855x_bl_ops_register(struct device *dev)
 446 {
 447         dev_set_drvdata(dev, &generic_bl_ops);
 448 }
 449
 450 static void tegra_panel_register_ops(struct tegra_dc_out *dc_out,
 451                                 struct tegra_panel_ops *p_ops)
 452 {
 453         BUG_ON(!dc_out);
 454
 455         if (!p_ops) {
 456                 /* TODO: register default ops */
 457         }
 458
 459         dc_out->enable = p_ops->enable;
 460         dc_out->postpoweron = p_ops->postpoweron;
 461         dc_out->prepoweroff = p_ops->prepoweroff;
 462         dc_out->disable = p_ops->disable;
 463         dc_out->hotplug_init = p_ops->hotplug_init;
 464         dc_out->postsuspend = p_ops->postsuspend;
 465         dc_out->hotplug_report = p_ops->hotplug_report;
 466 }
 467 static struct device_node *available_internal_panel_select(
 468                         struct tegra_dc_platform_data *pdata)
 469 {
 470         struct device_node *np_panel = NULL;
 471         struct device_node *np_dsi = NULL, *np_sor = NULL;
 472         struct tegra_dc_out *dc_out = NULL;
 473         const char *pn_compat = NULL;
 474
 475         /*
 476          * for internal panel node, search
 477          * child node from DSI_NODE at first.
 478          * If child node is not found, search
 479          * child node from SOR_NODE.
 480          */
 481
 482         np_dsi = of_find_node_by_path(DSI_NODE);
 483         if (np_dsi) {
 484                 for_each_available_child_of_node(np_dsi, np_panel) {
 485                         if (np_panel)
 486                                 break;
 487                 }
 488         }
 489
 490         if (!np_panel) {
 491                 np_sor = of_find_node_by_path(SOR_NODE);
 492                 if (np_sor) {
 493                         for_each_available_child_of_node(np_sor, np_panel) {
 494                                 if (np_panel && of_get_child_by_name(
 495                                         np_panel, "disp-default-out"))
 496                                                 break;
 497                         }
 498                 }
 499         }
 500
 501         if (!np_panel) {
 502                 pr_info("panel_select fail by _node_status\n");
 503                 goto end;
 504         }
 505
 506         if (!pdata)
 507                 goto end;
 508
 509         dc_out = pdata->default_out;
 510         if (!dc_out) {
 511                 WARN(1, "dc_out is not valid\n");
 512                 of_node_put(np_panel);
 513                 np_panel = NULL;
 514                 goto end;
 515         }
 516
 517         pn_compat = of_get_property(np_panel, "compatible", NULL);
 518         if (!pn_compat) {
 519                 WARN(1, "panel node do not have compatible prop\n");
 520                 of_node_put(np_panel);
 521                 np_panel = NULL;
 522                 goto end;
 523         }
 524
 525         if (of_device_is_compatible(np_panel, "p,wuxga-10-1")) {
 526                 tegra_panel_register_ops(dc_out,
 527                         &dsi_p_wuxga_10_1_ops);
 528         } else if (of_device_is_compatible(np_panel, "lg,wxga-7")) {
 529                 tegra_panel_register_ops(dc_out,
 530                         &dsi_lgd_wxga_7_0_ops);
 531         } else if (of_device_is_compatible(np_panel, "s,wqxga-10-1")) {
 532                 tegra_panel_register_ops(dc_out,
 533                         &dsi_s_wqxga_10_1_ops);
 534         } else if (of_device_is_compatible(np_panel, "c,wxga-14-0")) {
 535                 tegra_panel_register_ops(dc_out,
 536                         &lvds_c_1366_14_ops);
 537         } else if (of_device_is_compatible(np_panel, "a,1080p-14-0")) {
 538                 tegra_panel_register_ops(dc_out,
 539                         &dsi_a_1080p_14_0_ops);
 540         } else if (of_device_is_compatible(np_panel, "j,1440-810-5-8")) {
 541                 tegra_panel_register_ops(dc_out,
 542                         &dsi_j_1440_810_5_8_ops);
 543         } else if (of_device_is_compatible(np_panel, "s,wuxga-7-0")) {
 544                 tegra_panel_register_ops(dc_out,
 545                         &dsi_s_wuxga_7_0_ops);
 546         } else if (of_device_is_compatible(np_panel, "s,wuxga-8-0")) {
 547                 tegra_panel_register_ops(dc_out,
 548                         &dsi_s_wuxga_8_0_ops);
 549         } else if (of_device_is_compatible(np_panel, "a,wuxga-8-0")) {
 550                 tegra_panel_register_ops(dc_out,
 551                         &dsi_a_1200_1920_8_0_ops);
 552         } else if (of_device_is_compatible(np_panel, "a,wxga-8-0")) {
 553                 tegra_panel_register_ops(dc_out,
 554                         &dsi_a_1200_800_8_0_ops);
 555         } else if (of_device_is_compatible(np_panel, "i-edp,1080p-11-6")) {
 556                 tegra_panel_register_ops(dc_out,
 557                         &edp_i_1080p_11_6_ops);
 558         } else if (of_device_is_compatible(np_panel, "a-edp,1080p-14-0")) {
 559                 tegra_panel_register_ops(dc_out,
 560                         &edp_a_1080p_14_0_ops);
 561         } else if (of_device_is_compatible(np_panel, "j,720p-5-0")) {
 562                 tegra_panel_register_ops(dc_out,
 563                         &dsi_j_720p_5_ops);
 564         } else if (of_device_is_compatible(np_panel, "l,720p-5-0")) {
 565                 tegra_panel_register_ops(dc_out,
 566                         &dsi_l_720p_5_loki_ops);
 567         } else if (of_device_is_compatible(np_panel, "s-edp,uhdtv-15-6")) {
 568                 tegra_panel_register_ops(dc_out,
 569                         &edp_s_uhdtv_15_6_ops);
 570         } else {
 571                 pr_info("invalid panel compatible\n");
 572                 of_node_put(np_panel);
 573                 np_panel = NULL;
 574         }
 575
 576 end:
 577         of_node_put(np_dsi);
 578         of_node_put(np_sor);
 579         return np_panel;
 580 }
 581
 582 static struct device_node
 583         *internal_panel_select_by_disp_board_id(
 584                 struct tegra_dc_platform_data *pdata)
 585 {
 586         struct device_node *np_panel = NULL;
 587         struct tegra_dc_out *dc_out = NULL;
 588         struct board_info display_board;
 589
 590         bool is_dsi_a_1200_1920_8_0 = false;
 591         bool is_dsi_a_1200_800_8_0 = false;
 592         bool is_edp_i_1080p_11_6 = false;
 593         bool is_edp_a_1080p_14_0 = false;
 594         bool is_edp_s_2160p_15_6 = false;
 595
 596         tegra_get_display_board_info(&display_board);
 597         pr_info("display board info: id 0x%x, fab 0x%x\n",
 598                 display_board.board_id, display_board.fab);
 599
 600         if (pdata)
 601                 dc_out = pdata->default_out;
 602
 603         switch (display_board.board_id) {
 604         case BOARD_E1627:
 605         case BOARD_E1797:
 606                 np_panel = of_find_compatible_node(NULL, NULL, "p,wuxga-10-1");
 607                 if (np_panel && pdata && dc_out)
 608                         tegra_panel_register_ops(dc_out,
 609                                 &dsi_p_wuxga_10_1_ops);
 610                 break;
 611         case BOARD_E1549:
 612                 np_panel = of_find_compatible_node(NULL, NULL, "lg,wxga-7");
 613                 if (np_panel && pdata && dc_out)
 614                         tegra_panel_register_ops(dc_out,
 615                                 &dsi_lgd_wxga_7_0_ops);
 616                 break;
 617         case BOARD_E1639:
 618         case BOARD_E1813:
 619         case BOARD_E2145:
 620                 np_panel = of_find_compatible_node(NULL, NULL, "s,wqxga-10-1");
 621                 if (np_panel && pdata && dc_out)
 622                         tegra_panel_register_ops(dc_out,
 623                                 &dsi_s_wqxga_10_1_ops);
 624                 break;
 625         case BOARD_PM366:
 626                 np_panel = of_find_compatible_node(NULL, NULL, "c,wxga-14-0");
 627                 if (np_panel && pdata && dc_out)
 628                         tegra_panel_register_ops(dc_out,
 629                                 &lvds_c_1366_14_ops);
 630                 break;
 631         case BOARD_PM354:
 632                 np_panel = of_find_compatible_node(NULL, NULL, "a,1080p-14-0");
 633                 if (np_panel && pdata && dc_out)
 634                         tegra_panel_register_ops(dc_out,
 635                                 &dsi_a_1080p_14_0_ops);
 636                 break;
 637         case BOARD_E2129:
 638                 np_panel = of_find_compatible_node(NULL,
 639                         NULL, "j,1440-810-5-8");
 640                 if (np_panel && pdata && dc_out)
 641                         tegra_panel_register_ops(dc_out,
 642                                 &dsi_j_1440_810_5_8_ops);
 643                 break;
 644         case BOARD_E2534:
 645                 if (display_board.fab == 0x2) {
 646                         np_panel = of_find_compatible_node(NULL, NULL,
 647                                 "j,720p-5-0");
 648                         if (np_panel && pdata && dc_out)
 649                                 tegra_panel_register_ops(dc_out,
 650                                         &dsi_j_720p_5_ops);
 651                 } else if (display_board.fab == 0x1) {
 652                         np_panel = of_find_compatible_node(NULL, NULL,
 653                                 "j,1440-810-5-8");
 654                         if (np_panel && pdata && dc_out)
 655                                 tegra_panel_register_ops(dc_out,
 656                                         &dsi_j_1440_810_5_8_ops);
 657                 } else {
 658                         np_panel = of_find_compatible_node(NULL, NULL,
 659                                 "l,720p-5-0");
 660                         if (np_panel && pdata && dc_out)
 661                                 tegra_panel_register_ops(dc_out,
 662                                         &dsi_l_720p_5_loki_ops);
 663                 }
 664                 break;
 665         case BOARD_E1937:
 666         case BOARD_E2149:
 667                 is_dsi_a_1200_1920_8_0 = true;
 668                 break;
 669         case BOARD_E1807:
 670                 is_dsi_a_1200_800_8_0 = true;
 671                 break;
 672         case BOARD_P1761:
 673                 if (tegra_get_board_panel_id())
 674                         is_dsi_a_1200_1920_8_0 = true;
 675                 else
 676                         is_dsi_a_1200_800_8_0 = true;
 677                 break;
 678         case BOARD_PM363:
 679         case BOARD_E1824:
 680                 if (of_machine_is_compatible("nvidia,jetson-cv"))
 681                         is_edp_s_2160p_15_6 = true;
 682                 else if (display_board.sku == 1200)
 683                         is_edp_i_1080p_11_6 = true;
 684                 else
 685                         is_edp_a_1080p_14_0 = true;
 686                 break;
 687         default:
 688                 /* If display panel is not searched by display board id,
 689                  * check if there's fixed primary panel.
 690                  */
 691                 if (fixed_primary_panel_ops &&
 692                         fixed_primary_panel_compatible) {
 693                         np_panel = of_find_compatible_node(NULL, NULL,
 694                                 fixed_primary_panel_compatible);
 695                         if (np_panel && pdata && dc_out)
 696                                 tegra_panel_register_ops(dc_out,
 697                                         fixed_primary_panel_ops);
 698                 }
 699         };
 700
 701         if (is_dsi_a_1200_1920_8_0) {
 702                 np_panel = of_find_compatible_node(NULL, NULL,
 703                                 "a,wuxga-8-0");
 704                 if (np_panel && pdata && dc_out)
 705                         tegra_panel_register_ops(dc_out,
 706                                 &dsi_a_1200_1920_8_0_ops);
 707         }
 708         if (is_dsi_a_1200_800_8_0) {
 709                 np_panel = of_find_compatible_node(NULL, NULL,
 710                                 "a,wxga-8-0");
 711                 if (np_panel && pdata && dc_out)
 712                         tegra_panel_register_ops(dc_out,
 713                                 &dsi_a_1200_800_8_0_ops);
 714         }
 715
 716         if (is_edp_i_1080p_11_6) {
 717                 np_panel = of_find_compatible_node(NULL, NULL,
 718                                 "i-edp,1080p-11-6");
 719                 if (np_panel && pdata && dc_out)
 720                         tegra_panel_register_ops(dc_out,
 721                                 &edp_i_1080p_11_6_ops);
 722         }
 723         if (is_edp_a_1080p_14_0) {
 724                 np_panel = of_find_compatible_node(NULL, NULL,
 725                                 "a-edp,1080p-14-0");
 726                 if (np_panel && pdata && dc_out)
 727                         tegra_panel_register_ops(dc_out,
 728                                 &edp_a_1080p_14_0_ops);
 729         }
 730         if (is_edp_s_2160p_15_6) {
 731                 np_panel = of_find_compatible_node(NULL, NULL,
 732                                 "s-edp,uhdtv-15-6");
 733                 if (np_panel && pdata && dc_out)
 734                         tegra_panel_register_ops(dc_out,
 735                                 &edp_s_uhdtv_15_6_ops);
 736         }
 737         if (np_panel)
 738                 return np_panel;
 739         else
 740                 return NULL;
 741 }
 742
 743 struct device_node *tegra_primary_panel_get_dt_node(
 744                         struct tegra_dc_platform_data *pdata)
 745 {
 746         struct device_node *np_panel = NULL;
 747         struct tegra_dc_out *dc_out = NULL;
 748         struct device_node *np_hdmi =
 749                 of_find_node_by_path(HDMI_NODE);
 750
 751         if (pdata)
 752                 dc_out = pdata->default_out;
 753
 754         np_panel =
 755                 internal_panel_select_by_disp_board_id(pdata);
 756         if (np_panel) {
 757                 /*
 758                  * legacy method to select internal panel
 759                  * based on disp board id.
 760                  */
 761                 of_node_put(np_hdmi);
 762                 return np_panel;
 763         };
 764
 765         np_panel =
 766                 available_internal_panel_select(pdata);
 767         if (np_panel) {
 768                 /*
 769                  * search internal panel node by
 770                  * status property.
 771                  */
 772                 of_node_put(np_hdmi);
 773                 return np_panel;
 774         };
 775
 776         /*
 777          * Check hdmi primary, if there's neither
 778          * valid internal panel nor fixed panel.
 779          */
 780         np_panel =
 781                 of_get_child_by_name(np_hdmi, "hdmi-display");
 782
 783         of_node_put(np_hdmi);
 784         return of_device_is_available(np_panel) ? np_panel : NULL;
 785 }
 786
 787 struct device_node *tegra_secondary_panel_get_dt_node(
 788                         struct tegra_dc_platform_data *pdata)
 789 {
 790         struct device_node *np_panel = NULL, *np_display = NULL;
 791         struct tegra_dc_out *dc_out = NULL;
 792         const char *sor1_output_type;
 793
 794         if (pdata)
 795                 dc_out = pdata->default_out;
 796
 797         if (fixed_secondary_panel_ops &&
 798                         fixed_secondary_panel_compatible) {
 799                         np_panel = of_find_compatible_node(NULL, NULL,
 800                                 fixed_secondary_panel_compatible);
 801                         if (np_panel && pdata && dc_out)
 802                                 tegra_panel_register_ops(dc_out,
 803                                         fixed_secondary_panel_ops);
 804         } else {
 805                 np_display = of_find_node_by_path(SOR1_NODE);
 806                 if (!of_property_read_string(np_display,
 807                         "nvidia,sor1-output-type", &sor1_output_type)) {
 808                         if (strcmp(sor1_output_type, "dp") == 0) {
 809                                 np_panel = of_get_child_by_name(np_display,
 810                                                 "dp-display");
 811                                 goto success;
 812                         }
 813                 }
 814         }
 815
 816         of_node_put(np_display);
 817         np_display = of_find_node_by_path(HDMI_NODE);
 818         np_panel = of_get_child_by_name(np_display, "hdmi-display");
 819
 820 success:
 821         of_node_put(np_display);
 822         return of_device_is_available(np_panel) ? np_panel : NULL;
 823 }
 824
 825 void tegra_fb_copy_or_clear(void)
 826 {
 827         bool fb_existed = (tegra_fb_start && tegra_fb_size) ?
 828                 true : false;
 829         bool fb2_existed = (tegra_fb2_start && tegra_fb2_size) ?
 830                 true : false;
 831
 832         /* Copy the bootloader fb to the fb. */
 833         if (fb_existed) {
 834                 if (tegra_bootloader_fb_size)
 835                         __tegra_move_framebuffer(NULL,
 836                                 tegra_fb_start, tegra_bootloader_fb_start,
 837                                 min(tegra_fb_size, tegra_bootloader_fb_size));
 838                 else
 839                         __tegra_clear_framebuffer(NULL,
 840                                 tegra_fb_start, tegra_fb_size);
 841         }
 842
 843         /* Copy the bootloader fb2 to the fb2. */
 844         if (fb2_existed) {
 845                 if (tegra_bootloader_fb2_size)
 846                         __tegra_move_framebuffer(NULL,
 847                                 tegra_fb2_start, tegra_bootloader_fb2_start,
 848                                 min(tegra_fb2_size, tegra_bootloader_fb2_size));
 849                 else
 850                         __tegra_clear_framebuffer(NULL,
 851                                 tegra_fb2_start, tegra_fb2_size);
 852         }
 853 }
 854
 855 int tegra_disp_defer_vcore_override(void)
 856 {
 857 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
 858         struct clk *disp1_clk = clk_get_sys("tegradc.0", NULL);
 859         struct clk *disp2_clk = clk_get_sys("tegradc.1", NULL);
 860         long disp1_rate = 0;
 861         long disp2_rate = 0;
 862         struct device_node *np_target_disp1 = NULL;
 863         struct device_node *np_target_disp2 = NULL;
 864         struct device_node *np_disp1_timings = NULL;
 865         struct device_node *np_disp1_def_out = NULL;
 866         struct device_node *np_disp2_def_out = NULL;
 867         struct device_node *entry = NULL;
 868         u32 temp = 0;
 869         bool is_hdmi_primary = false;
 870
 871         if (WARN_ON(IS_ERR(disp1_clk))) {
 872                 if (disp2_clk && !IS_ERR(disp2_clk))
 873                         clk_put(disp2_clk);
 874                 return PTR_ERR(disp1_clk);
 875         }
 876
 877         if (WARN_ON(IS_ERR(disp2_clk))) {
 878                 clk_put(disp1_clk);
 879                 return PTR_ERR(disp1_clk);
 880         }
 881
 882         np_target_disp1 = tegra_primary_panel_get_dt_node(NULL);
 883         np_target_disp2 = tegra_secondary_panel_get_dt_node(NULL);
 884
 885         if (np_target_disp1)
 886                 if (of_device_is_compatible(np_target_disp1, "hdmi,display"))
 887                         is_hdmi_primary = true;
 888
 889         if (!is_hdmi_primary) {
 890                 /*
 891                  * internal panel is mapped to dc0,
 892                  * hdmi disp is mapped to dc1.
 893                  */
 894                 if (np_target_disp1) {
 895                         np_disp1_timings =
 896                                 of_get_child_by_name(np_target_disp1,
 897                                 "display-timings");
 898                 }
 899                 if (np_disp1_timings) {
 900                         for_each_child_of_node(np_disp1_timings, entry) {
 901                                 if (!of_property_read_u32(entry,
 902                                         "clock-frequency", &temp)) {
 903                                         disp1_rate = (long) temp;
 904                                         break;
 905                                 }
 906                         }
 907                 }
 908                 if (np_target_disp2) {
 909                         np_disp2_def_out =
 910                                 of_get_child_by_name(np_target_disp2,
 911                                 "disp-default-out");
 912                 }
 913
 914                 if (np_disp2_def_out) {
 915                         if (!of_property_read_u32(np_disp2_def_out,
 916                                 "nvidia,out-max-pixclk", &temp)) {
 917                                 disp2_rate = PICOS2KHZ(temp) * 1000;
 918                         }
 919                 } else
 920                         disp2_rate = 297000000; /* HDMI 4K */
 921                 if (disp1_rate)
 922                         tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
 923                 if (disp2_rate)
 924                         tegra_dvfs_resolve_override(disp2_clk, disp2_rate);
 925         } else {
 926                 /*
 927                  * this is hdmi primary
 928                  */
 929                 if (np_target_disp1) {
 930                         np_disp1_def_out =
 931                                 of_get_child_by_name(np_target_disp1,
 932                                 "disp-default-out");
 933                 }
 934                 if (np_disp1_def_out) {
 935                         if (!of_property_read_u32(np_disp1_def_out,
 936                                 "nvidia,out-max-pixclk", &temp)) {
 937                                 disp1_rate = PICOS2KHZ(temp) * 1000;
 938                         }
 939                 } else
 940                         disp1_rate = 297000000; /* HDMI 4K */
 941
 942                 if (disp1_rate)
 943                         tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
 944         }
 945
 946         clk_put(disp1_clk);
 947         clk_put(disp2_clk);
 948 #endif
 949         return 0;
 950 }