drivers/video/tegra/dc/sor.c

   1 /*
   2  * drivers/video/tegra/dc/sor.c
   3  *
   4  * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/nvhost.h>
  20 #include <linux/kernel.h>
  21 #include <linux/fb.h>
  22 #include <linux/delay.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/debugfs.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27
  28 #include <mach/dc.h>
  29 #include <mach/io_dpd.h>
  30
  31 #include "sor.h"
  32 #include "sor_regs.h"
  33 #include "dc_priv.h"
  34 #include "dp.h"
  35
  36 #include "../../../../arch/arm/mach-tegra/iomap.h"
  37
  38 #define APBDEV_PMC_DPD_SAMPLE                           (0x20)
  39 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE                (0)
  40 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE                 (1)
  41 #define APBDEV_PMC_SEL_DPD_TIM                          (0x1c8)
  42 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT      (0x7f)
  43 #define APBDEV_PMC_IO_DPD2_REQ                          (0x1c0)
  44 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT               (25)
  45 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF                 (0 << 25)
  46 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON                  (1 << 25)
  47 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT               (30)
  48 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK        (0x3 << 30)
  49 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE                (0 << 30)
  50 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF             (1 << 30)
  51 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON              (2 << 30)
  52 #define APBDEV_PMC_IO_DPD2_STATUS                       (0x1c4)
  53 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT            (25)
  54 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF              (0 << 25)
  55 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON               (1 << 25)
  56
  57 static unsigned long
  58 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
  59                                 u32 reg, u32 mask, u32 exp_val,
  60                                 u32 poll_interval_us, u32 timeout_ms)
  61 {
  62         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
  63         u32 reg_val = 0;
  64
  65         if (tegra_platform_is_linsim())
  66                 return 0;
  67         do {
  68                 reg_val = tegra_sor_readl(sor, reg);
  69                 if ((reg_val & mask) == exp_val)
  70                         return 0;       /* success */
  71
  72                 udelay(poll_interval_us);
  73         } while (time_after(timeout_jf, jiffies));
  74
  75         dev_err(&sor->dc->ndev->dev,
  76                 "sor_poll_register 0x%x: timeout\n", reg);
  77         return jiffies - timeout_jf + 1;
  78 }
  79
  80 void tegra_sor_config_safe_clk(struct tegra_dc_sor_data *sor)
  81 {
  82         int flag = tegra_is_clk_enabled(sor->sor_clk);
  83
  84         if (sor->clk_type == TEGRA_SOR_SAFE_CLK || tegra_platform_is_linsim())
  85                 return;
  86
  87         /*
  88          * HW bug 1425607
  89          * Disable clocks to avoid glitch when switching
  90          * between safe clock and macro pll clock
  91          */
  92         if (flag)
  93                 clk_disable_unprepare(sor->sor_clk);
  94
  95         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 0);
  96
  97         if (flag)
  98                 clk_prepare_enable(sor->sor_clk);
  99
 100         sor->clk_type = TEGRA_SOR_SAFE_CLK;
 101 }
 102
 103 void tegra_sor_config_dp_clk(struct tegra_dc_sor_data *sor)
 104 {
 105         int flag = tegra_is_clk_enabled(sor->sor_clk);
 106         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(sor->dc);
 107
 108         if (sor->clk_type == TEGRA_SOR_MACRO_CLK)
 109                 return;
 110
 111         tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
 112                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
 113                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
 114         tegra_dc_sor_set_link_bandwidth(sor, dp->link_cfg.link_bw ? :
 115                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62);
 116
 117         /*
 118          * HW bug 1425607
 119          * Disable clocks to avoid glitch when switching
 120          * between safe clock and macro pll clock
 121          *
 122          * Select alternative -- DP -- DVFS table for SOR clock (if SOR clock
 123          * has single DVFS table for all modes, nothing changes).
 124          */
 125         if (flag)
 126                 clk_disable_unprepare(sor->sor_clk);
 127
 128         tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, true);
 129
 130         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 1);
 131
 132         if (flag)
 133                 clk_prepare_enable(sor->sor_clk);
 134
 135         sor->clk_type = TEGRA_SOR_MACRO_CLK;
 136 }
 137
 138 #ifdef CONFIG_DEBUG_FS
 139 static int dbg_sor_show(struct seq_file *s, void *unused)
 140 {
 141         struct tegra_dc_sor_data *sor = s->private;
 142
 143 #define DUMP_REG(a) seq_printf(s, "%-32s  %03x  %08x\n",                \
 144                 #a, a, tegra_sor_readl(sor, a));
 145
 146         if (!tegra_powergate_is_powered(TEGRA_POWERGATE_SOR)) {
 147                 seq_puts(s, "SOR is powergated\n");
 148                 return 0;
 149         }
 150
 151         tegra_dc_io_start(sor->dc);
 152         tegra_sor_clk_enable(sor);
 153
 154         DUMP_REG(NV_SOR_SUPER_STATE0);
 155         DUMP_REG(NV_SOR_SUPER_STATE1);
 156         DUMP_REG(NV_SOR_STATE0);
 157         DUMP_REG(NV_SOR_STATE1);
 158         DUMP_REG(NV_HEAD_STATE0(0));
 159         DUMP_REG(NV_HEAD_STATE0(1));
 160         DUMP_REG(NV_HEAD_STATE1(0));
 161         DUMP_REG(NV_HEAD_STATE1(1));
 162         DUMP_REG(NV_HEAD_STATE2(0));
 163         DUMP_REG(NV_HEAD_STATE2(1));
 164         DUMP_REG(NV_HEAD_STATE3(0));
 165         DUMP_REG(NV_HEAD_STATE3(1));
 166         DUMP_REG(NV_HEAD_STATE4(0));
 167         DUMP_REG(NV_HEAD_STATE4(1));
 168         DUMP_REG(NV_HEAD_STATE5(0));
 169         DUMP_REG(NV_HEAD_STATE5(1));
 170         DUMP_REG(NV_SOR_CRC_CNTRL);
 171         DUMP_REG(NV_SOR_CLK_CNTRL);
 172         DUMP_REG(NV_SOR_CAP);
 173         DUMP_REG(NV_SOR_PWR);
 174         DUMP_REG(NV_SOR_TEST);
 175         DUMP_REG(NV_SOR_PLL0);
 176         DUMP_REG(NV_SOR_PLL1);
 177         DUMP_REG(NV_SOR_PLL2);
 178         DUMP_REG(NV_SOR_PLL3);
 179         DUMP_REG(NV_SOR_CSTM);
 180         DUMP_REG(NV_SOR_LVDS);
 181         DUMP_REG(NV_SOR_CRCA);
 182         DUMP_REG(NV_SOR_CRCB);
 183         DUMP_REG(NV_SOR_SEQ_CTL);
 184         DUMP_REG(NV_SOR_LANE_SEQ_CTL);
 185         DUMP_REG(NV_SOR_SEQ_INST(0));
 186         DUMP_REG(NV_SOR_SEQ_INST(1));
 187         DUMP_REG(NV_SOR_SEQ_INST(2));
 188         DUMP_REG(NV_SOR_SEQ_INST(3));
 189         DUMP_REG(NV_SOR_SEQ_INST(4));
 190         DUMP_REG(NV_SOR_SEQ_INST(5));
 191         DUMP_REG(NV_SOR_SEQ_INST(6));
 192         DUMP_REG(NV_SOR_SEQ_INST(7));
 193         DUMP_REG(NV_SOR_SEQ_INST(8));
 194         DUMP_REG(NV_SOR_PWM_DIV);
 195         DUMP_REG(NV_SOR_PWM_CTL);
 196         DUMP_REG(NV_SOR_MSCHECK);
 197         DUMP_REG(NV_SOR_XBAR_CTRL);
 198         DUMP_REG(NV_SOR_XBAR_POL);
 199         DUMP_REG(NV_SOR_DP_LINKCTL(0));
 200         DUMP_REG(NV_SOR_DP_LINKCTL(1));
 201         DUMP_REG(NV_SOR_DC(0));
 202         DUMP_REG(NV_SOR_DC(1));
 203         DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
 204         DUMP_REG(NV_SOR_PR(0));
 205         DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
 206         DUMP_REG(NV_SOR_POSTCURSOR(0));
 207         DUMP_REG(NV_SOR_DP_CONFIG(0));
 208         DUMP_REG(NV_SOR_DP_CONFIG(1));
 209         DUMP_REG(NV_SOR_DP_MN(0));
 210         DUMP_REG(NV_SOR_DP_MN(1));
 211         DUMP_REG(NV_SOR_DP_PADCTL(0));
 212         DUMP_REG(NV_SOR_DP_PADCTL(1));
 213         DUMP_REG(NV_SOR_DP_DEBUG(0));
 214         DUMP_REG(NV_SOR_DP_DEBUG(1));
 215         DUMP_REG(NV_SOR_DP_SPARE(0));
 216         DUMP_REG(NV_SOR_DP_SPARE(1));
 217         DUMP_REG(NV_SOR_DP_TPG);
 218         DUMP_REG(NV_SOR_HDMI2_CTRL);
 219         if (sor->instance) { /* sor1 */
 220                 DUMP_REG(NV_SOR_DP_AUDIO_CTRL);
 221
 222                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_HEADER);
 223                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(0));
 224                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(1));
 225                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(2));
 226                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(3));
 227                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(4));
 228                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(5));
 229                 DUMP_REG(NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(6));
 230
 231                 DUMP_REG(NV_SOR_DP_OUTPUT_CHANNEL_STATUS1);
 232                 DUMP_REG(NV_SOR_DP_OUTPUT_CHANNEL_STATUS2);
 233
 234                 DUMP_REG(NV_SOR_HDMI_AUDIO_N);
 235                 DUMP_REG(NV_SOR_HDMI2_CTRL);
 236
 237                 DUMP_REG(NV_SOR_AUDIO_NVAL_0320);
 238                 DUMP_REG(NV_SOR_AUDIO_NVAL_0441);
 239                 DUMP_REG(NV_SOR_AUDIO_NVAL_0882);
 240                 DUMP_REG(NV_SOR_AUDIO_NVAL_1764);
 241                 DUMP_REG(NV_SOR_AUDIO_NVAL_0480);
 242                 DUMP_REG(NV_SOR_AUDIO_NVAL_0960);
 243                 DUMP_REG(NV_SOR_AUDIO_NVAL_1920);
 244
 245                 DUMP_REG(NV_SOR_AUDIO_AVAL_0320);
 246                 DUMP_REG(NV_SOR_AUDIO_AVAL_0441);
 247                 DUMP_REG(NV_SOR_AUDIO_AVAL_0882);
 248                 DUMP_REG(NV_SOR_AUDIO_AVAL_1764);
 249                 DUMP_REG(NV_SOR_AUDIO_AVAL_0480);
 250                 DUMP_REG(NV_SOR_AUDIO_AVAL_0960);
 251                 DUMP_REG(NV_SOR_AUDIO_AVAL_1920);
 252
 253                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0320);
 254                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0441);
 255                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0882);
 256                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_1764);
 257                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0480);
 258                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_0960);
 259                 DUMP_REG(NV_SOR_DP_AUDIO_TIMESTAMP_1920);
 260
 261
 262         }
 263
 264         tegra_sor_clk_disable(sor);
 265         tegra_dc_io_end(sor->dc);
 266
 267         return 0;
 268 }
 269
 270 static int dbg_sor_open(struct inode *inode, struct file *file)
 271 {
 272         return single_open(file, dbg_sor_show, inode->i_private);
 273 }
 274
 275 static const struct file_operations dbg_fops = {
 276         .open           = dbg_sor_open,
 277         .read           = seq_read,
 278         .llseek         = seq_lseek,
 279         .release        = single_release,
 280 };
 281
 282 static int sor_crc_show(struct seq_file *s, void *unused)
 283 {
 284         struct tegra_dc_sor_data *sor = s->private;
 285         struct tegra_dc *dc = sor->dc;
 286         u32 reg_val;
 287         int i = 0;
 288
 289         tegra_dc_io_start(sor->dc);
 290         tegra_sor_clk_enable(sor);
 291
 292         reg_val = tegra_sor_readl(sor, NV_SOR_CRC_CNTRL);
 293         reg_val &= NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DEFAULT_MASK;
 294         if (reg_val == NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO) {
 295                 pr_err("SOR CRC is DISABLED, aborting with CRC=0\n");
 296                 seq_printf(s, "NV_SOR[%d]_CRCB = 0x%08x\n",
 297                         sor->dc->ctrl_num, reg_val);
 298                 goto exit;
 299         }
 300
 301         do {
 302                 if (tegra_dc_sor_poll_register(sor, NV_SOR_CRCA,
 303                                 NV_SOR_CRCA_VALID_DEFAULT_MASK,
 304                                 NV_SOR_CRCA_VALID_TRUE,
 305                                 100, TEGRA_SOR_TIMEOUT_MS)) {
 306                         dev_err(&sor->dc->ndev->dev,
 307                                 "NV_SOR[%d]_CRCA_VALID_TRUE timeout\n", i);
 308                         goto exit;
 309                 }
 310                 mutex_lock(&dc->lock);
 311                 reg_val = tegra_sor_readl(sor, NV_SOR_CRCB);
 312                 mutex_unlock(&dc->lock);
 313                 seq_printf(s, "NV_SOR[%x]_CRCB = 0x%08x\n",
 314                         sor->dc->ctrl_num, reg_val);
 315                 i++;
 316         } while (i < sor->portnum);
 317
 318 exit:
 319         tegra_sor_clk_disable(sor);
 320         tegra_dc_io_end(sor->dc);
 321
 322         return 0;
 323 }
 324
 325 static int sor_crc_open(struct inode *inode, struct file *file)
 326 {
 327         return single_open(file, sor_crc_show, inode->i_private);
 328 }
 329
 330 static ssize_t sor_crc_write(struct file *file,
 331                                 const char  *buf, size_t count, loff_t *off)
 332 {
 333         struct seq_file *s = file->private_data;
 334         struct tegra_dc_sor_data *sor = s->private;
 335         struct tegra_dc *dc = sor->dc;
 336         u32 reg_val;
 337         u32    data;
 338         int    i = 0;
 339         static u8 asy_crcmode;
 340
 341         if (sscanf(buf, "%x", &data) != 1)
 342                 return -EINVAL;
 343         /* at this point:
 344          * data[0:0] = 1|0: enable|disable CRC
 345          * data[5:4] contains ASY_CRCMODE */
 346
 347         tegra_dc_io_start(sor->dc);
 348         tegra_sor_clk_enable(sor);
 349
 350         asy_crcmode = data & (NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK >> 2);
 351         asy_crcmode >>= 4;  /* asy_crcmode[1:0] = ASY_CRCMODE */
 352         data &= 1;          /* data[0:0] = enable|disable CRC */
 353         mutex_lock(&dc->lock);
 354         do {
 355                 if (data == 1) {
 356                         reg_val = tegra_sor_readl(sor, NV_SOR_CRCA);
 357                         if (reg_val & NV_SOR_CRCA_VALID_TRUE) {
 358                                 tegra_sor_write_field(sor,
 359                                         NV_SOR_CRCA,
 360                                         NV_SOR_CRCA_VALID_DEFAULT_MASK,
 361                                         NV_SOR_CRCA_VALID_RST << NV_SOR_CRCA_VALID_SHIFT);
 362                         }
 363                         tegra_sor_write_field(sor,
 364                                 NV_SOR_TEST,
 365                                 NV_SOR_TEST_CRC_DEFAULT_MASK,
 366                                 NV_SOR_TEST_CRC_PRE_SERIALIZE << NV_SOR_TEST_CRC_SHIFT);
 367                         tegra_sor_write_field(sor, NV_SOR_STATE1,
 368                                 NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK,
 369                                 asy_crcmode << NV_SOR_STATE1_ASY_CRCMODE_SHIFT);
 370                         tegra_sor_write_field(sor,
 371                                 NV_SOR_STATE0,
 372                                 NV_SOR_STATE0_UPDATE_DEFAULT_MASK,
 373                                 NV_SOR_STATE0_UPDATE_UPDATE << NV_SOR_STATE0_UPDATE_SHIFT);
 374                 }
 375                 reg_val = tegra_sor_readl(sor, NV_SOR_CRC_CNTRL);
 376                 tegra_sor_write_field(sor,
 377                         NV_SOR_CRC_CNTRL,
 378                         NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DEFAULT_MASK,
 379                         data << NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT);
 380                 reg_val = tegra_sor_readl(sor, NV_SOR_CRC_CNTRL);
 381                 i++;
 382         } while (i < sor->portnum);
 383
 384         mutex_unlock(&dc->lock);
 385         tegra_sor_clk_disable(sor);
 386         tegra_dc_io_end(sor->dc);
 387
 388         return count;
 389 }
 390
 391 static const struct file_operations crc_fops = {
 392         .open           = sor_crc_open,
 393         .read           = seq_read,
 394         .write          = sor_crc_write,
 395         .llseek         = seq_lseek,
 396         .release        = single_release,
 397 };
 398
 399 static struct dentry *sordir;
 400
 401 static void tegra_dc_sor_debug_create(struct tegra_dc_sor_data *sor,
 402         const char *res_name)
 403 {
 404         struct dentry *retval;
 405         char sor_path[16];
 406
 407         BUG_ON(!res_name);
 408         snprintf(sor_path, sizeof(sor_path), "tegra_%s", res_name ? : "sor");
 409         sordir = debugfs_create_dir(sor_path, NULL);
 410         if (!sordir)
 411                 return;
 412         retval = debugfs_create_file("regs", S_IRUGO, sordir, sor, &dbg_fops);
 413         if (!retval)
 414                 goto free_out;
 415
 416         retval = debugfs_create_file("crc", S_IWUGO|S_IRUGO, sordir,
 417                 sor, &crc_fops);
 418         if (!retval)
 419                 goto free_out;
 420
 421         return;
 422 free_out:
 423         debugfs_remove_recursive(sordir);
 424         sordir = NULL;
 425         return;
 426 }
 427 EXPORT_SYMBOL(tegra_dc_sor_debug_create);
 428 #else
 429 static inline void tegra_dc_sor_debug_create(struct tegra_dc_sor_data *sor,
 430         const char *res_name)
 431 { }
 432 #endif
 433
 434 struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
 435                                 const struct tegra_dc_dp_link_config *cfg)
 436 {
 437         struct tegra_dc_sor_data *sor;
 438         struct resource *res;
 439         struct resource *base_res;
 440         struct resource of_sor_res;
 441         void __iomem *base;
 442         struct clk *clk;
 443         int err, i;
 444         struct clk *safe_clk = NULL;
 445         struct clk *brick_clk = NULL;
 446         struct clk *src_clk = NULL;
 447         struct device_node *np = dc->ndev->dev.of_node;
 448         int sor_num = tegra_dc_which_sor(dc);
 449         struct device_node *np_sor =
 450                 sor_num ? of_find_node_by_path(SOR1_NODE) :
 451                 of_find_node_by_path(SOR_NODE);
 452         const char *res_name = sor_num ? "sor1" : "sor0";
 453
 454         sor = devm_kzalloc(&dc->ndev->dev, sizeof(*sor), GFP_KERNEL);
 455         if (!sor) {
 456                 err = -ENOMEM;
 457                 goto err_allocate;
 458         }
 459         sor->instance = sor_num;
 460
 461         if (np) {
 462                 if (np_sor && (of_device_is_available(np_sor) ||
 463                         (dc->out->type == TEGRA_DC_OUT_FAKE_DP))) {
 464                         of_address_to_resource(np_sor, 0,
 465                                 &of_sor_res);
 466                         res = &of_sor_res;
 467                 } else {
 468                         err = -EINVAL;
 469                         goto err_free_sor;
 470                 }
 471         } else {
 472                 res = platform_get_resource_byname(dc->ndev,
 473                         IORESOURCE_MEM, res_name);
 474                 if (!res) {
 475                         dev_err(&dc->ndev->dev,
 476                                 "sor: no mem resource\n");
 477                         err = -ENOENT;
 478                         goto err_free_sor;
 479                 }
 480         }
 481
 482         base_res = devm_request_mem_region(&dc->ndev->dev,
 483                 res->start, resource_size(res),
 484                 dc->ndev->name);
 485         if (!base_res) {
 486                 dev_err(&dc->ndev->dev, "sor: request_mem_region failed\n");
 487                 err = -EBUSY;
 488                 goto err_free_sor;
 489         }
 490
 491         base = devm_ioremap(&dc->ndev->dev,
 492                         res->start, resource_size(res));
 493         if (!base) {
 494                 dev_err(&dc->ndev->dev, "sor: registers can't be mapped\n");
 495                 err = -ENOENT;
 496                 goto err_release_resource_reg;
 497         }
 498
 499         clk = clk_get(NULL, res_name);
 500         if (IS_ERR_OR_NULL(clk)) {
 501                 dev_err(&dc->ndev->dev, "sor: can't get clock\n");
 502                 err = -ENOENT;
 503                 goto err_iounmap_reg;
 504         }
 505
 506 #ifndef CONFIG_ARCH_TEGRA_12x_SOC
 507         safe_clk = clk_get(NULL, "sor_safe");
 508         if (IS_ERR_OR_NULL(safe_clk)) {
 509                 dev_err(&dc->ndev->dev, "sor: can't get safe clock\n");
 510                 err = -ENOENT;
 511                 goto err_safe;
 512         }
 513 #ifndef CONFIG_TEGRA_NVDISPLAY
 514         if (!strcmp(res_name, "sor1")) {
 515                 brick_clk = clk_get(NULL, "sor1_brick");
 516                 if (IS_ERR_OR_NULL(brick_clk)) {
 517                         dev_err(&dc->ndev->dev, "sor: can't get brick clock\n");
 518                         err = -ENOENT;
 519                         goto err_brick;
 520                 }
 521                 src_clk = clk_get(NULL, "sor1_src");
 522                 if (IS_ERR_OR_NULL(src_clk)) {
 523                         dev_err(&dc->ndev->dev, "sor: can't get src clock\n");
 524                         err = -ENOENT;
 525                         goto err_src;
 526                 }
 527         }
 528 #endif
 529 #endif
 530
 531         for (i = 0; i < sizeof(sor->xbar_ctrl)/sizeof(u32); i++)
 532                 sor->xbar_ctrl[i] = i;
 533         if (np_sor && of_device_is_available(np_sor))
 534                 of_property_read_u32_array(np_sor, "nvidia,xbar-ctrl",
 535                         sor->xbar_ctrl, sizeof(sor->xbar_ctrl)/sizeof(u32));
 536
 537         sor->dc = dc;
 538         sor->base = base;
 539         sor->res = res;
 540         sor->base_res = base_res;
 541         sor->sor_clk = clk;
 542         sor->safe_clk = safe_clk;
 543         sor->brick_clk = brick_clk;
 544         sor->src_switch_clk = src_clk;
 545         sor->link_cfg = cfg;
 546         sor->portnum = 0;
 547         sor->sor_state = SOR_DETACHED;
 548
 549         tegra_dc_sor_debug_create(sor, res_name);
 550         of_node_put(np_sor);
 551
 552         return sor;
 553
 554 err_src: __maybe_unused
 555         clk_put(brick_clk);
 556 err_brick: __maybe_unused
 557         clk_put(safe_clk);
 558 err_safe: __maybe_unused
 559         clk_put(clk);
 560 err_iounmap_reg:
 561         devm_iounmap(&dc->ndev->dev, base);
 562 err_release_resource_reg:
 563         devm_release_mem_region(&dc->ndev->dev,
 564                 res->start, resource_size(res));
 565         if (!np_sor || !of_device_is_available(np_sor))
 566                 release_resource(res);
 567 err_free_sor:
 568         devm_kfree(&dc->ndev->dev, sor);
 569 err_allocate:
 570         of_node_put(np_sor);
 571         return ERR_PTR(err);
 572 }
 573
 574 int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
 575 {
 576         u32 reg_val;
 577         u32 orig_val;
 578
 579         orig_val = tegra_sor_readl(sor, NV_SOR_PWR);
 580
 581         reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU :
 582                 NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */
 583
 584         if (reg_val == orig_val)
 585                 return 0;       /* No update needed */
 586
 587         reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER;
 588         tegra_sor_writel(sor, NV_SOR_PWR, reg_val);
 589
 590         /* Poll to confirm it is done */
 591         if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
 592                         NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
 593                         NV_SOR_PWR_SETTING_NEW_DONE,
 594                         100, TEGRA_SOR_TIMEOUT_MS)) {
 595                 dev_err(&sor->dc->ndev->dev,
 596                         "dc timeout waiting for SOR_PWR = NEW_DONE\n");
 597                 return -EFAULT;
 598         }
 599         return 0;
 600 }
 601
 602
 603 void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor)
 604 {
 605         struct device_node *np_sor = sor->instance ?
 606                 of_find_node_by_path(SOR1_NODE) :
 607                 of_find_node_by_path(SOR_NODE);
 608
 609         clk_put(sor->sor_clk);
 610         if (sor->safe_clk)
 611                 clk_put(sor->safe_clk);
 612         if (sor->brick_clk)
 613                 clk_put(sor->brick_clk);
 614         if (sor->src_switch_clk)
 615                 clk_put(sor->src_switch_clk);
 616         devm_iounmap(&sor->dc->ndev->dev, sor->base);
 617         devm_release_mem_region(&sor->dc->ndev->dev,
 618                 sor->res->start, resource_size(sor->res));
 619
 620         if (!np_sor || !of_device_is_available(np_sor))
 621                 release_resource(sor->res);
 622         devm_kfree(&sor->dc->ndev->dev, sor);
 623         of_node_put(np_sor);
 624 }
 625
 626 void tegra_sor_tpg(struct tegra_dc_sor_data *sor, u32 tp, u32 n_lanes)
 627 {
 628         u32 const tbl[][2] = {
 629                 /* ansi8b/10b encoded, scrambled */
 630                 {1, 1}, /* no pattern, training not in progress */
 631                 {1, 0}, /* training pattern 1 */
 632                 {1, 0}, /* training pattern 2 */
 633                 {1, 0}, /* training pattern 3 */
 634         };
 635         u32 cnt;
 636         u32 val = 0;
 637
 638         for (cnt = 0; cnt < n_lanes; cnt++) {
 639                 u32 tp_shift = NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT * cnt;
 640                 val |= tp << tp_shift |
 641                         tbl[tp][0] << (tp_shift +
 642                         NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT) |
 643                         tbl[tp][1] << (tp_shift +
 644                         NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT);
 645         }
 646
 647         tegra_sor_writel(sor, NV_SOR_DP_TPG, val);
 648 }
 649
 650 void tegra_sor_port_enable(struct tegra_dc_sor_data *sor, bool enb)
 651 {
 652         tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
 653                         NV_SOR_DP_LINKCTL_ENABLE_YES,
 654                         (enb ? NV_SOR_DP_LINKCTL_ENABLE_YES :
 655                         NV_SOR_DP_LINKCTL_ENABLE_NO));
 656 }
 657
 658 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, bool ena,
 659         u8 training_pattern, const struct tegra_dc_dp_link_config *cfg)
 660 {
 661         u32 reg_val;
 662
 663         reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
 664
 665         if (ena)
 666                 reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES;
 667         else
 668                 reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO;
 669
 670         reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK;
 671         reg_val |= (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT);
 672
 673         if (cfg->enhanced_framing)
 674                 reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE;
 675
 676         tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
 677
 678         switch (training_pattern) {
 679         case TRAINING_PATTERN_1:
 680                 tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141);
 681                 break;
 682         case TRAINING_PATTERN_2:
 683         case TRAINING_PATTERN_3:
 684                 reg_val = (cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
 685                         0x43434343 : 0x42424242;
 686                 tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val);
 687                 break;
 688         default:
 689                 tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050);
 690                 break;
 691         }
 692 }
 693
 694 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
 695                                                         bool pu, bool is_lvds)
 696 {
 697         u32 reg_val;
 698
 699         /* SOR lane sequencer */
 700         if (pu)
 701                 reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 702                         NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 703                         NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU;
 704         else
 705                 reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 706                         NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 707                         NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD;
 708
 709         if (is_lvds)
 710                 reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
 711         else
 712                 reg_val |= 5 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
 713
 714         if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
 715                         NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY,
 716                         NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE,
 717                         100, TEGRA_SOR_SEQ_BUSY_TIMEOUT_MS)) {
 718                 dev_dbg(&sor->dc->ndev->dev,
 719                         "dp: timeout, sor lane sequencer busy\n");
 720                 return -EFAULT;
 721         }
 722
 723         tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val);
 724
 725         if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
 726                         NV_SOR_LANE_SEQ_CTL_SETTING_MASK,
 727                         NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE,
 728                         100, TEGRA_SOR_TIMEOUT_MS)) {
 729                 dev_dbg(&sor->dc->ndev->dev,
 730                         "dp: timeout, SOR lane sequencer power up/down\n");
 731                 return -EFAULT;
 732         }
 733         return 0;
 734 }
 735
 736 int tegra_sor_power_lanes(struct tegra_dc_sor_data *sor,
 737                                         u32 lane_count, bool pu)
 738 {
 739         u32 val = 0;
 740         u8 pd_txd_0_no = NV_SOR_DP_PADCTL_PD_TXD_0_NO,
 741                 pd_txd_2_no = NV_SOR_DP_PADCTL_PD_TXD_2_NO;
 742
 743 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_TEGRA_NVDISPLAY)
 744         pd_txd_0_no = NV_SOR_DP_PADCTL_PD_TXD_2_NO;
 745         pd_txd_2_no = NV_SOR_DP_PADCTL_PD_TXD_0_NO;
 746 #endif
 747
 748         if (pu) {
 749                 switch (lane_count) {
 750                 /* T210 boards need to swap lanes 0 and 2 - bug 1545275 */
 751                 case 4:
 752                         val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | pd_txd_2_no);
 753                         /* fall through */
 754                 case 2:
 755                         val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
 756                 case 1:
 757                         val |= pd_txd_0_no;
 758                         break;
 759                 default:
 760                         dev_dbg(&sor->dc->ndev->dev,
 761                                 "dp: invalid lane number %d\n", lane_count);
 762                         return -EFAULT;
 763                 }
 764
 765                 tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
 766                                                 NV_SOR_DP_PADCTL_PD_TXD_MASK, val);
 767                 tegra_dc_sor_set_lane_count(sor, lane_count);
 768         }
 769
 770         return tegra_dc_sor_enable_lane_sequencer(sor, pu, false);
 771 }
 772
 773 /* power on/off pad calibration logic */
 774 void tegra_sor_pad_cal_power(struct tegra_dc_sor_data *sor,
 775                                         bool power_up)
 776 {
 777         u32 val = power_up ? NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP :
 778                         NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
 779
 780         /* !!TODO: need to enable panel power through GPIO operations */
 781         /* Check bug 790854 for HW progress */
 782
 783         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
 784                                 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, val);
 785 }
 786
 787 void tegra_dc_sor_termination_cal(struct tegra_dc_sor_data *sor)
 788 {
 789         u32 termadj;
 790         u32 cur_try;
 791         u32 reg_val;
 792
 793         termadj = cur_try = 0x8;
 794
 795         tegra_sor_write_field(sor, NV_SOR_PLL1,
 796                 NV_SOR_PLL1_TMDS_TERMADJ_DEFAULT_MASK |
 797                 NV_SOR_PLL1_TMDS_TERM_ENABLE,
 798                 NV_SOR_PLL1_TMDS_TERM_ENABLE |
 799                 termadj << NV_SOR_PLL1_TMDS_TERMADJ_SHIFT);
 800
 801         while (cur_try) {
 802                 /* binary search the right value */
 803                 usleep_range(100, 200);
 804                 reg_val = tegra_sor_readl(sor, NV_SOR_PLL1);
 805
 806                 if (reg_val & NV_SOR_PLL1_TERM_COMPOUT_HIGH)
 807                         termadj -= cur_try;
 808                 cur_try >>= 1;
 809                 termadj += cur_try;
 810
 811                 tegra_sor_write_field(sor, NV_SOR_PLL1,
 812                         NV_SOR_PLL1_TMDS_TERMADJ_DEFAULT_MASK,
 813                         termadj << NV_SOR_PLL1_TMDS_TERMADJ_SHIFT);
 814         }
 815 }
 816
 817 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
 818         u32 pwm_dutycycle)
 819 {
 820         tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div);
 821         tegra_sor_writel(sor, NV_SOR_PWM_CTL,
 822                 (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) |
 823                 NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER);
 824
 825         if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL,
 826                         NV_SOR_PWM_CTL_SETTING_NEW_SHIFT,
 827                         NV_SOR_PWM_CTL_SETTING_NEW_DONE,
 828                         100, TEGRA_SOR_TIMEOUT_MS)) {
 829                 dev_dbg(&sor->dc->ndev->dev,
 830                         "dp: timeout while waiting for SOR PWM setting\n");
 831         }
 832 }
 833
 834 void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
 835         const struct tegra_dc_dp_link_config *cfg)
 836 {
 837         u32 reg_val;
 838
 839         BUG_ON(!cfg || !cfg->is_valid);
 840
 841         tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
 842
 843         tegra_dc_sor_set_dp_linkctl(sor, true, TRAINING_PATTERN_DISABLE, cfg);
 844         reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
 845         reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
 846         reg_val |= cfg->watermark;
 847         reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
 848         reg_val |= (cfg->active_count <<
 849                 NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
 850         reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
 851         reg_val |= (cfg->active_frac <<
 852                 NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
 853         if (cfg->activepolarity)
 854                 reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 855         else
 856                 reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 857         reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
 858                 NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
 859
 860         tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
 861
 862         /* program h/vblank sym */
 863         tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
 864                 NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, cfg->hblank_sym);
 865
 866         tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
 867                 NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, cfg->vblank_sym);
 868 }
 869
 870 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
 871 {
 872         tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
 873         tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 1);
 874         tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
 875 }
 876
 877 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
 878 {
 879         tegra_sor_writel(sor, NV_SOR_STATE0, 0);
 880         tegra_sor_writel(sor, NV_SOR_STATE0, 1);
 881         tegra_sor_writel(sor, NV_SOR_STATE0, 0);
 882 }
 883
 884 static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, bool up)
 885 {
 886         u32 reg_val;
 887         static void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 888         unsigned long timeout_jf;
 889
 890         if (tegra_platform_is_linsim())
 891                 return;
 892
 893         if (up) {
 894                 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
 895                         pmc_base + APBDEV_PMC_DPD_SAMPLE);
 896                 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
 897         }
 898
 899         reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 900         reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
 901                 APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
 902
 903         reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
 904                 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
 905                 APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
 906                 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
 907
 908         writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 909
 910         /* Polling */
 911         timeout_jf = jiffies + msecs_to_jiffies(10);
 912         do {
 913                 usleep_range(20, 40);
 914                 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
 915         } while (((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) &&
 916                 time_after(timeout_jf, jiffies));
 917
 918         if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0)
 919                 dev_err(&sor->dc->ndev->dev,
 920                         "PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
 921
 922         if (up)
 923                 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
 924                         pmc_base + APBDEV_PMC_DPD_SAMPLE);
 925 }
 926
 927 /* hdmi uses sor sequencer for pad power up */
 928 void tegra_sor_hdmi_pad_power_up(struct tegra_dc_sor_data *sor)
 929 {
 930         struct tegra_io_dpd hdmi_dpd = {
 931                 .name = "hdmi",
 932                 .io_dpd_reg_index = 0,
 933                 .io_dpd_bit = 28,
 934         };
 935         /* seamless */
 936         if (sor->dc->initialized)
 937                 return;
 938         tegra_io_dpd_disable(&hdmi_dpd);
 939         mdelay(50);
 940
 941         tegra_sor_write_field(sor, NV_SOR_PLL2,
 942                                 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE,
 943                                 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE);
 944         tegra_sor_write_field(sor, NV_SOR_PLL2,
 945                                 NV_SOR_PLL2_AUX2_MASK,
 946                                 NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN);
 947         tegra_sor_write_field(sor, NV_SOR_PLL2,
 948                                 NV_SOR_PLL2_AUX1_SEQ_MASK,
 949                                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE);
 950         tegra_sor_write_field(sor, NV_SOR_PLL2,
 951                                 NV_SOR_PLL2_AUX0_MASK,
 952                                 NV_SOR_PLL2_AUX0_SEQ_PLL_PULLDOWN_OVERRIDE);
 953         mdelay(100);
 954
 955         tegra_sor_write_field(sor, NV_SOR_PLL0, NV_SOR_PLL0_PWR_MASK,
 956                                                 NV_SOR_PLL0_PWR_ON);
 957         tegra_sor_write_field(sor, NV_SOR_PLL0, NV_SOR_PLL0_VCOPD_MASK,
 958                                                 NV_SOR_PLL0_VCOPD_RESCIND);
 959         mdelay(100);
 960
 961         tegra_sor_write_field(sor, NV_SOR_PLL2,
 962                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 963                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 964         tegra_sor_write_field(sor, NV_SOR_PLL2,
 965                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 966                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 967         tegra_sor_write_field(sor, NV_SOR_PLL2,
 968                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
 969                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 970         tegra_sor_write_field(sor, NV_SOR_PLL2,
 971                                 NV_SOR_PLL2_CLKGEN_MODE_MASK,
 972                                 NV_SOR_PLL2_CLKGEN_MODE_DP_TMDS);
 973         mdelay(100);
 974
 975         tegra_sor_write_field(sor, NV_SOR_PLL1,
 976                                 NV_SOR_PLL1_TMDS_TERM_ENABLE,
 977                                 NV_SOR_PLL1_TMDS_TERM_ENABLE);
 978 }
 979
 980 void tegra_sor_hdmi_pad_power_down(struct tegra_dc_sor_data *sor)
 981 {
 982         struct tegra_io_dpd hdmi_dpd = {
 983                 .name = "hdmi",
 984                 .io_dpd_reg_index = 0,
 985                 .io_dpd_bit = 28,
 986         };
 987
 988         tegra_sor_write_field(sor, NV_SOR_PLL2,
 989                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
 990                                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE);
 991         usleep_range(25, 30);
 992
 993         tegra_sor_write_field(sor, NV_SOR_PLL0, NV_SOR_PLL0_PWR_MASK |
 994                                 NV_SOR_PLL0_VCOPD_MASK, NV_SOR_PLL0_PWR_OFF |
 995                                 NV_SOR_PLL0_VCOPD_ASSERT);
 996         tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX1_SEQ_MASK |
 997                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 998                                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
 999                                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
1000         usleep_range(25, 30);
1001
1002         tegra_sor_write_field(sor, NV_SOR_PLL2,
1003                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1004                                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE);
1005
1006         tegra_io_dpd_enable(&hdmi_dpd);
1007 }
1008
1009 void tegra_sor_config_hdmi_clk(struct tegra_dc_sor_data *sor)
1010 {
1011         int flag = tegra_is_clk_enabled(sor->sor_clk);
1012
1013         if (sor->clk_type == TEGRA_SOR_MACRO_CLK)
1014                 return;
1015
1016         tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
1017                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
1018                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK);
1019         tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_G2_7);
1020
1021         /*
1022          * HW bug 1425607
1023          * Disable clocks to avoid glitch when switching
1024          * between safe clock and macro pll clock
1025          */
1026         if (flag)
1027                 clk_disable_unprepare(sor->sor_clk);
1028
1029         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
1030
1031         if (flag)
1032                 clk_prepare_enable(sor->sor_clk);
1033
1034         sor->clk_type = TEGRA_SOR_MACRO_CLK;
1035 }
1036
1037 /* The SOR power sequencer does not work for t124 so SW has to
1038    go through the power sequence manually */
1039 /* Power up steps from spec: */
1040 /* STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL */
1041 /* 1    1       1       1       1       1       1       1 */
1042 /* 2    1       1       1       1       1       0       1 */
1043 /* 3    1       1       0       1       1       0       1 */
1044 /* 4    1       0       0       0       0       0       1 */
1045 /* 5    0       0       0       0       0       0       1 */
1046 static void tegra_sor_pad_power_up(struct tegra_dc_sor_data *sor,
1047                                         bool is_lvds)
1048 {
1049         if (sor->power_is_up)
1050                 return;
1051
1052         /* step 1 */
1053         tegra_sor_write_field(sor, NV_SOR_PLL2,
1054                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
1055                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
1056                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
1057                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE |
1058                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
1059                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
1060         tegra_sor_write_field(sor, NV_SOR_PLL0,
1061                 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
1062                 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
1063                 NV_SOR_PLL0_PWR_OFF |
1064                 NV_SOR_PLL0_VCOPD_ASSERT);
1065         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
1066                 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
1067                 NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN);
1068
1069         /* step 2 */
1070         tegra_dc_sor_io_set_dpd(sor, true);
1071         usleep_range(5, 100);   /* sleep > 5us */
1072
1073         /* step 3 */
1074         tegra_sor_write_field(sor, NV_SOR_PLL2,
1075                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1076                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
1077         usleep_range(20, 100);  /* sleep > 20 us */
1078
1079         /* step 4 */
1080         tegra_sor_write_field(sor, NV_SOR_PLL0,
1081                 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
1082                 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
1083                 NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
1084         tegra_sor_write_field(sor, NV_SOR_PLL2,
1085                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
1086                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
1087         usleep_range(200, 1000);
1088
1089         /* step 5 */
1090         tegra_sor_write_field(sor, NV_SOR_PLL2,
1091                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
1092                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
1093
1094         sor->power_is_up = true;
1095 }
1096
1097 /* Powerdown steps from the spec: */
1098 /* STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL */
1099 /* 1    0       0       0       0       0       0       1 */
1100 /* 2    1       0       0       0       0       0       1 */
1101 /* 3    1       1       0       1       1       0       1 */
1102 /* 4    1       1       1       1       1       0       1 */
1103 /* 5    1       1       1       1       1       1       1 */
1104 static void tegra_dc_sor_power_down(struct tegra_dc_sor_data *sor)
1105 {
1106         if (!sor->power_is_up)
1107                 return;
1108
1109         /* step 1 -- not necessary */
1110
1111         /* step 2 */
1112         tegra_sor_write_field(sor, NV_SOR_PLL2,
1113                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
1114                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE);
1115         udelay(5);      /* sleep > 5us */
1116
1117         /* step 3 */
1118         tegra_sor_write_field(sor, NV_SOR_PLL0,
1119                 NV_SOR_PLL0_PWR_MASK | /* PDPLL */
1120                 NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
1121                 NV_SOR_PLL0_PWR_OFF | NV_SOR_PLL0_VCOPD_ASSERT);
1122         tegra_sor_write_field(sor, NV_SOR_PLL2,
1123                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
1124                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
1125         udelay(5);      /* sleep > 5us */
1126
1127         /* step 4 */
1128         tegra_sor_write_field(sor, NV_SOR_PLL2,
1129                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1130                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE);
1131         udelay(5);
1132
1133         /* step 5 */
1134         tegra_dc_sor_io_set_dpd(sor, false);
1135
1136         sor->power_is_up = false;
1137 }
1138
1139
1140 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
1141                                                 bool is_lvds)
1142 {
1143         struct tegra_dc *dc = sor->dc;
1144         const struct tegra_dc_mode *dc_mode = &dc->mode;
1145         int head_num = dc->ctrl_num;
1146         u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
1147         u32 vtotal, htotal;
1148         u32 vsync_end, hsync_end;
1149         u32 vblank_end, hblank_end;
1150         u32 vblank_start, hblank_start;
1151         int out_type = dc->out->type;
1152
1153         if (out_type == TEGRA_DC_OUT_HDMI)
1154                 reg_val |= NV_SOR_STATE1_ASY_PROTOCOL_SINGLE_TMDS_A;
1155         else if ((out_type == TEGRA_DC_OUT_DP) ||
1156                 (out_type == TEGRA_DC_OUT_NVSR_DP) ||
1157                 (out_type == TEGRA_DC_OUT_FAKE_DP))
1158                 reg_val |= NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
1159         else
1160                 reg_val |= NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM;
1161
1162         reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE |
1163                 NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER;
1164
1165         if (dc_mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1166                 reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
1167         else
1168                 reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE;
1169
1170         if (dc_mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1171                 reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
1172         else
1173                 reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE;
1174
1175         reg_val |= (dc->out->depth > 18 || !dc->out->depth) ?
1176                 NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
1177                 NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
1178
1179         tegra_sor_writel(sor, NV_SOR_STATE1, reg_val);
1180
1181         /* Skipping programming NV_HEAD_STATE0, assuming:
1182            interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */
1183
1184         BUG_ON(!dc_mode);
1185         vtotal = dc_mode->v_sync_width + dc_mode->v_back_porch +
1186                 dc_mode->v_active + dc_mode->v_front_porch;
1187         htotal = dc_mode->h_sync_width + dc_mode->h_back_porch +
1188                 dc_mode->h_active + dc_mode->h_front_porch;
1189         tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
1190                 vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
1191                 htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
1192
1193         vsync_end = dc_mode->v_sync_width - 1;
1194         hsync_end = dc_mode->h_sync_width - 1;
1195         tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
1196                 vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
1197                 hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
1198
1199         vblank_end = vsync_end + dc_mode->v_back_porch;
1200         hblank_end = hsync_end + dc_mode->h_back_porch;
1201         tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
1202                 vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
1203                 hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
1204
1205         vblank_start = vblank_end + dc_mode->v_active;
1206         hblank_start = hblank_end + dc_mode->h_active;
1207         tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
1208                 vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
1209                 hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
1210
1211         /* TODO: adding interlace mode support */
1212         tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
1213
1214         tegra_sor_write_field(sor, NV_SOR_CSTM,
1215                 NV_SOR_CSTM_ROTCLK_DEFAULT_MASK |
1216                 NV_SOR_CSTM_LVDS_EN_ENABLE,
1217                 2 << NV_SOR_CSTM_ROTCLK_SHIFT |
1218                 is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
1219                 NV_SOR_CSTM_LVDS_EN_DISABLE);
1220
1221         tegra_dc_sor_config_pwm(sor, 1024, 1024);
1222
1223         tegra_dc_sor_update(sor);
1224 }
1225
1226 static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
1227 {
1228         struct tegra_dc *dc = sor->dc;
1229         u32 reg_val;
1230
1231         tegra_dc_get(dc);
1232
1233         reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1234 #ifndef CONFIG_TEGRA_NVDISPLAY
1235         tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1236 #else
1237         tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1238 #endif /* CONFIG_TEGRA_NVDISPLAY */
1239
1240         if (tegra_platform_is_fpga()) {
1241                 tegra_dc_writel(dc, 0, DC_DISP_DISP_CLOCK_CONTROL);
1242                 tegra_dc_writel(dc, 0xe, DC_DISP_DC_MCCIF_FIFOCTRL);
1243         }
1244
1245 #ifndef CONFIG_TEGRA_NVDISPLAY
1246         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
1247 #endif
1248
1249         /* Enable DC */
1250         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1251         tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
1252
1253         tegra_dc_put(dc);
1254 }
1255
1256 static void tegra_dc_sor_attach_lvds(struct tegra_dc_sor_data *sor)
1257 {
1258         /* Set head owner */
1259         tegra_sor_write_field(sor, NV_SOR_STATE1,
1260                 NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK,
1261                 NV_SOR_STATE1_ASY_SUBOWNER_BOTH);
1262
1263         tegra_dc_sor_update(sor);
1264
1265         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1266                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1267                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1268                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1269         tegra_dc_sor_super_update(sor);
1270
1271         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1272                         NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
1273                         NV_SOR_TEST_ATTACHED_TRUE,
1274                         100, TEGRA_SOR_TIMEOUT_MS)) {
1275                 dev_err(&sor->dc->ndev->dev,
1276                         "dc timeout waiting for ATTACHED = TRUE\n");
1277                 return;
1278         }
1279
1280         /* OR mode: normal */
1281         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1282                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1283                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1284                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1285         tegra_dc_sor_super_update(sor);
1286
1287         /* then awake */
1288         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1289                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1290                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1291                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1292         tegra_dc_sor_super_update(sor);
1293
1294 }
1295
1296 static void tegra_sor_dp_cal(struct tegra_dc_sor_data *sor)
1297 {
1298         tegra_sor_pad_cal_power(sor, true);
1299
1300         tegra_sor_write_field(sor, NV_SOR_PLL2,
1301                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
1302                 NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
1303         usleep_range(20, 100);
1304
1305         tegra_sor_write_field(sor, NV_SOR_PLL3,
1306                 NV_SOR_PLL3_PLLVDD_MODE_MASK,
1307                 NV_SOR_PLL3_PLLVDD_MODE_V3_3);
1308         tegra_sor_writel(sor, NV_SOR_PLL0,
1309                 0x1 << NV_SOR_PLL0_ICHPMP_SHFIT |
1310                 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT |
1311                 NV_SOR_PLL0_PLLREG_LEVEL_V45 |
1312                 NV_SOR_PLL0_RESISTORSEL_EXT |
1313                 NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
1314         tegra_sor_write_field(sor, NV_SOR_PLL2,
1315                 NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
1316                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1317                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
1318                 NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
1319                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
1320         tegra_sor_writel(sor, NV_SOR_PLL1,
1321                 NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE |
1322                 0x0 << NV_SOR_PLL1_LVDSCM_SHIFT);
1323
1324         if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2,
1325                         NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1326                         NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
1327                         100, TEGRA_SOR_TIMEOUT_MS)) {
1328                 dev_err(&sor->dc->ndev->dev, "DP failed to lock PLL\n");
1329                 return;
1330         }
1331
1332         tegra_sor_write_field(sor, NV_SOR_PLL2,
1333                 NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
1334                 NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
1335                 NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
1336
1337         tegra_dc_sor_termination_cal(sor);
1338
1339         tegra_sor_pad_cal_power(sor, false);
1340 }
1341
1342 static inline void tegra_sor_reset(struct tegra_dc_sor_data *sor)
1343 {
1344         if (tegra_platform_is_linsim())
1345                 return;
1346
1347         tegra_periph_reset_assert(sor->sor_clk);
1348         mdelay(2);
1349         tegra_periph_reset_deassert(sor->sor_clk);
1350         mdelay(1);
1351 }
1352
1353 void tegra_sor_config_xbar(struct tegra_dc_sor_data *sor)
1354 {
1355         u32 val = 0, mask = 0, shift = 0;
1356         u32 i = 0;
1357
1358         mask = (NV_SOR_XBAR_BYPASS_MASK | NV_SOR_XBAR_LINK_SWAP_MASK);
1359         for (i = 0, shift = 2; i < sizeof(sor->xbar_ctrl)/sizeof(u32);
1360                 shift += 3, i++) {
1361                 mask |= NV_SOR_XBAR_LINK_SWAP_MASK << shift;
1362                 val |= sor->xbar_ctrl[i] << shift;
1363         }
1364
1365         tegra_sor_write_field(sor, NV_SOR_XBAR_CTRL, mask, val);
1366         tegra_sor_writel(sor, NV_SOR_XBAR_POL, 0);
1367 }
1368
1369 void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
1370 {
1371         tegra_sor_reset(sor);
1372
1373         tegra_sor_config_safe_clk(sor);
1374         tegra_sor_clk_enable(sor);
1375
1376         tegra_sor_dp_cal(sor);
1377
1378         tegra_sor_pad_power_up(sor, false);
1379 }
1380
1381 static void tegra_dc_sor_enable_sor(struct tegra_dc_sor_data *sor, bool enable)
1382 {
1383         struct tegra_dc *dc = sor->dc;
1384         int sor_num = sor->instance;
1385         u32 reg_val = tegra_dc_readl(sor->dc, DC_DISP_DISP_WIN_OPTIONS);
1386         u32 enb = sor_num ? SOR1_ENABLE : SOR_ENABLE;
1387
1388         /* Do not disable SOR during seamless boot */
1389         if (sor->dc->initialized && !enable)
1390                 return;
1391
1392         if (sor->dc->out->type == TEGRA_DC_OUT_HDMI)
1393                 enb = sor_num ? SOR1_ENABLE : SOR_ENABLE;
1394
1395         if (dc->out->type == TEGRA_DC_OUT_HDMI)
1396                 enb |= SOR1_TIMING_CYA;
1397
1398         reg_val = enable ? reg_val | enb : reg_val & ~enb;
1399
1400         tegra_dc_writel(dc, reg_val, DC_DISP_DISP_WIN_OPTIONS);
1401 }
1402
1403 void tegra_sor_start_dc(struct tegra_dc_sor_data *sor)
1404 {
1405         struct tegra_dc *dc = sor->dc;
1406         u32 reg_val;
1407
1408         if (sor->sor_state == SOR_ATTACHED)
1409                 return;
1410
1411         tegra_dc_get(dc);
1412         reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1413 #ifndef CONFIG_TEGRA_NVDISPLAY
1414         tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1415 #else
1416         tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1417 #endif /* CONFIG_TEGRA_NVDISPLAY */
1418         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1419         tegra_dc_sor_enable_sor(sor, true);
1420
1421         tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
1422         tegra_dc_put(dc);
1423 }
1424
1425 void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
1426 {
1427         struct tegra_dc *dc = sor->dc;
1428         u32 reg_val;
1429
1430         if (sor->sor_state == SOR_ATTACHED)
1431                 return;
1432
1433         tegra_dc_get(dc);
1434
1435         reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1436 #ifndef CONFIG_TEGRA_NVDISPLAY
1437         tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1438 #else
1439         tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1440 #endif /* CONFIG_TEGRA_NVDISPLAY */
1441
1442         tegra_dc_sor_config_panel(sor, false);
1443
1444         /* WAR for bug 1428181 */
1445         tegra_dc_sor_enable_sor(sor, true);
1446         tegra_dc_sor_enable_sor(sor, false);
1447
1448 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
1449         /* Awake request */
1450         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1451                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1452                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1453                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1454         tegra_dc_sor_super_update(sor);
1455
1456         tegra_dc_sor_enable_dc(sor);
1457
1458         tegra_dc_sor_enable_sor(sor, true);
1459
1460         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1461                 NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
1462                 NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE,
1463                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1464                 dev_err(&dc->ndev->dev,
1465                         "dc timeout waiting for OPMOD = AWAKE\n");
1466         }
1467 #else
1468         tegra_dc_sor_update(sor);
1469
1470         /* Sleep request */
1471         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1472                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1473                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1474                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1475         tegra_dc_sor_super_update(sor);
1476
1477         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1478                 NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
1479                 NV_SOR_TEST_ATTACHED_TRUE,
1480                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1481                 dev_err(&dc->ndev->dev,
1482                         "dc timeout waiting for ATTACH = TRUE\n");
1483         }
1484
1485         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1486                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1487                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1488                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1489         tegra_dc_sor_super_update(sor);
1490
1491         tegra_dc_sor_enable_dc(sor);
1492
1493         tegra_dc_sor_enable_sor(sor, true);
1494
1495         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1496                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1497                 NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
1498                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1499         tegra_dc_sor_super_update(sor);
1500
1501 #endif
1502
1503         tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
1504         tegra_dc_put(dc);
1505
1506         sor->sor_state = SOR_ATTACHED;
1507 }
1508
1509 static struct tegra_dc_mode min_mode = {
1510         .h_ref_to_sync = 0,
1511         .v_ref_to_sync = 1,
1512         .h_sync_width = 1,
1513         .v_sync_width = 1,
1514         .h_back_porch = 20,
1515         .v_back_porch = 0,
1516         .h_active = 16,
1517         .v_active = 16,
1518         .h_front_porch = 1,
1519         .v_front_porch = 2,
1520 };
1521
1522 /* Disable windows and set minimum raster timings */
1523 static void
1524 tegra_dc_sor_disable_win_short_raster(struct tegra_dc *dc, int *dc_reg_ctx)
1525 {
1526         int selected_windows, i;
1527
1528         if (tegra_platform_is_linsim())
1529                 return;
1530         selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
1531
1532         /* Store and clear window options */
1533         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1534                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1535                         DC_CMD_DISPLAY_WINDOW_HEADER);
1536                 dc_reg_ctx[i] = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
1537                 tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1538                 tegra_dc_writel(dc, WIN_A_ACT_REQ << i, DC_CMD_STATE_CONTROL);
1539         }
1540
1541         tegra_dc_writel(dc, selected_windows, DC_CMD_DISPLAY_WINDOW_HEADER);
1542
1543         /* Store current raster timings and set minimum timings */
1544         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
1545         tegra_dc_writel(dc, min_mode.h_ref_to_sync |
1546                 (min_mode.v_ref_to_sync << 16), DC_DISP_REF_TO_SYNC);
1547
1548         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_SYNC_WIDTH);
1549         tegra_dc_writel(dc, min_mode.h_sync_width |
1550                 (min_mode.v_sync_width << 16), DC_DISP_SYNC_WIDTH);
1551
1552         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_BACK_PORCH);
1553         tegra_dc_writel(dc, min_mode.h_back_porch |
1554                 ((min_mode.v_back_porch - min_mode.v_ref_to_sync) << 16),
1555                 DC_DISP_BACK_PORCH);
1556
1557         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_FRONT_PORCH);
1558         tegra_dc_writel(dc, min_mode.h_front_porch |
1559                 ((min_mode.v_front_porch + min_mode.v_ref_to_sync) << 16),
1560                 DC_DISP_FRONT_PORCH);
1561
1562         dc_reg_ctx[i++] = tegra_dc_readl(dc, DC_DISP_DISP_ACTIVE);
1563         tegra_dc_writel(dc, min_mode.h_active | (min_mode.v_active << 16),
1564                         DC_DISP_DISP_ACTIVE);
1565
1566         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1567 }
1568
1569 /* Restore previous windows status and raster timings */
1570 static void
1571 tegra_dc_sor_restore_win_and_raster(struct tegra_dc *dc, int *dc_reg_ctx)
1572 {
1573         int selected_windows, i;
1574
1575         if (tegra_platform_is_linsim())
1576                 return;
1577
1578         selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
1579
1580         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1581                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1582                         DC_CMD_DISPLAY_WINDOW_HEADER);
1583                 tegra_dc_writel(dc, dc_reg_ctx[i], DC_WIN_WIN_OPTIONS);
1584                 tegra_dc_writel(dc, WIN_A_ACT_REQ << i, DC_CMD_STATE_CONTROL);
1585         }
1586
1587         tegra_dc_writel(dc, selected_windows, DC_CMD_DISPLAY_WINDOW_HEADER);
1588
1589         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_REF_TO_SYNC);
1590         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_SYNC_WIDTH);
1591         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_BACK_PORCH);
1592         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_FRONT_PORCH);
1593         tegra_dc_writel(dc, dc_reg_ctx[i++], DC_DISP_DISP_ACTIVE);
1594
1595         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1596 }
1597
1598 void tegra_sor_stop_dc(struct tegra_dc_sor_data *sor)
1599 {
1600         struct tegra_dc *dc = sor->dc;
1601
1602         tegra_dc_get(dc);
1603
1604 #if defined(CONFIG_TEGRA_NVDISPLAY)
1605         /*SOR should be attached if the Display command != STOP */
1606         /* Stop DC */
1607         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1608         tegra_dc_enable_general_act(dc);
1609
1610         /* Stop DC->SOR path */
1611         tegra_dc_sor_enable_sor(sor, false);
1612 #else
1613         /* Stop DC->SOR path */
1614         tegra_dc_sor_enable_sor(sor, false);
1615         tegra_dc_enable_general_act(dc);
1616
1617         /* Stop DC */
1618         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1619 #endif
1620         tegra_dc_enable_general_act(dc);
1621
1622         tegra_dc_put(dc);
1623 }
1624
1625 void tegra_dc_sor_pre_detach(struct tegra_dc_sor_data *sor)
1626 {
1627         struct tegra_dc *dc = sor->dc;
1628
1629         if (sor->sor_state != SOR_ATTACHED)
1630                 return;
1631
1632         tegra_dc_get(dc);
1633
1634 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)
1635         /* Sleep mode */
1636         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1637                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1638                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1639                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1640         tegra_dc_sor_super_update(sor);
1641 #else
1642         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1643                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
1644                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1645                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1646         tegra_dc_sor_super_update(sor);
1647
1648         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1649                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1650                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1651                 NV_SOR_SUPER_STATE1_ATTACHED_YES);
1652         tegra_dc_sor_super_update(sor);
1653 #endif
1654
1655         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1656                 NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
1657                 NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP,
1658                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1659                 dev_err(&dc->ndev->dev,
1660                         "dc timeout waiting for OPMOD = SLEEP\n");
1661         }
1662
1663         tegra_dc_sor_disable_win_short_raster(dc, sor->dc_reg_ctx);
1664
1665         sor->sor_state = SOR_DETACHING;
1666         tegra_dc_put(dc);
1667 }
1668
1669 void tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
1670 {
1671         struct tegra_dc *dc = sor->dc;
1672         unsigned long dc_int_mask;
1673
1674         if (sor->sor_state == SOR_DETACHED)
1675                 return;
1676
1677         tegra_dc_get(dc);
1678
1679         /* Mask DC interrupts during the 2 dummy frames required for detach */
1680         dc_int_mask = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1681         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1682
1683         if (sor->sor_state != SOR_DETACHING)
1684                 tegra_dc_sor_pre_detach(sor);
1685
1686         tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
1687                 NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1688                 NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
1689                 NV_SOR_SUPER_STATE1_ATTACHED_NO);
1690         tegra_dc_sor_super_update(sor);
1691
1692         if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
1693                 NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
1694                 NV_SOR_TEST_ATTACHED_FALSE,
1695                 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1696                 dev_err(&dc->ndev->dev,
1697                         "dc timeout waiting for ATTACH = FALSE\n");
1698         }
1699
1700         tegra_sor_writel(sor, NV_SOR_STATE1,
1701                 NV_SOR_STATE1_ASY_OWNER_NONE |
1702                 NV_SOR_STATE1_ASY_SUBOWNER_NONE |
1703                 NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM);
1704         tegra_dc_sor_update(sor);
1705
1706         tegra_sor_stop_dc(sor);
1707
1708         tegra_dc_sor_restore_win_and_raster(dc, sor->dc_reg_ctx);
1709
1710         tegra_dc_writel(dc, dc_int_mask, DC_CMD_INT_MASK);
1711         sor->sor_state = SOR_DETACHED;
1712         tegra_dc_put(dc);
1713 }
1714
1715 static void tegra_sor_config_lvds_clk(struct tegra_dc_sor_data *sor)
1716 {
1717         int flag = tegra_is_clk_enabled(sor->sor_clk);
1718
1719         if (sor->clk_type == TEGRA_SOR_MACRO_CLK)
1720                 return;
1721
1722         tegra_sor_writel(sor, NV_SOR_CLK_CNTRL,
1723                 NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK |
1724                 NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS);
1725
1726         tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
1727
1728         /*
1729          * HW bug 1425607
1730          * Disable clocks to avoid glitch when switching
1731          * between safe clock and macro pll clock
1732          */
1733         if (flag)
1734                 clk_disable_unprepare(sor->sor_clk);
1735
1736         tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 1);
1737
1738         if (flag)
1739                 clk_prepare_enable(sor->sor_clk);
1740
1741         sor->clk_type = TEGRA_SOR_MACRO_CLK;
1742 }
1743 void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
1744         bool balanced, bool conforming)
1745 {
1746         u32 reg_val;
1747
1748         tegra_dc_sor_enable_dc(sor);
1749         tegra_dc_sor_config_panel(sor, true);
1750         tegra_dc_writel(sor->dc, 0x9f00, DC_CMD_STATE_CONTROL);
1751         tegra_dc_writel(sor->dc, 0x9f, DC_CMD_STATE_CONTROL);
1752
1753         tegra_dc_writel(sor->dc, SOR_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1754
1755         tegra_sor_write_field(sor, NV_SOR_PLL3,
1756                 NV_SOR_PLL3_PLLVDD_MODE_MASK,
1757                 NV_SOR_PLL3_PLLVDD_MODE_V1_8);
1758
1759         tegra_sor_writel(sor, NV_SOR_PLL1,
1760                 NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE);
1761         tegra_sor_write_field(sor, NV_SOR_PLL2,
1762                 NV_SOR_PLL2_AUX1_SEQ_MASK |
1763                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
1764                 NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
1765                 NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
1766
1767
1768         reg_val = NV_SOR_LVDS_LINKACTB_DISABLE |
1769                 NV_SOR_LVDS_LINKACTA_ENABLE |
1770                 NV_SOR_LVDS_UPPER_TRUE |
1771                 NV_SOR_LVDS_PD_TXCB_DISABLE |
1772                 NV_SOR_LVDS_PD_TXDB_3_DISABLE |
1773                 NV_SOR_LVDS_PD_TXDB_2_DISABLE |
1774                 NV_SOR_LVDS_PD_TXDB_1_DISABLE |
1775                 NV_SOR_LVDS_PD_TXDB_0_DISABLE |
1776                 NV_SOR_LVDS_PD_TXDA_2_ENABLE |
1777                 NV_SOR_LVDS_PD_TXDA_1_ENABLE |
1778                 NV_SOR_LVDS_PD_TXDA_0_ENABLE;
1779         if (!conforming && (sor->dc->pdata->default_out->depth == 18))
1780                 reg_val |= (NV_SOR_LVDS_PD_TXDA_3_DISABLE);
1781
1782         tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
1783         tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
1784                 0x40404040);
1785
1786 #if 0
1787         tegra_sor_write_field(sor, NV_SOR_LVDS,
1788                 NV_SOR_LVDS_BALANCED_DEFAULT_MASK,
1789                 balanced ? NV_SOR_LVDS_BALANCED_ENABLE :
1790                 NV_SOR_LVDS_BALANCED_DISABLE);
1791         tegra_sor_write_field(sor, NV_SOR_LVDS,
1792                 NV_SOR_LVDS_ROTDAT_DEFAULT_MASK,
1793                 conforming ? 6 << NV_SOR_LVDS_ROTDAT_SHIFT :
1794                 0 << NV_SOR_LVDS_ROTDAT_SHIFT);
1795 #endif
1796
1797         tegra_sor_pad_power_up(sor, true);
1798
1799         tegra_sor_writel(sor, NV_SOR_SEQ_INST(0),
1800                 NV_SOR_SEQ_INST_LANE_SEQ_RUN |
1801                 NV_SOR_SEQ_INST_HALT_TRUE);
1802         tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum),
1803                 NV_SOR_DP_SPARE_SEQ_ENABLE_YES |
1804                 NV_SOR_DP_SPARE_PANEL_INTERNAL |
1805                 NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK);
1806
1807         tegra_dc_sor_enable_lane_sequencer(sor, true, true);
1808
1809         tegra_sor_config_lvds_clk(sor);
1810
1811         tegra_dc_sor_attach_lvds(sor);
1812
1813         if ((tegra_dc_sor_set_power_state(sor, 1))) {
1814                 dev_err(&sor->dc->ndev->dev,
1815                         "Failed to power up SOR sequencer for LVDS\n");
1816                 return;
1817         }
1818
1819         if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
1820                         NV_SOR_PWR_MODE_DEFAULT_MASK,
1821                         NV_SOR_PWR_MODE_NORMAL,
1822                         100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
1823                 dev_err(&sor->dc->ndev->dev,
1824                         "dc timeout waiting for ATTACHED = TRUE\n");
1825                 return;
1826         }
1827 }
1828
1829 void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds)
1830 {
1831         struct tegra_dc *dc = sor->dc;
1832
1833         tegra_sor_config_safe_clk(sor);
1834
1835         tegra_dc_sor_power_down(sor);
1836
1837         /* Power down DP lanes */
1838         if (!is_lvds && tegra_sor_power_lanes(sor, 4, false)) {
1839                 dev_err(&dc->ndev->dev,
1840                         "Failed to power down dp lanes\n");
1841                 return;
1842         }
1843
1844         if (tegra_platform_is_linsim())
1845                 return;
1846
1847         tegra_sor_clk_disable(sor);
1848         /* Reset SOR clk */
1849         tegra_periph_reset_assert(sor->sor_clk);
1850 }
1851
1852 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, bool is_int)
1853 {
1854         u32 reg_val;
1855
1856         reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum));
1857         if (is_int)
1858                 reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL;
1859         else
1860                 reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL;
1861
1862         reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
1863                 NV_SOR_DP_SPARE_SEQ_ENABLE_YES;
1864
1865         tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val);
1866
1867         if (sor->dc->out->type == TEGRA_DC_OUT_HDMI)
1868                 tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
1869                                 NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_ENABLE,
1870                                 NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_ENABLE);
1871 }
1872
1873 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
1874                                    u8 *lane_count)
1875 {
1876         u32 reg_val;
1877
1878         reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
1879         *link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK)
1880                 >> NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT;
1881         reg_val = tegra_sor_readl(sor,
1882                 NV_SOR_DP_LINKCTL(sor->portnum));
1883
1884         switch (reg_val & NV_SOR_DP_LINKCTL_LANECOUNT_MASK) {
1885         case NV_SOR_DP_LINKCTL_LANECOUNT_ZERO:
1886                 *lane_count = 0;
1887                 break;
1888         case NV_SOR_DP_LINKCTL_LANECOUNT_ONE:
1889                 *lane_count = 1;
1890                 break;
1891         case NV_SOR_DP_LINKCTL_LANECOUNT_TWO:
1892                 *lane_count = 2;
1893                 break;
1894         case NV_SOR_DP_LINKCTL_LANECOUNT_FOUR:
1895                 *lane_count = 4;
1896                 break;
1897         default:
1898                 dev_err(&sor->dc->ndev->dev, "Unknown lane count\n");
1899         }
1900 }
1901
1902 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
1903 {
1904         WARN_ON(sor->sor_state == SOR_ATTACHED);
1905
1906         tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
1907                 NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,
1908                 link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
1909
1910         /* It can take upto 200us for PLLs in analog macro to settle */
1911         udelay(300);
1912 }
1913
1914 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
1915 {
1916         u32 reg_lane_cnt = 0;
1917
1918         switch (lane_count) {
1919         case 0:
1920                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_ZERO;
1921                 break;
1922         case 1:
1923                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_ONE;
1924                 break;
1925         case 2:
1926                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_TWO;
1927                 break;
1928         case 4:
1929                 reg_lane_cnt = NV_SOR_DP_LINKCTL_LANECOUNT_FOUR;
1930                 break;
1931         default:
1932                 /* 0 should be handled earlier. */
1933                 dev_err(&sor->dc->ndev->dev, "dp: Invalid lane count %d\n",
1934                         lane_count);
1935                 return;
1936         }
1937
1938         tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
1939                                 NV_SOR_DP_LINKCTL_LANECOUNT_MASK,
1940                                 reg_lane_cnt);
1941 }
1942
1943 void tegra_sor_setup_clk(struct tegra_dc_sor_data *sor, struct clk *clk,
1944         bool is_lvds)
1945 {
1946         struct clk *dc_parent_clk;
1947         struct tegra_dc *dc = sor->dc;
1948
1949         if (tegra_platform_is_linsim())
1950                 return;
1951         if (clk == dc->clk) {
1952                 dc_parent_clk = clk_get_parent(clk);
1953                 BUG_ON(!dc_parent_clk);
1954
1955                 if (dc->mode.pclk != clk_get_rate(dc_parent_clk))
1956                         clk_set_rate(dc_parent_clk, dc->mode.pclk);
1957         }
1958 }
1959
1960 void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor)
1961 {
1962         const struct tegra_dc_dp_link_config *cfg = sor->link_cfg;
1963         u32 val = 0;
1964
1965         switch (cfg->lane_count) {
1966         /* T210 boards need to swap lanes 0 and 2 */
1967         case 4:
1968                 val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
1969 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_TEGRA_NVDISPLAY)
1970                         NV_SOR_DP_PADCTL_PD_TXD_0_NO);
1971 #else
1972                         NV_SOR_DP_PADCTL_PD_TXD_2_NO);
1973 #endif
1974                 /* fall through */
1975         case 2:
1976                 val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
1977         case 1:
1978 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_TEGRA_NVDISPLAY)
1979                 val |= NV_SOR_DP_PADCTL_PD_TXD_2_NO;
1980 #else
1981                 val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
1982 #endif
1983                 break;
1984         default:
1985                 dev_dbg(&sor->dc->ndev->dev,
1986                         "dp: invalid lane number %d\n", cfg->lane_count);
1987                 return;
1988         }
1989
1990         /* force lanes to output common mode voltage */
1991         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
1992                 (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
1993                 (val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
1994
1995         /* precharge for atleast 10us */
1996         usleep_range(20, 100);
1997
1998         /* fallback to normal operation */
1999         tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
2000                 (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0);
2001 }
2002
2003 void tegra_dc_sor_modeset_notifier(struct tegra_dc_sor_data *sor, bool is_lvds)
2004 {
2005         if (!sor->clk_type)
2006                 tegra_sor_config_safe_clk(sor);
2007
2008         tegra_sor_clk_enable(sor);
2009
2010         tegra_dc_sor_config_panel(sor, is_lvds);
2011         tegra_dc_sor_update(sor);
2012         tegra_dc_sor_super_update(sor);
2013
2014         tegra_sor_clk_disable(sor);
2015 }
2016